专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07436039B2 Gallium nitride semiconductor device 失效
标题翻译：氮化镓半导体器件
公开(公告)号：US07436039B2
公开(公告)日：2008-10-14
申请号：US11030554
申请日：2005-01-06
申请人： TingGang Zhu , Bryan S. Shelton , Marek K. Pabisz , Mark Gottfried , Linlin Liu , Milan Pophristic , Michael Murphy , Richard A. Stall
发明人： TingGang Zhu , Bryan S. Shelton , Marek K. Pabisz , Mark Gottfried , Linlin Liu , Milan Pophristic , Michael Murphy , Richard A. Stall
IPC分类号： H01L23/58
CPC分类号： H01L29/872 , H01L29/2003 , H01L29/475
摘要： A gallium nitride based semiconductor Schottky diode fabricated from a n+ doped GaN layer having a thickness between one and six microns disposed on a sapphire substrate; an n− doped GaN layer having a thickness greater than one micron disposed on said n+ GaN layer patterned into a plurality of elongated fingers and a metal layer disposed on the n− doped GaN layer and forming a Schottky junction therewith. The layer thicknesses and the length and width of the elongated fingers are optimized to achieve a device with breakdown voltage of greater than 500 volts, current capacity in excess of one ampere, and a forward voltage of less than three volts.
摘要翻译：由氮化镓基半导体肖特基二极管制成的n +掺杂GaN层，其厚度介于1微米与6微米之间，设置在蓝宝石衬底上; 设置在图案化成多个细长指状物的所述n + GaN层上的厚度大于1微米的n掺杂GaN层和设置在n掺杂GaN层上并与其形成肖特基结的金属层。优化了层厚度和细长指状物的长度和宽度，以实现具有大于500伏特的击穿电压，超过1安培的电流容量和小于3伏特的正向电压的器件。

2. 发明授权

US07116567B2 GaN semiconductor based voltage conversion device 有权
标题翻译：基于GaN半导体的电压转换装置
公开(公告)号：US07116567B2
公开(公告)日：2006-10-03
申请号：US11029266
申请日：2005-01-05
申请人： Bryan S. Shelton , Boris Peres , Daniel McGlynn
发明人： Bryan S. Shelton , Boris Peres , Daniel McGlynn
IPC分类号： H02H3/20
CPC分类号： H02M1/4225 , H02M3/155 , H02M7/2176 , Y02B70/126 , Y02B70/1483
摘要： A converter is provided having an AC input and a DC output. The converter includes a rectifier that receives the AC input and that provides a rectifier output, a series connected current to magnetic field energy storage device and current interrupter connected across the rectifier output and a series connected gallium nitride diode and output charge storage device connected between a midpoint of the series connected magnetic field energy storage device and current interrupter and a terminal of the rectifier output and wherein the converter is characterized in not needing a transient voltage suppression circuit.
摘要翻译： A转换器具有AC输入和DC输出。该转换器包括一个接收AC输入并提供整流器输出的整流器，连接在整流器输出端的磁场能量存储装置和断流器的串联电流和串联的氮化镓二极管和输出电荷存储装置串联连接的磁场蓄能装置的中点和电流断流器以及整流器输出的端子，其中转换器的特征在于不需要瞬态电压抑制电路。

3. 发明授权

US08026568B2 Second Schottky contact metal layer to improve GaN Schottky diode performance 失效
标题翻译：第二肖特基接触金属层，以提高GaN肖特基二极管的性能
公开(公告)号：US08026568B2
公开(公告)日：2011-09-27
申请号：US11589124
申请日：2006-10-27
申请人： Ting Gang Zhu , Marek Pabisz
发明人： Ting Gang Zhu , Marek Pabisz
IPC分类号： H01L31/07 , H01L21/338
CPC分类号： H01L29/7786 , H01L21/28581 , H01L29/2003 , H01L29/47 , H01L29/475 , H01L29/66143 , H01L29/7787 , H01L29/872
摘要： A Schottky contact is disposed atop a surface of a semiconductor. A first Schottky contact metal layer is disposed atop a first portion of the semiconductor surface. A second Schottky contact metal is disposed atop a second portion of the surface layer and adjoins the first Schottky contact metal layer. The first Schottky contact metal layer has a lower work function than the second Schottky contact metal layer.
摘要翻译：将肖特基接触件设置在半导体的表面上。第一肖特基接触金属层设置在半导体表面的第一部分的顶部。第二肖特基接触金属设置在表面层的第二部分的顶部并与第一肖特基接触金属层相邻。第一肖特基接触金属层的功函数低于第二肖特基接触金属层。

4. 发明授权

US07229866B2 Non-activated guard ring for semiconductor devices 失效
标题翻译：半导体器件非激活保护环
公开(公告)号：US07229866B2
公开(公告)日：2007-06-12
申请号：US10935000
申请日：2004-09-07
申请人： Ting Gang Zhu , Bryan S. Shelton , Alex D. Ceruzzi , Linlin Liu , Michael Murphy , Milan Pophristic
发明人： Ting Gang Zhu , Bryan S. Shelton , Alex D. Ceruzzi , Linlin Liu , Michael Murphy , Milan Pophristic
IPC分类号： H01L21/338
CPC分类号： H01L29/32 , H01L29/0615 , H01L29/0619 , H01L29/0634 , H01L29/2003 , H01L29/207 , H01L29/452 , H01L29/475 , H01L29/66143 , H01L29/66212 , H01L29/872
摘要： A guard ring is formed in a semiconductor region that is part of a Schottky junction or Schottky diode. The guard ring is formed by ion implantation into the semiconductor contact layer without completely annealing the semiconductor contact layer to form a high resistance region. The guard ring may be located at the edge of the layer or, alternatively, at a distance away from the edge of the layer. A Schottky metal contact is formed atop the layer, and the edges of the Schottky contact are disposed atop the guard ring.
摘要翻译：在作为肖特基结或肖特基二极管的一部分的半导体区域中形成保护环。保护环通过离子注入形成于半导体接触层中，而不会使半导体接触层完全退火以形成高电阻区域。保护环可以位于层的边缘处，或者可选地，离开层的边缘一定距离。肖特基金属接触形成在层的顶部，肖特基接触的边缘设置在保护环的顶部。

5. 发明申请

US20090321787A1 High voltage GaN-based heterojunction transistor structure and method of forming same 审中-公开
标题翻译：高电压GaN基异质结晶体结构及其形成方法
公开(公告)号：US20090321787A1
公开(公告)日：2009-12-31
申请号：US11725820
申请日：2007-03-20
申请人： Michael Murphy , Milan Pophristic
发明人： Michael Murphy , Milan Pophristic
IPC分类号： H01L29/778 , H01L21/335
CPC分类号： H01L29/7787 , H01L21/02378 , H01L21/0242 , H01L21/02458 , H01L21/0254 , H01L23/3171 , H01L29/2003 , H01L29/66462 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a substrate, a first active layer disposed over the substrate, and a second active layer disposed on the first active layer. The second active layer has a higher bandgap than the first active layer such that a two-dimensional electron gas layer arises between the first active layer and the second active layer. A flash layer is disposed on the second active layer and source, gate and drain contacts are disposed on the flash layer.
摘要翻译：半导体器件包括衬底，设置在衬底上的第一有源层和设置在第一有源层上的第二有源层。第二有源层具有比第一有源层更高的带隙，使得在第一有源层和第二有源层之间产生二维电子气层。闪光层设置在第二有源层上，源极，栅极和漏极触点设置在闪光层上。

6. 发明申请

US20080230785A1 Termination and contact structures for a high voltage GaN-based heterojunction transistor 有权
标题翻译：用于高电压GaN基异质结晶体管的端接和接触结构
公开(公告)号：US20080230785A1
公开(公告)日：2008-09-25
申请号：US11725823
申请日：2007-03-20
申请人： Michael Murphy , Milan Pophristic
发明人： Michael Murphy , Milan Pophristic
IPC分类号： H01L29/778
CPC分类号： H01L29/2003 , H01L21/02378 , H01L21/0242 , H01L21/02458 , H01L21/0254 , H01L21/31683 , H01L23/3171 , H01L29/205 , H01L29/432 , H01L29/7786 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device is provided that includes a substrate, a first active layer disposed over the substrate, and a second active layer disposed on the first active layer. The second active layer has a higher bandgap than the first active layer such that a two-dimensional electron gas layer arises between the first active layer and the second active layer. A termination layer, which is disposed on the second active layer, includes InGaN. Source, gate and drain contacts are disposed on the termination layer.
摘要翻译：提供了一种半导体器件，其包括衬底，设置在衬底上的第一有源层和设置在第一有源层上的第二有源层。第二有源层具有比第一有源层更高的带隙，使得在第一有源层和第二有源层之间产生二维电子气层。设置在第二有源层上的端接层包括InGaN。源极，栅极和漏极触点设置在端接层上。

7. 发明申请

US20070108547A1 Second Schottky contact metal layer to improve GaN Schottky diode performance 失效
标题翻译：第二肖特基接触金属层，以提高GaN肖特基二极管的性能
公开(公告)号：US20070108547A1
公开(公告)日：2007-05-17
申请号：US11589124
申请日：2006-10-27
申请人： Ting Zhu , Marek Pabisz
发明人： Ting Zhu , Marek Pabisz
IPC分类号： H01L31/07 , H01L21/338
CPC分类号： H01L29/7786 , H01L21/28581 , H01L29/2003 , H01L29/47 , H01L29/475 , H01L29/66143 , H01L29/7787 , H01L29/872
摘要： A Schottky contact is disposed atop a surface of a semiconductor. A first Schottky contact metal layer is disposed atop a first portion of the semiconductor surface. A second Schottky contact metal is disposed atop a second portion of the surface layer and adjoins the first Schottky contact metal layer. The first Schottky contact metal layer has a lower work function than the second Schottky contact metal layer.
摘要翻译：将肖特基接触件设置在半导体的表面上。第一肖特基接触金属层设置在半导体表面的第一部分的顶部。第二肖特基接触金属设置在表面层的第二部分的顶部并与第一肖特基接触金属层相邻。第一肖特基接触金属层具有比第二肖特基接触金属层更低的功函数。

8. 发明申请

US20110316045A1 LAYOUT DESIGN FOR A HIGH POWER, GaN-BASED FET 有权
标题翻译：用于高功率GaN基FET的布局设计
公开(公告)号：US20110316045A1
公开(公告)日：2011-12-29
申请号：US12821492
申请日：2010-06-23
申请人： Linlin LIU , Milan POPHRISTIC , Boris Peres
发明人： Linlin LIU , Milan POPHRISTIC , Boris Peres
IPC分类号： H01L29/772
CPC分类号： H01L29/7786 , H01L29/0657 , H01L29/2003 , H01L29/41758 , H01L29/42316
摘要： A FET includes a substrate, a buffer layer disposed on the substrate, a channel layer disposed over the buffer layer and a barrier layer disposed over the channel layer. Source, gate and drain electrodes are located over the barrier layer and extend in a longitudinal direction thereon. A portion of the channel and barrier layers define a mesa extending in the longitudinal direction and the source and drain electrodes extend beyond an edge of the mesa. The gate electrodes extend along an edge sidewall of the mesa. A conductive source interconnect is disposed over the buffer layer and have a first end electrically connected to the source electrode. A first dielectric layer is disposed over the buffer layer and over the source interconnect. A gate via is formed in the first dielectric layer. A conductive gate node extends along the buffer layer and electrically connects the portion of the gate electrode extending along the sidewall of the mesa. A gate pad is disposed on the first dielectric layer adjacent the mesa. A conductive gate connect strip is located over the gate node and is in contact therewith. The gate strip is in electrical contact with the gate pad. A source via is formed in the first dielectric layer and a source pad is formed in the source via. The conductive source interconnect has a second end in electrical contact with the source pad.
摘要翻译： FET包括衬底，设置在衬底上的缓冲层，设置在缓冲层上的沟道层和设置在沟道层上的阻挡层。源极，栅极和漏极电极位于阻挡层的上方并沿其纵向方向延伸。通道和阻挡层的一部分限定沿纵向方向延伸的台面，并且源电极和漏电极延伸超过台面的边缘。栅电极沿台面的边缘侧壁延伸。导电源互连设置在缓冲层之上并且具有电连接到源电极的第一端。第一介电层设置在缓冲层之上并且在源互连上。在第一电介质层中形成栅极通孔。导电栅极节点沿着缓冲层延伸并且电连接沿着台面的侧壁延伸的栅电极的部分。栅极焊盘设置在与台面相邻的第一电介质层上。导电栅极连接条位于栅极节点上方并与其接触。栅极条与栅极焊盘电接触。源极通孔形成在第一电介质层中，并且在源极通孔中形成源极焊盘。导电源互连具有与源极焊盘电接触的第二端。

9. 发明申请

US20110309372A1 ENHANCEMENT-MODE HFET CIRCUIT ARRANGEMENT HAVING HIGH POWER AND A HIGH THRESHOLD VOLTAGE 有权
标题翻译：具有高功率和高阈值电压的增强型HFET电路布置
公开(公告)号：US20110309372A1
公开(公告)日：2011-12-22
申请号：US12819446
申请日：2010-06-21
申请人： Xiaobin XIN , Milan POPHRISTIC , Michael SHUR
发明人： Xiaobin XIN , Milan POPHRISTIC , Michael SHUR
IPC分类号： H01L29/737 , H01L29/20 , H01L21/335
CPC分类号： H01L27/0629 , H01L27/0605 , H01L27/0617 , H01L29/2003 , H01L29/402 , H01L29/41725 , H01L29/41758 , H01L29/42316 , H01L29/4236 , H01L29/7787 , H03K2017/6875
摘要： A circuit includes input drain, source and gate nodes. The circuit also includes a group III nitride enhancement-mode HFET having a source, drain and gate and a voltage shifter having a first terminal connected to the gate of the enhancement mode HFET at a common junction. The circuit also includes a load resistive element connected to the common junction. The drain of the enhancement-mode HFET serves as the input drain node, the source of the enhancement-mode HFET serves as the input source node and a second terminal of the voltage shifter serves as the input gate node.
摘要翻译：电路包括输入漏极，源极和栅极节点。该电路还包括具有源极，漏极和栅极的III族氮化物增强型HFET和电压移位器，其具有在公共结处连接到增强型HFET的栅极的第一端子。电路还包括连接到公共接点的负载电阻元件。增强型HFET的漏极用作输入漏极节点，增强型HFET的源极用作输入源节点，并且电压移位器的第二端子用作输入栅极节点。

10. 发明授权

US07501670B2 Cascode circuit employing a depletion-mode, GaN-based FET 有权
标题翻译：采用耗尽型GaN基FET的串联电路
公开(公告)号：US07501670B2
公开(公告)日：2009-03-10
申请号：US11725760
申请日：2007-03-20
申请人： Michael Murphy
发明人： Michael Murphy
IPC分类号： H01L31/0328
CPC分类号： H03K19/0952 , H01L27/0605 , H01L27/0883 , H01L29/2003 , H01L29/66462 , H01L29/7786 , H03F1/226 , H03K17/567 , H03K19/09482
摘要： A circuit includes an input drain, source and gate nodes. The circuit also includes a group III nitride depletion mode FET having a source, drain and gate, wherein the gate of the depletion mode FET is coupled to a potential that maintains the depletion mode FET in its on-state. In addition, the circuit further includes an enhancement mode FET having a source, drain and gate. The source of the depletion mode FET is serially coupled to the drain of the enhancement mode FET. The drain of the depletion mode FET serves as the input drain node, the source of the enhancement mode FET serves as the input source node and the gate of the enhancement mode FET serves as the input gate node.
摘要翻译：电路包括输入漏极，源极和栅极节点。电路还包括具有源极，漏极和栅极的III族氮化物耗尽型FET，其中耗尽型FET的栅极耦合到将耗尽型FET维持在其导通状态的电位。此外，电路还包括具有源极，漏极和栅极的增强型FET。耗尽型FET的源极串联耦合到增强型FET的漏极。耗尽型FET的漏极用作输入漏极节点，增强型FET的源极用作输入源极节点，而增强型FET的栅极用作输入栅极节点。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式