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1. 发明授权

US07356786B2 Method and user interface for debugging an electronic system 有权
标题翻译：用于调试电子系统的方法和用户界面
公开(公告)号：US07356786B2
公开(公告)日：2008-04-08
申请号：US10915516
申请日：2004-08-09
申请人： Nils Endric Schubert , John Mark Beardslee , Gernot Heinrich Koch , Olaf Poeppe
发明人： Nils Endric Schubert , John Mark Beardslee , Gernot Heinrich Koch , Olaf Poeppe
IPC分类号： G06F17/50
CPC分类号： G01R31/31705 , G01R31/318357 , G06F17/5022
摘要： Techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level are described. Although the hardware designs (which were designed in HDL) have been fabricated in integrated circuit products with limited input/output pins, the techniques and systems enable the hardware designs within the integrated circuit products to be comprehensively analyzed, diagnosed, and debugged at the HDL level at speed. The ability to debug hardware designs at the HDL level facilitates correction or adjustment of the HDL description of the hardware designs.
摘要翻译：描述了硬件描述语言（HDL）级别的分析，诊断和调试制造硬件设计的技术和系统。虽然硬件设计（HDL设计）已经在具有有限输入/输出引脚的集成电路产品中制造，但是这些技术和系统使集成电路产品中的硬件设计能够在HDL中进行全面分析，诊断和调试水平速度。以HDL级别调试硬件设计的能力有助于校正或调整硬件设计的HDL描述。

2. 发明授权

US07251800B2 Method and apparatus for automated circuit design 有权
标题翻译：自动化电路设计的方法和装置
公开(公告)号：US07251800B2
公开(公告)日：2007-07-31
申请号：US10856280
申请日：2004-05-27
申请人： Kenneth S. McElvain , Andrew Crews , Champaka Ramachandran
发明人： Kenneth S. McElvain , Andrew Crews , Champaka Ramachandran
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5031 , G06F17/505 , G06F17/5072
摘要： Methods and apparatuses to automatically modify a circuit design according to the possible deviation in the subsequent implementation of the circuit. In one aspect, a method to design a circuit includes: determining whether a design constraint is likely to be violated during a subsequent routing implementation of a design of the circuit; and, modifying the design of the circuit to reduce likelihood of the design constraint being violated during a subsequent implementation. For example, a route for a net with a number of fanout larger than two and on a timing critical or near-critical path may be considered sensitive to route topology such that an alternative routing path may lead to a violation in timing constraint; to reduce the possibility of a timing problem in a subsequent routing solution, a transformation can be selectively applied to the circuit design to an extent not worsening a cost function.
摘要翻译：方法和装置根据电路的后续实现中的可能偏差自动修改电路设计。一方面，一种设计电路的方法包括：确定在电路设计的后续路由实现期间是否可能违反设计约束; 以及修改电路的设计以减少在随后的实施期间违反设计约束的可能性。例如，对于具有大于2的扇区数目的网络以及在时间关键或接近关键路径上的网络的路由可以被认为对路由拓扑敏感，使得替代的路由路径可能导致定时约束的违规; 为了减少后续路由解决方案中的定时问题的可能性，可以在不会降低成本函数的程度上选择性地将电路设计应用于转换。

3. 发明授权

US07213216B2 Method and system for debugging using replicated logic and trigger logic 有权
公开(公告)号：US07213216B2
公开(公告)日：2007-05-01
申请号：US11112092
申请日：2005-04-22
申请人： Chun Kit Ng , Mario Larouche
发明人： Chun Kit Ng , Mario Larouche
IPC分类号： G06F17/50
CPC分类号： G01R31/3016 , G01R31/31705 , G01R31/318364 , G06F11/3648 , G06F17/5022
摘要： A method and system for debugging using replicated logic and trigger logic is described. A representation of a circuit is compiled. One or more signals are selected for triggering and trigger logic is inserted into the circuit. A portion of the circuit is selected for replication. The selected portion of the circuit is replicated and delay logic is inserted to delay the inputs into the replicated portion of the circuit. The representation of the circuit is recompiled and programmed into a hardware device. A debugger may then be invoked. One or more of the triggering signals are selected. For each selected triggering signal, one or more states are selected to setup a trigger condition. The hardware device may then be run. The replicated portion of the circuit will be paused when the trigger condition occurs. The states of registers in the replicated portion of the circuit and the sequence of steps that led to the trigger condition may then be recorded.

4. 发明授权

US07051296B1 Method and apparatus for parallel carry chains 有权
标题翻译：并行携带链的方法和装置
公开(公告)号：US07051296B1
公开(公告)日：2006-05-23
申请号：US10817586
申请日：2004-04-02
申请人： Ken S. McElvain
发明人： Ken S. McElvain
IPC分类号： G06F17/50
CPC分类号： G06F7/506 , G06F17/505 , G06F2217/84
摘要： An apparatus having two or more parallel carry chain structures, each of the carry chain structures comprising a series of logical structures, where at least one of the logical structures within each of the carry chain structures has an associated input node, output node and carry node. The input node corresponds to a function input term, the output node corresponds to an output term of the function and the carry node corresponds to a carry value to a following logical structure in the series of logical structures.
摘要翻译：具有两个或更多个并行进位链结构的装置，每个进位链结构包括一系列逻辑结构，其中每个进位链结构内的至少一个逻辑结构具有相关联的输入节点，输出节点和进位节点。输入节点对应于功能输入项，输出节点对应于功能的输出项，进位节点对应于一系列逻辑结构中的后续逻辑结构的进位值。

5. 发明授权

US07350173B1 Method and apparatus for placement and routing cells on integrated circuit chips 有权
公开(公告)号：US07350173B1
公开(公告)日：2008-03-25
申请号：US10351094
申请日：2003-01-23
申请人： Roger P. Ang , Ken R. McElvain , Kenneth S. McElvain
发明人： Roger P. Ang , Ken R. McElvain , Kenneth S. McElvain
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5031 , G06F17/5077 , G06F17/5081
摘要： Methods and apparatuses to place and route cells on integrated circuit chips along paths. In one aspect of the invention, methods to layout an integrated circuit are based on placing and routing cells along paths. In one embodiment, a method to layout an integrated circuit including: routing a wire to connect a first cell of the integrated circuit and a second cell of the integrated circuit; and placing a third cell of the integrated circuit after the wire is routed to connect the first cell and the second cell. In one example, the first, second and third cells are on a first path; and, the third cell is connected to one of the first and second cells on the first path by only one net. The first path is selected from a set of paths; and the first and second cells are placed before the wire is routed to connect the first cell and the second cell. Timing is analyzed using a route of the wire connecting the first cell and the second cell to select a second path from the set of paths before a cell is placed on the second path.

6. 发明授权

US07278120B2 Methods and apparatuses for transient analyses of circuits 有权
标题翻译：电路瞬态分析的方法和装置
公开(公告)号：US07278120B2
公开(公告)日：2007-10-02
申请号：US10897459
申请日：2004-07-23
申请人： Khalid Rahmat , Kenneth S. McElvain
发明人： Khalid Rahmat , Kenneth S. McElvain
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/78
摘要： Methods and apparatuses for transient analyses of a circuit using a hierarchical approach. In one embodiment, the cells are grouped locally on the power supply network according to average power dissipation. A time varying current of each cell group is estimated using a probabilistic approach to represent the cell group so that the probability of a more severe waveform for the current of the cell group is under a certain level. For example, the cells in a group are partitioned as switching cells and non-switching cells using cell toggle rates for the determination of the time varying current. The circuit model of the power supply network includes the current sources according to the estimated time varying currents for the cell groups, the power supply wire resistance, the power supply to ground wire capacitance, well capacitance and the de-coupling capacitance from non-switching cells.
摘要翻译：使用分层方法对电路进行瞬态分析的方法和装置。在一个实施例中，根据平均功耗，电池在电源网络上局部分组。使用概率方法估计每个小区组的时变电流，以表示小区组，使得小区组的当前电流的更严重波形的概率在一定水平以下。例如，使用单元切换速率将组中的单元划分为切换单元和非切换单元，以确定时变电流。电源网络的电路模型包括根据电池组的估计时变电流的电流源，电源线电阻，接地线电容的电源，阱电容和非开关的去耦电容细胞。

7. 发明授权

US07162704B2 Method and apparatus for circuit design and retiming 有权
标题翻译：电路设计和重新定时的方法和装置
公开(公告)号：US07162704B2
公开(公告)日：2007-01-09
申请号：US10435061
申请日：2003-05-09
申请人： Levent Oktem
发明人： Levent Oktem
IPC分类号： G06F17/50
CPC分类号： G06F17/5059 , G06F17/505
摘要： Methods and apparatuses to hierarchically retime a circuit. In at least one embodiment of the present invention, a module of a circuit is designed with a plurality of different latencies to have a plurality of different minimum clock periods (e.g., through retiming at the module level). In one example, the minimum clock periods are determined from detailed timing analyses after the placement and routing for the module; and, in retiming the circuit that contains the module, a data flow graph representation of the module is constructed based on the target clock period of the circuit and the correlation between the latencies and the minimum clock periods. In at least one embodiment of the present invention, hierarchical retiming is performed in which portions of the circuit is retimed to generate results (e.g., for different latencies), which are selectively used for the retiming of the entire circuit based on the target clock period.
摘要翻译：电路分层复位的方法和装置。在本发明的至少一个实施例中，电路的模块被设计成具有多个不同的延迟以具有多个不同的最小时钟周期（例如，通过在模块级重新定时）。在一个示例中，在模块的放置和布线之后，从详细的时序分析确定最小时钟周期; 并且在重新定时包含模块的电路中，基于电路的目标时钟周期和延迟与最小时钟周期之间的相关性，构建模块的数据流图表示。在本发明的至少一个实施例中，执行分层重新定时，其中电路的部分被重新定时以产生结果（例如，对于不同的延迟），其被选择性地用于基于目标时钟周期重新定时整个电路。

8. 发明授权

US07072818B1 Method and system for debugging an electronic system 有权
公开(公告)号：US07072818B1
公开(公告)日：2006-07-04
申请号：US09724585
申请日：2000-11-28
申请人： John Mark Beardslee , Nils Endric Schubert , Douglas L. Perry
发明人： John Mark Beardslee , Nils Endric Schubert , Douglas L. Perry
IPC分类号： G06F17/50
CPC分类号： G01R31/31705 , G01R31/318357 , G01R31/318364 , G06F17/5022
摘要： Techniques and systems for debugging an electronic system having instrumentation circuitry included therein are disclosed. The techniques and systems facilitate analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level. Although the hardware designs (which were designed in HDL) have been fabricated in integrated circuit products with limited input/output pins, the invention enables the hardware designs within the integrated circuit products to be comprehensively analyzed, diagnosed, and debugged at the HDL level at speed. The ability to debug hardware designs at the HDL level facilitates correction or adjustment of the HDL description of the hardware designs.

9. 发明授权

US07065481B2 Method and system for debugging an electronic system using instrumentation circuitry and a logic analyzer 有权
公开(公告)号：US07065481B2
公开(公告)日：2006-06-20
申请号：US10212128
申请日：2002-07-31
申请人： Nils Endric Schubert , John Mark Beardslee , Gernot Heinrich Koch , Olaf Poeppe
发明人： Nils Endric Schubert , John Mark Beardslee , Gernot Heinrich Koch , Olaf Poeppe
IPC分类号： G06F17/50
CPC分类号： G01R31/318357 , G01R31/318364 , G06F17/5022
摘要： Techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level are described. Although the hardware designs (which were designed in HDL) have been fabricated in integrated circuit products with limited input/output pins, the techniques and systems enable the hardware designs within the integrated circuit products to be comprehensively analyzed, diagnosed, and debugged at the HDL level at speed. The ability to debug hardware designs at the HDL level facilitates correction or adjustment of the HDL description of the hardware designs.

10. 发明授权

US07376919B1 Methods and apparatuses for automated circuit optimization and verification 有权
标题翻译：用于自动化电路优化和验证的方法和设备
公开(公告)号：US07376919B1
公开(公告)日：2008-05-20
申请号：US11124496
申请日：2005-05-04
申请人： Kenneth S. McElvain , Vijay Seshadri
发明人： Kenneth S. McElvain , Vijay Seshadri
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： Methods and apparatuses to automatically determine conditions at hierarchical boundaries of a hierarchical circuit design and to use the determined conditions in hierarchical optimization and verification. In one embodiment, a hierarchical block is optimized and transformed during design synthesis using one or more lemmas at the boundary of the hierarchical block. For example, the lemmas are automatically generated to specify range information for input boundary nodes. The lemmas are also used for the equivalence checker to perform hierarchical equivalence checking. Equivalence of hierarchical blocks is individually checked, in view of the lemmas. Thus, based on the lemmas, optimizations across hierarchical boundaries can be performed, while the hierarchical structure of the design is preserved so that equivalence checking of hierarchical circuit designs can still be based on the equivalence of individual hierarchical blocks.
摘要翻译：自动确定分层电路设计层级边界条件的方法和装置，并在分层优化和验证中使用确定的条件。在一个实施例中，在设计合成期间使用分层块的边界处的一个或多个引理优化和变换分层块。例如，自动生成引文以指定输入边界节点的范围信息。引文也用于等价检查器以执行层次等价检查。鉴于引理，分层检查的等同性被单独检查。因此，基于引理，可以执行跨层次边界的优化，同时保留设计的层次结构，使得分层电路设计的等价性检查仍然可以基于各个层级块的等价性。

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