专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07665046B2 Method and system for debugging using replicated logic and trigger logic 有权
标题翻译：使用复制逻辑和触发逻辑进行调试的方法和系统
公开(公告)号：US07665046B2
公开(公告)日：2010-02-16
申请号：US11732784
申请日：2007-04-03
申请人： Chun Kit Ng , Kenneth S. McElvain
发明人： Chun Kit Ng , Kenneth S. McElvain
IPC分类号： G06F17/50
CPC分类号： G01R31/3016 , G01R31/31705 , G01R31/318364 , G06F11/3648 , G06F17/5022
摘要： A method and system for debugging using replicated logic and trigger logic is described. A representation of a circuit is compiled. One or more signals are selected for triggering and trigger logic is inserted into the circuit. A portion of the circuit is selected for replication. The selected portion of the circuit is replicated and delay logic is inserted to delay the inputs into the replicated portion of the circuit. The representation of the circuit is recompiled and programmed into a hardware device. A debugger may then be invoked. One or more of the triggering signals are selected. For each selected triggering signal, one or more states are selected to setup a trigger condition. The hardware device may then be run. The replicated portion of the circuit will be paused when the trigger condition occurs. The states of registers in the replicated portion of the circuit and the sequence of steps that led to the trigger condition may then be recorded.
摘要翻译：描述了使用复制逻辑和触发逻辑进行调试的方法和系统。编译电路的表示。选择一个或多个信号进行触发，并将触发逻辑插入电路。电路的一部分被选择用于复制。电路的所选部分被复制，并且插入延迟逻辑以将输入延迟到电路的复制部分。电路的表示被重新编译并编程到硬件设备中。然后可以调用调试器。选择一个或多个触发信号。对于每个选定的触发信号，选择一个或多个状态来设置触发条件。然后可以运行硬件设备。当触发条件发生时，电路的复制部分将被暂停。然后可以记录电路的复制部分中的寄存器的状态和导致触发条件的步骤序列。

2. 发明申请

US20080313589A1 Techniques For Use With Automated Circuit Design and Simulations 有权
标题翻译：使用自动电路设计和仿真技术
公开(公告)号：US20080313589A1
公开(公告)日：2008-12-18
申请号：US12117714
申请日：2008-05-08
申请人： Richard C. Maixner , Mario Larouche , Chun Kit Ng , Kenneth S. McElvain
发明人： Richard C. Maixner , Mario Larouche , Chun Kit Ng , Kenneth S. McElvain
IPC分类号： G06F17/50
CPC分类号： G06F17/5027 , G06F2217/62
摘要： Various techniques related to clocking signals used for automated circuit design and simulations are disclosed. In some embodiments, a method includes receiving first and second asynchronous clock signals having a first phase relationship at a first time and sampling the second clock signal at transitions of the first clock. The method further includes storing the samples; and analyzing the samples to ascertain the first phase relationship of the second clock signal with respect to the first clock signal and provide a representation of the first phase relationship. Other embodiments are described.
摘要翻译：公开了与用于自动化电路设计和模拟的时钟信号有关的各种技术。在一些实施例中，一种方法包括在第一时间接收具有第一相位关系的第一和第二异步时钟信号，并且在第一时钟的转变处对第二时钟信号进行采样。该方法还包括存储样品; 以及分析样本以确定第二时钟信号相对于第一时钟信号的第一相位关系，并提供第一相位关系的表示。描述其他实施例。

3. 发明授权

US06904576B2 Method and system for debugging using replicated logic 有权
标题翻译：使用复制逻辑进行调试的方法和系统
公开(公告)号：US06904576B2
公开(公告)日：2005-06-07
申请号：US10215869
申请日：2002-08-09
申请人： Chun Kit Ng , Kenneth S. McElvain
发明人： Chun Kit Ng , Kenneth S. McElvain
IPC分类号： G01R31/30 , G01R31/317 , G06F17/50 , H01L21/82 , H03K19/173
CPC分类号： G01R31/3016 , G01R31/31705 , G06F17/5022
摘要： A method and apparatus is provided to debug using replicated logic. A text representation of a circuit is compiled to generate a first register transfer level (RTL) netlist. The netlist may be mapped to a target architecture, such as a field programmable gate array (FPGA). The netlist may be used to program an FPGA to create a prototype board for debugging. After debug, a portion of the circuit that a designer would like to analyze is selected. The selected portion of the circuit is replicated. Delay logic is inserted to delay the inputs into the replicated portion of the circuit. The text representation of the circuit is recompiled to generate a second RTL netlist. The second RTL netlist may be mapped to a target architecture, such as a FPGA or application specific integrated circuit (ASIC).
摘要翻译：提供了一种使用复制逻辑进行调试的方法和装置。编译电路的文本表示以产生第一寄存器传送级（RTL）网表。网表可以映射到目标架构，例如现场可编程门阵列（FPGA）。网表可用于编程FPGA以创建用于调试的原型板。在调试之后，选择设计者想要分析的电路的一部分。电路的选定部分被复制。插入延迟逻辑以将输入延迟到电路的复制部分。重新编译电路的文本表示以生成第二个RTL网表。第二RTL网表可以映射到目标架构，例如FPGA或专用集成电路（ASIC）。

4. 发明授权

US08392859B2 Method and system for debugging using replicated logic and trigger logic 有权
标题翻译：使用复制逻辑和触发逻辑进行调试的方法和系统
公开(公告)号：US08392859B2
公开(公告)日：2013-03-05
申请号：US12687809
申请日：2010-01-14
申请人： Chun Kit Ng , Kenneth S. McElvain
发明人： Chun Kit Ng , Kenneth S. McElvain
IPC分类号： G06F17/50
CPC分类号： G01R31/3016 , G01R31/31705 , G01R31/318364 , G06F11/3648 , G06F17/5022
摘要： A method and system for debugging using replicated logic and trigger logic is described. A representation of a circuit is compiled. One or more signals are selected for triggering and trigger logic is inserted into the circuit. A portion of the circuit is selected for replication. The selected portion of the circuit is replicated and delay logic is inserted to delay the inputs into the replicated portion of the circuit. The representation of the circuit is recompiled and programmed into a hardware device. A debugger may then be invoked. One or more of the triggering signals are selected. For each selected triggering signal, one or more states are selected to setup a trigger condition. The hardware device may then be run. The replicated portion of the circuit will be paused when the trigger condition occurs. The states of registers in the replicated portion of the circuit and the sequence of steps that led to the trigger condition may then be recorded.
摘要翻译：描述了使用复制逻辑和触发逻辑进行调试的方法和系统。编译电路的表示。选择一个或多个信号进行触发，并将触发逻辑插入电路。电路的一部分被选择用于复制。电路的所选部分被复制，并且插入延迟逻辑以将输入延迟到电路的复制部分。电路的表示被重新编译并编程到硬件设备中。然后可以调用调试器。选择一个或多个触发信号。对于每个选定的触发信号，选择一个或多个状态来设置触发条件。然后可以运行硬件设备。当触发条件发生时，电路的复制部分将被暂停。然后可以记录电路的复制部分中的寄存器的状态和导致触发条件的步骤序列。

5. 发明申请

US20100122132A1 METHOD AND SYSTEM FOR DEBUGGING USING REPLICATED LOGIC AND TRIGGER LOGIC 有权
标题翻译：使用复制逻辑和触发逻辑进行调试的方法和系统
公开(公告)号：US20100122132A1
公开(公告)日：2010-05-13
申请号：US12687809
申请日：2010-01-14
申请人： Chun Kit Ng , Kenneth S. McElvain
发明人： Chun Kit Ng , Kenneth S. McElvain
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/3016 , G01R31/31705 , G01R31/318364 , G06F11/3648 , G06F17/5022
摘要： A method and system for debugging using replicated logic and trigger logic is described. A representation of a circuit is compiled. One or more signals are selected for triggering and trigger logic is inserted into the circuit. A portion of the circuit is selected for replication. The selected portion of the circuit is replicated and delay logic is inserted to delay the inputs into the replicated portion of the circuit. The representation of the circuit is recompiled and programmed into a hardware device. A debugger may then be invoked. One or more of the triggering signals are selected. For each selected triggering signal, one or more states are selected to setup a trigger condition. The hardware device may then be run. The replicated portion of the circuit will be paused when the trigger condition occurs. The states of registers in the replicated portion of the circuit and the sequence of steps that led to the trigger condition may then be recorded.
摘要翻译：描述了使用复制逻辑和触发逻辑进行调试的方法和系统。编译电路的表示。选择一个或多个信号进行触发，并将触发逻辑插入电路。电路的一部分被选择用于复制。电路的所选部分被复制，并且插入延迟逻辑以将输入延迟到电路的复制部分。电路的表示被重新编译并编程到硬件设备中。然后可以调用调试器。选择一个或多个触发信号。对于每个选定的触发信号，选择一个或多个状态来设置触发条件。然后可以运行硬件设备。当触发条件发生时，电路的复制部分将被暂停。然后可以记录电路的复制部分中的寄存器的状态和导致触发条件的步骤序列。

6. 发明申请

US20080313579A1 Techniques For Use With Automated Circuit Design and Simulations 有权
标题翻译：使用自动电路设计和仿真技术
公开(公告)号：US20080313579A1
公开(公告)日：2008-12-18
申请号：US12117711
申请日：2008-05-08
申请人： Mario Larouche , Richard C. Maixner , Chun Kit Ng , Kenneth S. McElvain
发明人： Mario Larouche , Richard C. Maixner , Chun Kit Ng , Kenneth S. McElvain
IPC分类号： G06F17/50
CPC分类号： G06F17/5027
摘要： Various techniques related to clocking for use with automated circuit design and simulations are disclosed. In some embodiments, a method includes receiving descriptions of design circuitry including logic to receive input signals. The method further includes generating additional descriptions through at least one computer program including descriptions of a multiplexer to multiplex the input signals and delayed input signals, and provide them to the logic, and a demultiplexer to demultiplex output signals and delayed output signals from the logic. Other embodiments are described.
摘要翻译：公开了与用于自动化电路设计和仿真的时钟有关的各种技术。在一些实施例中，一种方法包括接收包括用于接收输入信号的逻辑的设计电路的描述。该方法还包括通过至少一个计算机程序产生附加的描述，所述计算机程序包括多路复用器的描述，以复用输入信号和延迟的输入信号，并将其提供给逻辑，以及解复用器，用于从逻辑解复用输出信号和延迟的输出信号。描述其他实施例。

7. 发明授权

US07398445B2 Method and system for debug and test using replicated logic 有权
标题翻译：使用复制逻辑进行调试和测试的方法和系统
公开(公告)号：US07398445B2
公开(公告)日：2008-07-08
申请号：US11195180
申请日：2005-08-02
申请人： Chun Kit Ng , Mario Larouche
发明人： Chun Kit Ng , Mario Larouche
IPC分类号： G06F11/00
CPC分类号： G01R31/3016 , G01R31/31705 , G01R31/318342 , G01R31/318364 , G06F17/5022
摘要： A method and system for debug and test using replicated logic is described. A representation of a circuit is compiled. The circuit includes a replicated portion and delay logic to delay inputs into the replicated portion. The circuit may also include trigger logic and clock control logic to enable execution of the replicated portion of the circuit to be paused when a trigger condition occurs. The compiled representation of the circuit may be programmed into a hardware device. A debugger may then be invoked. One or more triggering signals are selected. For each selected triggering signal, one or more states are selected to setup a trigger condition. The hardware device may then be run. The replicated portion of the circuit will be paused when the trigger condition occurs. The states of registers in the replicated portion of the circuit and the sequence of inputs that led to the trigger condition are recorded. This recorded data may then used to generate a test to be run on a software simulator when the circuit is modified.
摘要翻译：描述了使用复制逻辑进行调试和测试的方法和系统。编译电路的表示。电路包括复制部分和延迟逻辑以将输入延迟到复制部分。该电路还可以包括触发逻辑和时钟控制逻辑，以便当发生触发条件时能够执行待暂停的电路的复制部分。电路的编译表示可以被编程到硬件设备中。然后可以调用调试器。选择一个或多个触发信号。对于每个选定的触发信号，选择一个或多个状态来设置触发条件。然后可以运行硬件设备。当触发条件发生时，电路的复制部分将被暂停。记录电路复制部分的寄存器状态以及导致触发条件的输入序列。然后，该记录的数据可用于产生在电路被修改时在软件模拟器上运行的测试。

8. 发明授权

US07107570B1 Method and system for user-defined triggering logic in a hardware description language 有权
标题翻译：硬件描述语言中用户定义触发逻辑的方法和系统
公开(公告)号：US07107570B1
公开(公告)日：2006-09-12
申请号：US10822192
申请日：2004-04-08
申请人： Mario Larouche , Chun Kit Ng
发明人： Mario Larouche , Chun Kit Ng
IPC分类号： G06F17/50 , G06F11/00
CPC分类号： G06F17/505 , G06F17/5022 , G06F17/504
摘要： A method and system for user-defined triggering logic in a hardware description language is described. The method includes reading a file containing user-defined triggering logic described in a hardware description language (HDL), inserting and connecting the triggering logic to a circuit described in HDL, and compiling the HDL description of the circuit to generate a register transfer level (RTL) netlist.
摘要翻译：描述了硬件描述语言中用户定义的触发逻辑的方法和系统。该方法包括读取包含以硬件描述语言（HDL）描述的用户定义的触发逻辑的文件，将触发逻辑插入并连接到HDL中描述的电路，以及编译电路的HDL描述以产生寄存器传送电平 RTL）网表。

9. 发明授权

US07984400B2 Techniques for use with automated circuit design and simulations 有权
标题翻译：用于自动化电路设计和仿真的技术
公开(公告)号：US07984400B2
公开(公告)日：2011-07-19
申请号：US12117705
申请日：2008-05-08
申请人： Richard C. Maixner , Mario Larouche , Chun Kit Ng , Kenneth S. McElvain
发明人： Richard C. Maixner , Mario Larouche , Chun Kit Ng , Kenneth S. McElvain
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5027
摘要： Various techniques involving snapshots of the contents of registers are described and claimed. In some embodiments, a method includes receiving descriptions of design circuitry including design registers to receive register input signals. The method also includes generating additional descriptions through at least one computer program including descriptions of additional registers (snapshot registers) to receive snapshots of the register input signals, wherein the additional registers provide register initial condition signals for use in a simulation of at least a portion of the design circuitry. Other embodiments are described.
摘要翻译：描述和要求保护涉及寄存器内容的快照的各种技术。在一些实施例中，一种方法包括接收包括设计寄存器的设计电路的描述以接收寄存器输入信号。该方法还包括通过包括用于接收寄存器输入信号的快照的附加寄存器（快照寄存器）的描述的至少一个计算机程序产生附加描述，其中附加寄存器提供用于模拟至少一部分的寄存器初始条件信号的设计电路。描述其他实施例。

10. 发明授权

US07213216B2 Method and system for debugging using replicated logic and trigger logic 有权
公开(公告)号：US07213216B2
公开(公告)日：2007-05-01
申请号：US11112092
申请日：2005-04-22
申请人： Chun Kit Ng , Mario Larouche
发明人： Chun Kit Ng , Mario Larouche
IPC分类号： G06F17/50
CPC分类号： G01R31/3016 , G01R31/31705 , G01R31/318364 , G06F11/3648 , G06F17/5022
摘要： A method and system for debugging using replicated logic and trigger logic is described. A representation of a circuit is compiled. One or more signals are selected for triggering and trigger logic is inserted into the circuit. A portion of the circuit is selected for replication. The selected portion of the circuit is replicated and delay logic is inserted to delay the inputs into the replicated portion of the circuit. The representation of the circuit is recompiled and programmed into a hardware device. A debugger may then be invoked. One or more of the triggering signals are selected. For each selected triggering signal, one or more states are selected to setup a trigger condition. The hardware device may then be run. The replicated portion of the circuit will be paused when the trigger condition occurs. The states of registers in the replicated portion of the circuit and the sequence of steps that led to the trigger condition may then be recorded.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式