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1. 发明申请

US20140097530A1 INTEGRATED CIRCUIT PACKAGE 审中-公开
标题翻译：集成电路封装
公开(公告)号：US20140097530A1
公开(公告)日：2014-04-10
申请号：US13779840
申请日：2013-02-28
申请人： STS SEMICONDUCTOR & TELECOMMUNICATIONS CO., LTD.
发明人： Kyung Teck BOO
IPC分类号： H01L25/07
CPC分类号： H01L25/074 , H01L23/3107 , H01L23/3128 , H01L23/49531 , H01L23/49575 , H01L24/06 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0657 , H01L2224/04042 , H01L2224/05553 , H01L2224/06155 , H01L2224/32145 , H01L2224/32225 , H01L2224/451 , H01L2224/48145 , H01L2224/48147 , H01L2224/48227 , H01L2224/49175 , H01L2224/73265 , H01L2225/06506 , H01L2225/0651 , H01L2225/06562 , H01L2924/00014 , H01L2924/10161 , H01L2924/10253 , H01L2924/1431 , H01L2924/1434 , H01L2924/15311 , H01L2924/181 , H01L2924/19107 , H01L2924/00012 , H01L2924/00 , H01L2224/05599 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An integrated circuit package and a manufacturing method thereof are provided. The integrated circuit package can include a substrate provided with a circuit pattern, a first set of bonding fingers and a second set of bonding fingers, a first chip stack mounted on the substrate and having a plurality of first semiconductor chips stacked in a first direction in a stepped manner, each of the first semiconductor chips being provided with a first bonding pad at an end thereof on one side, a second chip stack mounted on the first chip stack and having a plurality of second semiconductor chips stacked in a second direction opposite to the first direction in a stepped manner.
摘要翻译：提供一种集成电路封装及其制造方法。集成电路封装可以包括设置有电路图案的基板，第一组接合指状物和第二组接合指状物，安装在基板上的第一芯片堆叠，并且具有沿第一方向堆叠的多个第一半导体芯片每个第一半导体芯片在其一端的端部设置有第一焊盘，安装在第一芯片堆叠上的第二芯片堆叠，并且具有多个第二半导体芯片，该第二半导体芯片沿与第二焊盘相反的第二方向堆叠第一个方向是分阶段的。

2. 发明授权

US09905551B2 Method of manufacturing wafer level packaging including through encapsulation vias 有权
公开(公告)号：US09905551B2
公开(公告)日：2018-02-27
申请号：US14799875
申请日：2015-07-15
申请人： STS Semiconductor & Telecommunications Co., Ltd.
发明人： Eun Dong Kim , Jong Won Lee , Jai Kyoung Choi
IPC分类号： H01L25/00 , H01L21/48 , H01L21/683 , H01L23/538 , H01L23/31 , H01L21/56 , H01L23/00 , H01L25/065 , H01L25/10 , H01L25/16 , H01L23/498 , H01L23/50
CPC分类号： H01L25/50 , H01L21/4853 , H01L21/486 , H01L21/568 , H01L21/6835 , H01L23/3128 , H01L23/49816 , H01L23/50 , H01L23/5383 , H01L23/5384 , H01L23/5389 , H01L24/16 , H01L24/17 , H01L24/19 , H01L24/20 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/92 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L2221/68345 , H01L2221/68381 , H01L2224/04105 , H01L2224/05025 , H01L2224/0557 , H01L2224/06181 , H01L2224/12105 , H01L2224/13025 , H01L2224/16145 , H01L2224/16146 , H01L2224/16235 , H01L2224/17181 , H01L2224/2518 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2224/48235 , H01L2224/73204 , H01L2224/73259 , H01L2224/73265 , H01L2224/73267 , H01L2224/83191 , H01L2224/83192 , H01L2224/83815 , H01L2224/92143 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/1035 , H01L2225/1058 , H01L2924/00014 , H01L2924/15311 , H01L2924/18162 , H01L2924/19041 , H01L2924/19042 , H01L2924/19104 , H01L2924/19105 , H01L2924/00012 , H01L2224/81 , H01L2224/83 , H01L2224/45099 , H01L2924/00
摘要： Provided is a method of manufacturing a wafer level package. The method includes forming a repassivation layer that encapsulates a plurality of semiconductor chips isolated from a wafer, forming a through encapsulation via (TEV) in the repassivation layer, forming a redistribution layer electrically connected to the TEV, and forming a bump ball on the redistribution layer.

3. 发明授权

US09449911B1 Fan-out wafer level package and manufacturing method thereof 有权
标题翻译：扇形晶圆级封装及其制造方法
公开(公告)号：US09449911B1
公开(公告)日：2016-09-20
申请号：US14800990
申请日：2015-07-16
申请人： STS Semiconductor & Telecommunications Co., Ltd.
发明人： Hee Cheol Kim , Jae Hyun Yoo , Young Seok Lee
IPC分类号： H01L23/48 , H01L29/40 , H01L23/498 , H01L21/48 , H01L21/56 , H01L23/31
CPC分类号： H01L23/49811 , H01L21/4853 , H01L21/561 , H01L21/568 , H01L23/15 , H01L23/49866 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/83 , H01L24/92 , H01L24/96 , H01L24/97 , H01L2224/04105 , H01L2224/12105 , H01L2224/19 , H01L2224/2919 , H01L2224/32225 , H01L2224/73267 , H01L2224/83192 , H01L2224/92244 , H01L2224/97 , H01L2924/15153 , H01L2924/157 , H01L2924/15788 , H01L2924/3511 , H01L2224/83
摘要： Provided are a wafer level package and a manufacturing method thereof. The wafer level package method includes preparing a patterned wafer, forming a recess in a position, in which a semiconductor chip is to be attached, of the patterned wafer through an etching process, fixing the semiconductor chip to the interior of the recess, and applying a passivation material to portions other than the semiconductor chip within the recess and to an upper end of the wafer. The wafer level package includes a silicon or glass wafer including a recess formed through etching and having an area larger than a semiconductor chip, a semiconductor chip fixed to the interior of the recess, and a passivation material filling an empty space other than the semiconductor chip within the recess and applied to a portion corresponding to an area larger than the semiconductor chip on an upper end of the wafer.
摘要翻译：提供了一种晶片级封装及其制造方法。晶片级封装方法包括：通过蚀刻工艺制备图案化晶片，通过蚀刻工艺，将半导体芯片固定到凹部的内部，并将应用钝化材料到凹部内的半导体芯片以外的部分和晶片的上端。晶片级封装包括硅或玻璃晶片，其包括通过蚀刻形成的凹部，并且具有大于半导体芯片的面积，固定到凹部内部的半导体芯片以及填充除了半导体芯片之外的空白空间的钝化材料并且施加到对应于在晶片上端上的比半导体芯片大的区域的部分。

4. 发明授权

US09349667B2 Method of manufacturing stacked package 有权
标题翻译：堆叠包装的制造方法
公开(公告)号：US09349667B2
公开(公告)日：2016-05-24
申请号：US14255274
申请日：2014-04-17
申请人： STS SEMICONDUCTOR & TELECOMMUNICATIONS CO., LTD.
发明人： Jae Bok Yoo , Hyun Hak Jung , Kyoung Min Song
IPC分类号： H01L23/31 , H01L21/56 , H01L23/498 , H01L23/00 , H01L25/10
CPC分类号： H01L23/3128 , H01L21/56 , H01L23/49811 , H01L23/49816 , H01L24/16 , H01L24/48 , H01L25/105 , H01L2224/16225 , H01L2224/48227 , H01L2225/1023 , H01L2924/00014 , H01L2924/12042 , H01L2924/15311 , H01L2924/1533 , H01L2924/181 , H01L2924/1815 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method of manufacturing a stacked package includes a first process of stacking a semiconductor chip on an upper surface of a PCB having a wiring pattern and a via-hole pad, a second process of forming a photoresist (PR) layer on the upper surface of the PCB having the semiconductor chip and the via-hole pad, a third process of removing the photoresist layer of a remaining region except for an upper portion of the via-hole pad so that a photoresist layer of a via-hole region remains only at the upper portion of the via-hole pad, a fourth process of forming a molding layer by molding the upper surface of the PCB having the semiconductor chip to expose an upper surface of the photoresist layer of the via-hole region, and a fifth process of removing the photoresist layer of the via-hole region to form a via-hole on the via-hole pad.
摘要翻译：制造堆叠封装的方法包括：在具有布线图案和通孔焊盘的PCB的上表面上堆叠半导体芯片的第一工艺，在第一工艺上形成光致抗蚀剂（PR）层的工艺具有半导体芯片和通孔焊盘的PCB，除去通孔焊盘的上部之外的剩余区域的光致抗蚀剂层的第三工序，使得通孔区域的光致抗蚀剂层仅保持在通孔焊盘的上部，通过模制具有半导体芯片的PCB的上表面以暴露通孔区域的光致抗蚀剂层的上表面而形成模制层的第四工艺，以及第五工艺去除通孔区域的光致抗蚀剂层，以在通孔焊盘上形成通孔。

5. 发明授权

US08742551B2 Semiconductor package and method of manufacturing the same 有权
标题翻译：半导体封装及其制造方法
公开(公告)号：US08742551B2
公开(公告)日：2014-06-03
申请号：US13716652
申请日：2012-12-17
申请人： STS Semiconductor & Telecommunications Co., Ltd.
发明人： Min Suh Park
IPC分类号： H01L23/495
CPC分类号： H01L23/495 , H01L21/4821 , H01L21/56 , H01L23/3107 , H01L23/49548 , H01L23/49586 , H01L24/97 , H01L2224/45144 , H01L2224/48247 , H01L2224/97 , H01L2924/1461 , H01L2924/181 , H01L2224/85 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor package including: a lead frame including a chip attachment unit and a lead unit; a semiconductor chip that is mounted on the chip attachment unit of the lead frame; a wire that electrically connects the semiconductor chip to the lead unit; an insulation layer formed in the lead frame under the chip attachment unit; and an encapsulant that seals an upper portion of the lead frame, the semiconductor chip, and the wire, wherein the lead unit does not protrude to the outside of the encapsulant.
摘要翻译：一种半导体封装，包括：引线框架，包括芯片附接单元和引线单元; 安装在引线框的芯片安装单元上的半导体芯片; 将半导体芯片电连接到引线单元的导线; 绝缘层，其形成在所述引线框架下方的所述芯片安装单元下方; 以及密封引线框架，半导体芯片和导线的上部的密封剂，其中引线单元不突出到密封剂的外部。

6. 发明申请

US20130319731A1 PRINTED CIRCUIT BOARD OF SEMICONDUCTOR PACKAGE FOR DECREASING NOISE BY ELECTROMAGNETIC INTERFERENCE 审中-公开
标题翻译：印刷电路板用于通过电磁干扰减少噪音的半导体封装
公开(公告)号：US20130319731A1
公开(公告)日：2013-12-05
申请号：US13846342
申请日：2013-03-18
申请人： STS SEMICONDUCTOR & TELECOMMUNICATIONS CO., LTD.
发明人： Yun Im Lee
IPC分类号： H05K1/02
CPC分类号： H05K1/0216 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/552 , H01L23/66 , H01L24/48 , H01L2223/6616 , H01L2224/48227 , H01L2924/00014 , H01L2924/142 , H01L2924/1435 , H01L2924/15192 , H01L2924/15311 , H05K1/0219 , H05K2201/09354 , H05K2201/09618 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A printed circuit board for a semiconductor package which is capable of reducing noise by electromagnetic interference (EMI), including: an upper circuit layer in which a first circuit pattern is formed; an intermediate circuit layer that is disposed below the upper circuit layer and has a second circuit pattern formed therein; a lower circuit layer that is disposed below the intermediate circuit layer and has a third circuit pattern formed therein; an insulating layer disposed between the first and second circuit patterns and between the second and third circuit patterns; vias that vertically connect the first, second and third circuit patterns; and EMI blocking vias that are arranged along edge portions of the first, second and third circuit patterns and are connected to a ground layer.
摘要翻译：一种用于半导体封装的印刷电路板，其能够通过电磁干扰（EMI）降低噪声，包括：形成第一电路图案的上电路层; 中间电路层，其设置在所述上电路层的下方，并且形成有第二电路图案; 下电路层，其设置在所述中间电路层的下方，并且具有形成在其中的第三电路图案; 设置在第一和第二电路图案之间以及第二和第三电路图案之间的绝缘层; 垂直连接第一，第二和第三电路图案的通孔; 以及沿着第一，第二和第三电路图案的边缘部分布置并连接到接地层的EMI阻挡通孔。

7. 发明授权

US08202744B2 Wafer through silicon via forming method and equipment therefor 有权
标题翻译：通过其形成方法和设备通过硅晶片
公开(公告)号：US08202744B2
公开(公告)日：2012-06-19
申请号：US12512813
申请日：2009-07-30
申请人： Jung Hwan Chun , Gyu Han Kim
发明人： Jung Hwan Chun , Gyu Han Kim
IPC分类号： H01L21/00
CPC分类号： H01L21/76898
摘要： Provided are a wafer through silicon via (TSV) forming method and equipment therefor. The wafer TSV forming method includes the operations of arranging a wafer having a front surface having a circuit area patterned thereon; recognizing locations of bond pads in the circuit area of the front surface of the wafer by using an image recognition camera, and converting the recognition of the locations into bond pad location information with respect to a back surface of the wafer; flipping the wafer; forming etching holes with middle depth in the back surface of the wafer by using a laser in a manner to match the locations of the bond pads by using the bond pad location information from the image recognition camera; and performing a plasma isotropic etching on the back surface having formed therein the etching holes with middle depth, thereby forming TSVs penetrating the bond pads.
摘要翻译：提供了一种晶片通过硅通孔（TSV）的形成方法及其设备。晶片TSV形成方法包括布置具有其上形成有电路区域的正面的晶片的操作; 通过使用图像识别照相机识别晶片正面的电路区域中的接合焊盘的位置，并且将位置的识别转换为相对于晶片的背面的接合焊盘位置信息; 翻转晶片; 通过使用激光以通过使用来自图像识别照相机的接合焊盘位置信息来匹配接合焊盘的位置的方式在晶片的后表面中形成具有中间深度的蚀刻孔; 并且在其中形成有具有中间深度的蚀刻孔的背表面上进行等离子体各向同性蚀刻，从而形成贯穿接合焊盘的TSV。

8. 发明授权

US09905436B2 Wafer level fan-out package and method for manufacturing the same 有权
公开(公告)号：US09905436B2
公开(公告)日：2018-02-27
申请号：US15054097
申请日：2016-02-25
申请人： STS Semiconductor & Telecommunications Co., Ltd.
发明人： You Jin Oh , Eun Dong Kim , Jong Won Lee , Jai Kyoung Choi
IPC分类号： H01L21/00 , H01L21/48 , H01L21/56
CPC分类号： H01L21/4825 , H01L21/4828 , H01L21/4842 , H01L21/4882 , H01L21/56 , H01L21/568 , H01L23/36 , H01L23/49816 , H01L23/5384 , H01L23/5389 , H01L24/19 , H01L25/0657 , H01L2224/04105 , H01L2224/12105 , H01L2224/16227 , H01L2224/32145 , H01L2224/73204 , H01L2224/73267 , H01L2224/92244
摘要： A method for manufacturing a wafer level fan-out package includes attaching a semiconductor chip on a partial area of an IO pattern formed on one surface of a wafer, forming a first passivation layer on surfaces of the semiconductor chip and the wafer, forming an RDL (redistribution layer) that is electrically conducted with the IO pattern and the semiconductor chip, in a partial area of a top surface of the first passivation layer, and forming a second passivation layer on the top surface of the first passivation layer and a partial surface of the RDL.

9. 发明申请

US20150228507A1 METHOD OF MANUFACTURING STACKED PACKAGE 有权
标题翻译：制造堆叠包装的方法
公开(公告)号：US20150228507A1
公开(公告)日：2015-08-13
申请号：US14255274
申请日：2014-04-17
申请人： STS SEMICONDUCTOR & TELECOMMUNICATIONS CO., LTD.
发明人： Jae Bok YOO , Hyun Hak JUNG , Kyoung Min SONG
IPC分类号： H01L21/56
CPC分类号： H01L23/3128 , H01L21/56 , H01L23/49811 , H01L23/49816 , H01L24/16 , H01L24/48 , H01L25/105 , H01L2224/16225 , H01L2224/48227 , H01L2225/1023 , H01L2924/00014 , H01L2924/12042 , H01L2924/15311 , H01L2924/1533 , H01L2924/181 , H01L2924/1815 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method of manufacturing a stacked package includes a first process of stacking a semiconductor chip on an upper surface of a PCB having a wiring pattern and a via-hole pad, a second process of forming a photoresist (PR) layer on the upper surface of the PCB having the semiconductor chip and the via-hole pad, a third process of removing the photoresist layer of a remaining region except for an upper portion of the via-hole pad so that a photoresist layer of a via-hole region remains only at the upper portion of the via-hole pad, a fourth process of forming a molding layer by molding the upper surface of the PCB having the semiconductor chip to expose an upper surface of the photoresist layer of the via-hole region, and a fifth process of removing the photoresist layer of the via-hole region to form a via-hole on the via-hole pad.
摘要翻译：制造堆叠封装的方法包括：在具有布线图案和通孔焊盘的PCB的上表面上堆叠半导体芯片的第一工艺，在第一工艺上形成光致抗蚀剂（PR）层的工艺具有半导体芯片和通孔焊盘的PCB，除去通孔焊盘的上部之外的剩余区域的光致抗蚀剂层的第三工序，使得通孔区域的光致抗蚀剂层仅保持在通孔焊盘的上部，通过模制具有半导体芯片的PCB的上表面以暴露通孔区域的光致抗蚀剂层的上表面而形成模制层的第四工艺，以及第五工艺去除通孔区域的光致抗蚀剂层，以在通孔焊盘上形成通孔。

10. 发明授权

US08941225B2 Integrated circuit package and method for manufacturing the same 有权
标题翻译：集成电路封装及其制造方法
公开(公告)号：US08941225B2
公开(公告)日：2015-01-27
申请号：US13932930
申请日：2013-07-01
申请人： STS Semiconductor & Telecommunications Co., Ltd.
发明人： Daesik Choi , Seung Hoon Oh
IPC分类号： H01L23/02 , H01L23/22 , H01L23/10 , H01L21/44 , H01L21/50 , H01L25/065 , H01L25/00
CPC分类号： H01L25/50 , H01L23/3128 , H01L23/49811 , H01L23/49827 , H01L23/49833 , H01L23/49838 , H01L24/13 , H01L24/16 , H01L24/48 , H01L24/81 , H01L24/85 , H01L25/105 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/48227 , H01L2224/81801 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/00014 , H01L2924/12042 , H01L2924/15311 , H01L2924/181 , H01L2924/3511 , H01L2924/014 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： A stacked integrated circuit package and a method for manufacturing the same are provided. The stacked integrated circuit package includes a first integrated circuit package comprising a first substrate, a first semiconductor chip, and a first molding portion, an interposer mounted on the first substrate to be electrically connected to the circuit pattern of the first substrate by a first solder bump, the interposer being provided with an opening to accommodate the first semiconductor chip, and a second integrated circuit package stacked on the first integrated circuit package and the interposer and electrically connected to the interposer by a second solder bump, the second integrated circuit package comprising a second substrate, a second semiconductor chip, and a second molding portion.
摘要翻译：提供一种堆叠集成电路封装及其制造方法。堆叠集成电路封装包括第一集成电路封装，其包括第一基板，第一半导体芯片和第一模制部分，安装在第一基板上以通过第一焊料电连接到第一基板的电路图案的插入器所述插入件设置有容纳所述第一半导体芯片的开口以及堆叠在所述第一集成电路封装和所述插入件上并通过第二焊料凸块电连接到所述插入件的第二集成电路封装，所述第二集成电路封装包括第二基板，第二半导体芯片和第二模制部分。

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