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    • 3. 发明申请
    • System, medium and method of encoding/decoding multi-channel audio signals
    • 多声道音频信号编码/解码的系统,媒介和方法
    • US20110293099A1
    • 2011-12-01
    • US13137292
    • 2011-08-03
    • Junghee KimMino LeiEunmi Oh
    • Junghee KimMino LeiEunmi Oh
    • H04R5/00
    • H03M7/30G10L19/008G10L19/167H04H20/80H04S3/002H04S3/008H04S2420/03
    • An system, method, and method of encoding/decoding a multi-channel audio signal, including a decoding level generation unit producing decoding-level information that helps a bitstream including a number of audio channel signals and space information to be decoded into a number of audio channel signals, wherein the space information includes information about magnitude differences and/or similarities between channels, and an audio decoder decoding the bitstream according to the decoding-level information. Accordingly, even a single input bitstream can be decoded into a suitable number of channels depending on the type of a speaker configuration used. Scalable channel decoding can be achieved by partially decoding an input bitstream. In the scalable channel decoding, a decoder may set decoding levels and outputs audio channel signals according to the decoding levels, thereby reducing decoding complexity.
    • 一种对多声道音频信号进行编码/解码的系统,媒体和方法,包括解码电平生成单元,其产生解码级信息,该解码电平信息有助于将包含多个音频信道信号的位流和空间信息解码为多个 音频信道信号,其中所述空间信息包括关于信道之间的幅度差异和/或相似性的信息,以及根据所述解码级别信息对所述比特流进行解码的音频解码器。 因此,即使单个输入比特流也可以根据所使用的扬声器配置的类型被解码为适当数量的信道。 可以通过对输入比特流进行部分解码来实现可扩展的信道解码。 在可扩展信道解码中,解码器可以根据解码电平设置解码电平并输出音频信道信号,从而降低解码复杂度。
    • 6. 发明授权
    • Unit cell of a non-volatile memory device, a non-volatile memory device and method thereof
    • 非易失性存储器件的单元,非易失性存储器件及其方法
    • US07551491B2
    • 2009-06-23
    • US11715404
    • 2007-03-08
    • Won-joo KimSuk-pil KimJae-woong HyunYoon-dong ParkJune-mo Koo
    • Won-joo KimSuk-pil KimJae-woong HyunYoon-dong ParkJune-mo Koo
    • G11C11/34
    • G11C16/0433G11C16/0491G11C16/10H01L27/115H01L27/11521H01L27/11524H01L27/11568
    • Unit cells of a non-volatile memory device and a method thereof are provided. In an example, the unit cell may include a first memory transistor and a second memory transistor connected to each other in series and further connected in common to a word line, the first and second memory transistors including first and second storage nodes, respectively, the first and second storage nodes configured to execute concurrent memory operations. In another example, the unit cell may include a semiconductor substrate in which first and second bit line regions are defined, first and second storage node layers respectively formed on the semiconductor substrate between the first and second bit line regions, a first pass gate electrode formed on the semiconductor substrate between the first bit line region and the first storage node layer, a second pass gate electrode formed on the semiconductor substrate between the second bit line region and the second storage node layer, a third pass gate electrode formed on the semiconductor substrate between the first and second storage node layers, a third bit line region formed in a portion of the semiconductor substrate under the third pass gate electrode and a control gate electrode extending across the first and second storage node layers. The example unit cells may be implemented within a non-volatile memory device (e.g., a flash memory device), such that the non-volatile memory device may include a plurality of example unit cells.
    • 提供非易失性存储器件的单元电池及其方法。 在一个示例中,单元可以包括串联连接并进一步连接到字线的第一存储晶体管和第二存储晶体管,第一和第二存储晶体管分别包括第一和第二存储节点, 配置为执行并发存储器操作的第一和第二存储节点。 在另一示例中,单元可以包括其中限定了第一和第二位线区域的半导体衬底,分别形成在第一和第二位线区域之间的半导体衬底上的第一和第二存储节点层,形成的第一遍栅极电极 在第一位线区域和第一存储节点层之间的半导体衬底上,形成在第二位线区域和第二存储节点层之间的半导体衬底上的第二遍栅极电极,形成在半导体衬底上的第三栅极电极 在所述第一和第二存储节点层之间形成第三位线区域,所述第三位线区域形成在所述第三栅极电极下方的所述半导体衬底的一部分中,以及跨越所述第一和第二存储节点层延伸的控制栅电极。 示例性单元单元可以在非易失性存储器件(例如,闪存器件)内实现,使得非易失性存储器件可以包括多个示例单位单元。