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1. 发明授权

US07279699B2 Integrated circuit comprising a waveguide having an energy band engineered superlattice 有权
标题翻译：集成电路包括具有能带工程超晶格的波导
公开(公告)号：US07279699B2
公开(公告)日：2007-10-09
申请号：US10937071
申请日：2004-09-09
申请人： Robert J. Mears , Robert John Stephenson
发明人： Robert J. Mears , Robert John Stephenson
IPC分类号： G02F1/017
CPC分类号： H01L29/1054 , H01L21/823807 , H01L29/155 , H01L29/7833
摘要： An integrated circuit may include at least one active optical device and a waveguide coupled thereto. The waveguide may include a superlattice including a plurality of stacked groups of layers. Each group of layers of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. The energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
摘要翻译：集成电路可以包括至少一个有源光学器件和耦合到其上的波导。波导可以包括包括多个堆叠的层组的超晶格。超晶格的每组层可以包括在其上限定基极半导体部分和能带改性层的多个堆叠的基底半导体单层。能带修改层可以包括约束在相邻的基底半导体部分的晶格内的至少一个非半导体单层。

2. 发明授权

US07265002B2 Method for making a semiconductor device including a MOSFET having a band-engineered superlattice with a semiconductor cap layer providing a channel 有权
标题翻译：制造半导体器件的方法，该半导体器件包括具有带状工程超晶格的MOSFET，其具有提供沟道的半导体盖层
公开(公告)号：US07265002B2
公开(公告)日：2007-09-04
申请号：US11042272
申请日：2005-01-25
申请人： Robert J. Mears , Jean Augustin Chan Sow Fook Yiptong , Marek Hytha , Scott A. Kreps , Ilija Dukovski
发明人： Robert J. Mears , Jean Augustin Chan Sow Fook Yiptong , Marek Hytha , Scott A. Kreps , Ilija Dukovski
IPC分类号： H01L21/20
CPC分类号： H01L29/1054 , H01L21/823807 , H01L29/155 , H01L29/7833
摘要： A method for making a semiconductor device may include providing a substrate, and forming at least one MOSFET adjacent the substrate by forming a superlattice including a plurality of stacked groups of layers and a semiconductor cap layer on an uppermost group of layers. Each group of layers of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming source, drain, and gate regions defining a channel through at least a portion of the semiconductor cap layer.
摘要翻译：制造半导体器件的方法可以包括提供衬底，以及通过在最上层组上形成包括多层堆叠层和半导体帽层的超晶格，形成与衬底相邻的至少一个MOSFET。超晶格的每组层可以包括限定基极半导体部分的多个堆叠的基底半导体单层和限制在相邻的基极半导体部分的晶格内的至少一个非半导体单层。该方法还可以包括形成通过半导体盖层的至少一部分限定沟道的源极，漏极和栅极区域。

3. 发明申请

US20070194298A1 SEMICONDUCTOR DEVICE COMPRISING A LATTICE MATCHING LAYER 有权
标题翻译：包含层间匹配层的半导体器件
公开(公告)号：US20070194298A1
公开(公告)日：2007-08-23
申请号：US11677098
申请日：2007-02-21
申请人： Ilija Dukovski , Robert Stephenson , Jean Augustin Yiptong , Samed Halilov , Robert Mears , Xiangyang Huang , Marek Hytha
发明人： Ilija Dukovski , Robert Stephenson , Jean Augustin Yiptong , Samed Halilov , Robert Mears , Xiangyang Huang , Marek Hytha
IPC分类号： H01L29/06
CPC分类号： H01L29/155 , H01L21/0237 , H01L21/02381 , H01L21/02439 , H01L21/0245 , H01L21/02488 , H01L21/02499 , H01L21/02507 , H01L21/0251 , H01L21/02521 , H01L21/02532 , H01L21/28194 , H01L21/28255 , H01L29/1079 , H01L29/1083 , H01L29/152 , H01L29/51 , H01L29/513 , H01L29/78
摘要： A semiconductor device may include a first monocrystalline layer comprising a first material having a first lattice constant. A second monocrystalline layer may include a second material having a second lattice constant different than the first lattice constant. The device may also include a lattice matching layer between the first and second monocrystalline layers and comprising a superlattice. The superlattice may include a plurality of groups of layers, and each group of layers may include a plurality of stacked semiconductor monolayers defining a semiconductor base portion and at least one non-semiconductor monolayer thereon. The at least one non-semiconductor monolayer may be constrained within a crystal lattice of adjacent base semiconductor portions, and at least some semiconductor atoms from opposing base semiconductor portions may be chemically bound together through the at least one non-semiconductor monolayer therebetween.
摘要翻译：半导体器件可以包括包含具有第一晶格常数的第一材料的第一单晶层。第二单晶层可以包括具有不同于第一晶格常数的第二晶格常数的第二材料。该器件还可以包括第一和第二单晶层之间的晶格匹配层并且包括超晶格。超晶格可以包括多组层，并且每组层可以包括多个层叠的半导体单层，其限定半导体基底部分和至少一个非半导体单层。至少一个非半导体单层可以被约束在相邻的基底半导体部分的晶格内，并且来自相对的基极半导体部分的至少一些半导体原子可以通过其间的至少一个非半导体单层化学地结合在一起。

4. 发明申请

US20070166928A1 METHOD FOR MAKING AN ELECTRONIC DEVICE INCLUDING A SELECTIVELY POLABLE SUPERLATTICE 审中-公开
标题翻译：制造电子设备的方法，包括可选择的超级电容
公开(公告)号：US20070166928A1
公开(公告)日：2007-07-19
申请号：US11614559
申请日：2006-12-21
申请人： Samed Halilov , Xiangyang Huang , Ilija Dukovski , Jean Augustin Yiptong , Robert Mears , Marek Hytha , Robert Stephenson
发明人： Samed Halilov , Xiangyang Huang , Ilija Dukovski , Jean Augustin Yiptong , Robert Mears , Marek Hytha , Robert Stephenson
IPC分类号： H01L21/336
CPC分类号： H01L29/152 , B82Y10/00 , G01J5/34 , H01L28/55 , H01L29/151 , H01L29/40111 , H01L29/40117 , H01L29/516 , H01L29/78391 , H01L29/7881 , H01L37/025 , H01L41/183 , H03H9/02543
摘要： A method for making an electronic device may include forming a selectively polable superlattice comprising a plurality of stacked groups of layers. Each group of layers of the selectively polable superlattice may include a plurality of stacked semiconductor monolayers defining a semiconductor base portion and at least one non-semiconductor monolayer thereon. The at least one non-semiconductor monolayer may be constrained within a crystal lattice of adjacent silicon portions, and at least some semiconductor atoms from opposing base semiconductor portions may be chemically bound together through the at least one non-semiconductor monolayer therebetween. The method may further include coupling at least one electrode to the selectively polable superlattice for selective poling thereof.
摘要翻译：制造电子器件的方法可以包括形成包括多个堆叠层组的选择性可覆盖的超晶格。选择性可定向超晶格的每组层可以包括限定半导体基底部分和其上的至少一个非半导体单层的多个堆叠的半导体单层。至少一个非半导体单层可以被约束在相邻硅部分的晶格内，并且来自相对的基极半导体部分的至少一些半导体原子可以通过其间的至少一个非半导体单层化学地结合在一起。所述方法还可以包括将至少一个电极耦合到所述选择性可触发的超晶格以用于其选择性极化。

5. 发明申请

US20070020860A1 Method for Making Semiconductor Device Including a Strained Superlattice and Overlying Stress Layer and Related Methods 审中-公开
标题翻译：包括应变超晶格和上覆应力层的半导体器件的方法及相关方法
公开(公告)号：US20070020860A1
公开(公告)日：2007-01-25
申请号：US11457293
申请日：2006-07-13
申请人： Robert Mears , Scott Kreps
发明人： Robert Mears , Scott Kreps
IPC分类号： H01L21/336
CPC分类号： H01L29/1054 , B82Y10/00 , H01L29/151 , H01L29/78
摘要： A method for making a semiconductor device may include forming a superlattice layer including a plurality of stacked groups of layers, and forming a stress layer above the strained superlattice layer to induce a strain therein. Each group of layers of the superlattice layer may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
摘要翻译：制造半导体器件的方法可以包括形成包括多个层叠层的超晶格层，并且在应变超晶格层上形成应力层以在其中引起应变。超晶格层的每组层可以包括限定基极半导体部分的多个层叠的基底半导体单层，以及约束在相邻的基极半导体部分的晶格内的至少一个非半导体单层。

6. 发明申请

US20070012909A1 Semiconductor Device Including a Strained Superlattice Between at Least One Pair of Spaced Apart Stress Regions 有权
标题翻译：包括应变超晶格的半导体器件在至少一对间距应力区域之间
公开(公告)号：US20070012909A1
公开(公告)日：2007-01-18
申请号：US11457269
申请日：2006-07-13
申请人： Robert Mears , Scott Kreps
发明人： Robert Mears , Scott Kreps
IPC分类号： H01L29/06
CPC分类号： H01L29/1054 , H01L29/152 , H01L29/78
摘要： A semiconductor device may include at least one pair of spaced apart stress regions, and a strained superlattice layer between the at least one pair of spaced apart stress regions and including a plurality of stacked groups of layers. Each group of layers of the strained superlattice layer may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
摘要翻译：半导体器件可以包括至少一对间隔开的应力区域和在至少一对间隔应力区域之间的应变超晶格层，并且包括多个堆叠的层组。应变超晶格层的每组层可以包括限定基极半导体部分的多个层叠的基底半导体单层和限制在相邻的基极半导体部分的晶格内的至少一个非半导体单层。

7. 发明申请

US20060289049A1 Semiconductor Device Having a Semiconductor-on-Insulator (SOI) Configuration and Including a Superlattice on a Thin Semiconductor Layer 审中-公开
标题翻译：具有半导体绝缘体（SOI）配置并在薄半导体层上包括超晶格的半导体器件
公开(公告)号：US20060289049A1
公开(公告)日：2006-12-28
申请号：US11428015
申请日：2006-06-30
申请人： Kalipatnam Rao
发明人： Kalipatnam Rao
IPC分类号： H01L35/34
CPC分类号： H01L29/1054 , H01L21/7624 , H01L29/152 , H01L29/155 , H01L29/40114 , H01L29/665 , H01L29/66636 , H01L29/66825 , H01L29/78687 , H01L29/78696 , H01L29/7881
摘要： A semiconductor device may include a substrate, an insulating layer on the substrate, and a semiconductor layer on the insulating layer on a side thereof opposite the substrate. The semiconductor device may further include a superlattice on the semiconductor layer on a side thereof opposite the insulating layer. The superlattice may include a plurality of stacked groups of layers, with each group comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon. The at least one non-semiconductor monolayer may be constrained within a crystal lattice of adjacent base semiconductor portions.
摘要翻译：半导体器件可以包括衬底，衬底上的绝缘层，以及在与衬底相对的一侧的绝缘层上的半导体层。半导体器件还可以在半导体层的与绝缘层相对的一侧上包括超晶格。超晶格可以包括多个堆叠的层组，每个组包括限定基极半导体部分和至少一个非半导体单层的多个堆叠的基底半导体单层。所述至少一个非半导体单层可以被约束在相邻的基底半导体部分的晶格内。

8. 发明申请

US20060270169A1 Method for Making a Semiconductor Device Including Shallow Trench Isolation (STI) Regions with a Superlattice Therebetween 有权
标题翻译：制造半导体器件的方法包括在其间具有超晶格的浅沟槽隔离（STI）区域
公开(公告)号：US20060270169A1
公开(公告)日：2006-11-30
申请号：US11425209
申请日：2006-06-20
申请人： Kalipatnam Rao
发明人： Kalipatnam Rao
IPC分类号： H01L21/336
CPC分类号： H01L21/823807 , B82Y10/00 , H01L21/823878 , H01L29/1054 , H01L29/1083 , H01L29/152 , H01L29/155 , H01L29/6659 , H01L29/7833
摘要： A method for making a semiconductor device may include forming a plurality of shallow trench isolation (STI) regions in a semiconductor substrate. Further, a plurality of layers may be deposited over the substrate to define respective superlattices over the substrate between adjacent STI regions and to define respective non-monocrystalline regions over the STI regions. The method may further include selectively removing at least portions of the non-monocrystalline regions using at least one active area (AA) mask.
摘要翻译：制造半导体器件的方法可以包括在半导体衬底中形成多个浅沟槽隔离（STI）区域。此外，可以在衬底上沉积多个层以在相邻STI区之间的衬底上限定相应的超晶格并且在STI区上限定相应的非单晶区。该方法可以进一步包括使用至少一个有效面积（AA）掩模来选择性地去除非单晶区域的至少一部分。

9. 发明申请

US20060267130A1 Semiconductor Device Including Shallow Trench Isolation (STI) Regions with a Superlattice Therebetween 审中-公开
标题翻译：包括在其间具有超晶格的浅沟槽隔离（STI）区域的半导体器件
公开(公告)号：US20060267130A1
公开(公告)日：2006-11-30
申请号：US11425201
申请日：2006-06-20
申请人： Kalipatnam Rao
发明人： Kalipatnam Rao
IPC分类号： H01L29/00
CPC分类号： H01L29/1054 , H01L21/823807 , H01L21/823878 , H01L29/1083 , H01L29/6659 , H01L29/7833
摘要： A semiconductor device may include a semiconductor substrate and a plurality of shallow trench isolation (STI) regions in the substrate. More particularly, at least some of the STI regions may include divots therein. The semiconductor device may further include a respective superlattice between adjacent STI regions, and respective non-monocrystalline stringers in the divots.
摘要翻译：半导体器件可以包括半导体衬底和衬底中的多个浅沟槽隔离（STI）区域。更具体地，STI区域中的至少一些可以包括其中的纹理。半导体器件还可以包括在相邻STI区域之间的相应超晶格，以及在纹间中的相应的非单晶桁条。

10. 发明申请

US20060243964A1 METHOD FOR MAKING A SEMICONDUCTOR DEVICE HAVING A SEMICONDUCTOR-ON-INSULATOR CONFIGURATION AND A SUPERLATTICE 审中-公开
标题翻译：制造具有半导体绝缘体构造和超导体的半导体器件的方法
公开(公告)号：US20060243964A1
公开(公告)日：2006-11-02
申请号：US11381850
申请日：2006-05-05
申请人： Scott Kreps , Kalipatnam Rao
发明人： Scott Kreps , Kalipatnam Rao
IPC分类号： H01L29/06
CPC分类号： H01L29/155 , H01L29/1054 , H01L29/40114 , H01L29/66825 , H01L29/7881
摘要： A method for making a semiconductor device may include forming an insulating layer adjacent a substrate, forming a superlattice adjacent a semiconductor layer, and positioning the semiconductor layer adjacent a face of the insulating layer opposite the substrate. The method may further include forming a gate overlying the superlattice, and forming source and drain regions on the semiconductor layer so that the superlattice extends therebetween to define a channel. The superlattice may include a plurality of stacked groups of layers with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. The energy band-modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
摘要翻译：制造半导体器件的方法可以包括在衬底附近形成绝缘层，在半导体层附近形成超晶格，并且将半导体层定位在与衬底相对的绝缘层的表面附近。该方法还可以包括形成覆盖超晶格的栅极，以及在半导体层上形成源极和漏极区域，使得超晶格在其间延伸以限定沟道。超晶格可以包括多个堆叠的层组，其中每组层包括限定基极半导体部分和其上的能带修饰层的多个层叠的基底半导体单层。能带修饰层可以包括约束在相邻的基底半导体部分的晶格内的至少一个非半导体单层。

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