专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08365580B2 System and method for automatically judging the sealing effectiveness of a sealed compartment 有权
标题翻译：用于自动判断密封舱密封效能的系统和方法
公开(公告)号：US08365580B2
公开(公告)日：2013-02-05
申请号：US11270052
申请日：2005-11-09
申请人： Michael Stumpf
发明人： Michael Stumpf
IPC分类号： G01N29/02
CPC分类号： G01M17/007 , G01M3/24
摘要： An improved and non-destructive test method and system utilizes ultrasound wave energy to automatically judge the sealing effectiveness of a sealed compartment such as the cabin of a motor vehicle or aircraft. An ultrasonic transmitter generates ultrasound energy of a specified frequency within the compartment, and one or more ultrasound sensors outside the volume detect the presence and amplitude of ultrasound energy at the specified frequency. Alternatively, the transmitter can be configured to generate ultrasound energy outside the compartment, and the sensors can be arranged to detect ultrasound energy within the compartment. The detected energy level is compared to a calibrated threshold, and a leak indication is generated if the threshold is exceeded. In a factory setting, the volume can be passed through an arched array of ultrasound sensors strategically located to detect the presence and amplitude of ultrasound energy of the specified frequency in the vicinity of potential leakage areas of the compartment. If the position of the compartment relative to the sensor array is known, the leak indication can be used to pinpoint the location of the leak, and to suggest specific corrective action.
摘要翻译：改进的非破坏性测试方法和系统利用超声波能量来自动判断诸如机动车辆或飞行器舱室的密封舱的密封效果。超声波发射器产生在隔室内的指定频率的超声能量，并且体外的一个或多个超声波传感器检测在指定频率的超声能量的存在和幅度。或者，发射机可以被配置为在隔室外产生超声波能量，并且传感器可被布置成检测隔室内的超声能量。将检测到的能量水平与校准的阈值进行比较，并且如果超过阈值则产生泄漏指示。在工厂设置中，体积可以通过位于策略位置的拱形阵列的超声波传感器，以检测隔室潜在泄漏区域附近的指定频率的超声能量的存在和幅度。如果隔室相对于传感器阵列的位置是已知的，则可以使用泄漏指示来确定泄漏的位置，并提出具体的纠正措施。

2. 发明申请

US20120124333A1 ADAPTIVE INTEGRATED CIRCUITRY WITH HETEROGENEOUS AND RECONFIGURABLE MATRICES OF DIVERSE AND ADAPTIVE COMPUTATIONAL UNITS HAVING FIXED, APPLICATION SPECIFIC COMPUTATIONAL ELEMENTS 有权
标题翻译：具有固定的特殊计算元素的多变量和自适应计算单元的异构和可重构矩阵的自适应集成电路
公开(公告)号：US20120124333A1
公开(公告)日：2012-05-17
申请号：US13353764
申请日：2012-01-19
申请人： Paul L. Master , Eugene Hogenauer , Walter James Scheuermann
发明人： Paul L. Master , Eugene Hogenauer , Walter James Scheuermann
IPC分类号： G06F15/76 , G06F9/315 , G06F9/38 , G06F9/302 , G06F9/305
CPC分类号： G06F15/7867 , G06F13/4027 , Y02D10/12 , Y02D10/13
摘要： The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations. The various fixed architectures are selected to comparatively minimize power consumption and increase performance of the adaptive computing integrated circuit, particularly suitable for mobile, hand-held or other battery-powered computing applications.
摘要翻译：本发明涉及一种新类型的集成电路和用于自适应或可重新配置计算的新方法。优选的IC实施例包括耦合到互连网络的多个异构计算元件。多个异构计算元件包括具有固定和不同架构的对应的计算元件，例如用于不同功能的固定架构，例如存储器，加法，乘法，复数乘法，减法，配置，重配置，控制，输入，输出和现场可编程性。响应于配置信息，互连网络可实时操作以配置和重新配置用于多种不同功能模式的多个异构计算元件，包括线性算法运算，非线性算法运算，有限状态机操作，存储器操作和位级操作。选择各种固定架构以相对最小化功率消耗并增加自适应计算集成电路的性能，特别适用于移动，手持或其他电池供电的计算应用。

3. 再颁专利

USRE43393E1 Method and system for creating and programming an adaptive computing engine 有权
标题翻译：用于创建和编程自适应计算引擎的方法和系统
公开(公告)号：USRE43393E1
公开(公告)日：2012-05-15
申请号：US12504093
申请日：2009-07-16
申请人： Paul L. Master
发明人： Paul L. Master
IPC分类号： G06F17/50
CPC分类号： G06F15/7867 , G06F17/5027
摘要： A system for creating an adaptive computing engine (ACE) includes algorithmic elements adaptable for use in the ACE and configured to provide algorithmic operations, and provides mapping of the algorithmic operations to heterogeneous nodes. The mapping is for initially configuring the heterogeneous nodes to provide appropriate hardware circuit functions that perform algorithmic operations. A reconfigurable interconnection network interconnects the heterogeneous nodes. The mapping includes selecting a combination of ACE building blocks from the ACE building block types for the appropriate hardware circuit functions. The system and corresponding method also includes utilizing the algorithmic operations for optimally configuring the heterogeneous nodes to provide the appropriate hardware circuit function. The utilizing includes the simulating of the performance of the ACE with the combination of ACE building blocks and altering the combination until predetermined performance standards that determine the efficiency of the ACE are met while simulating performance of the ACE.
摘要翻译：用于创建自适应计算引擎（ACE）的系统包括适于在ACE中使用并被配置为提供算法操作并且提供算法操作到异构节点的映射的算法元件。该映射用于初始配置异构节点以提供执行算法操作的适当的硬件电路功能。可重构互连网络将异构节点互连。该映射包括从ACE构建块类型中选择ACE构建块的组合以获得适当的硬件电路功能。该系统和相应的方法还包括利用算法操作来优化配置异构节点以提供适当的硬件电路功能。利用包括通过ACE构建块的组合模拟ACE的性能，并改变组合，直到在模拟ACE的性能的同时满足决定ACE效率的预定性能标准。

4. 发明授权

US08108656B2 Task definition for specifying resource requirements 有权
标题翻译：指定资源需求的任务定义
公开(公告)号：US08108656B2
公开(公告)日：2012-01-31
申请号：US10233175
申请日：2002-08-29
申请人： Ramana Katragadda , Paul Spoltore , Ric Howard
发明人： Ramana Katragadda , Paul Spoltore , Ric Howard
IPC分类号： G06F9/30 , G06F9/46 , G06F15/76 , G06F15/16
CPC分类号： G06F9/5044
摘要： Task definitions are used by a task scheduler and prioritizer to allocate task operation to a plurality of processing units. The task definition is an electronic record that specifies researching needed by, and other characteristics of, a task to be executed. Resources include types of processing nodes desired to execute the task, needed amount or rate of processing cycles, amount of memory capacity, number of registers, input/output ports, buffer sizes, etc. Characteristics of a task include maximum latency tome, frequency of execution of a task, communication ports, and other characteristics. An exemplary task definition language and syntax is described that uses constructs including other of attempted scheduling operations, percentage or amount of resources desired by different operations, handling of multiple executable images or modules, overlays, port aliases and other features.
摘要翻译：任务定义被任务调度器和优先级分配器用于将任务操作分配给多个处理单元。任务定义是指定要执行的任务所需的研究和其他特征的电子记录。资源包括执行任务所需的处理节点的类型，所需的处理周期数量或速率，存储容量，寄存器数量，输入/输出端口，缓冲区大小等。任务的特征包括最大延迟时间，执行任务，通信端口等特性。描述了一种示例性的任务定义语言和语法，其使用包括其他尝试的调度操作，不同操作所需的资源的百分比或数量，多个可执行映像或模块的处理，覆盖，端口别名和其他特征的构造。

5. 发明授权

US07822109B2 Method and system for reconfigurable channel coding 有权
标题翻译：可重构信道编码的方法和系统
公开(公告)号：US07822109B2
公开(公告)日：2010-10-26
申请号：US10402691
申请日：2003-03-28
申请人： W. James Scheuermann
发明人： W. James Scheuermann
IPC分类号： H04B1/38 , H04L5/12
CPC分类号： H04L1/0043 , H04B1/40 , H04L1/0054 , H04L1/0059 , H04L65/601
摘要： Aspects of a reconfigurable system for providing channel coding in a wireless communication device are described. The aspects include a plurality of computation elements for performing channel coding operations and memory for storing programs to direct each of the plurality of computation elements. A controller controls the plurality of computation elements and stored programs to achieve channel coding operations in accordance with a plurality of wireless communication standards. The plurality of computation elements include a data reordering element, a linear feedback shift register (LFSR) element, a convolutional encoder element, and a Viterbi decoder element.
摘要翻译：描述了用于在无线通信设备中提供信道编码的可重新配置系统的方面。这些方面包括用于执行信道编码操作的多个计算元件和用于存储用于指示多个计算元素中的每一个的程序的存储器。控制器控制多个计算元件和存储的程序，以实现根据多个无线通信标准的信道编码操作。多个计算元件包括数据重排序元件，线性反馈移位寄存器（LFSR）元件，卷积编码器元件和维特比解码器元件。

6. 发明授权

US07752419B1 Method and system for managing hardware resources to implement system functions using an adaptive computing architecture 失效
标题翻译：用于管理硬件资源以使用自适应计算架构来实现系统功能的方法和系统
公开(公告)号：US07752419B1
公开(公告)日：2010-07-06
申请号：US10015530
申请日：2001-12-12
申请人： Robert T. Plunkett , Ghobad Heidari , Paul L. Master
发明人： Robert T. Plunkett , Ghobad Heidari , Paul L. Master
IPC分类号： G06F15/00
CPC分类号： G06F15/177 , G06F15/7867 , Y02D10/12 , Y02D10/13
摘要： The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The exemplary IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations. The various fixed architectures are selected to comparatively minimize power consumption and increase performance of the adaptive computing integrated circuit, particularly suitable for mobile, hand-held or other battery-powered computing applications. In an exemplary embodiment, some or all of the computational elements are alternately configured to implement two or more functions.
摘要翻译：本发明涉及一种新类型的集成电路和用于自适应或可重新配置计算的新方法。示例性IC实施例包括耦合到互连网络的多个异构计算元件。多个异构计算元件包括具有固定和不同架构的对应的计算元件，例如用于不同功能的固定架构，例如存储器，加法，乘法，复数乘法，减法，配置，重配置，控制，输入，输出和现场可编程性。响应于配置信息，互连网络可实时操作以配置和重新配置用于多种不同功能模式的多个异构计算元件，包括线性算法运算，非线性算法运算，有限状态机操作，存储器操作和位级操作。选择各种固定架构以相对最小化功率消耗并增加自适应计算集成电路的性能，特别适用于移动，手持或其他电池供电的计算应用。在示例性实施例中，一些或所有计算元件被交替地配置为实现两个或多个功能。

7. 发明授权

US07653710B2 Hardware task manager 有权
标题翻译：硬件任务经理
公开(公告)号：US07653710B2
公开(公告)日：2010-01-26
申请号：US10443501
申请日：2003-05-21
申请人： W. James Scheuermann , Eugene B. Hogenauer
发明人： W. James Scheuermann , Eugene B. Hogenauer
IPC分类号： G06F15/173 , G06F9/46 , G06F3/00
CPC分类号： G06F3/0613 , G06F3/0656 , G06F3/0659 , G06F3/0673 , G06F9/4881 , G06F9/52 , G06F13/28 , G06F15/17331
摘要： A hardware task manager for managing operations in an adaptive computing system. The task manager indicates when input and output buffer resources are sufficient to allow a task to execute. The task can require an arbitrary number of input values from one or more other (or the same) tasks. Likewise, a number of output buffers must also be available before the task can start to execute and store results in the output buffers. The hardware task manager maintains a counter in association with each input and output buffer. For input buffers, a negative value for the counter means that there is no data in the buffer and, hence, the respective input buffer is not ready or available. Thus, the associated task can not run. Predetermined numbers of bytes, or “units,” are stored into the input buffer and an associated counter is incremented. When the counter value transitions from a negative value to a zero the high-order bit of the counter is cleared, thereby indicating the input buffer has sufficient data and is available to be processed by a task.
摘要翻译：用于管理自适应计算系统中的操作的硬件任务管理器。任务管理器指示输入和输出缓冲区资源何时足以允许任务执行。该任务可能需要来自一个或多个其他（或相同）任务的任意数量的输入值。同样，在任务可以开始执行并将结果存储在输出缓冲区之前，还必须有许多输出缓冲区可用。硬件任务管理器维护与每个输入和输出缓冲器相关联的计数器。对于输入缓冲器，计数器的负值表示缓冲器中没有数据，因此相应的输入缓冲器尚未就绪或可用。因此，相关任务无法运行。预定的字节数或“单位”被存储到输入缓冲器中，相关联的计数器递增。当计数器值从负值转换为零时，计数器的高位被清除，从而指示输入缓冲器具有足够的数据，并可由任务处理。

8. 发明申请

US20090327541A1 ADAPTABLE DATAPATH FOR A DIGITAL PROCESSING SYSTEM 有权
标题翻译：适用于数字处理系统的数据
公开(公告)号：US20090327541A1
公开(公告)日：2009-12-31
申请号：US12556894
申请日：2009-09-10
申请人： Amit RAMCHANDRAN
发明人： Amit RAMCHANDRAN
IPC分类号： G06F13/14 , G06F12/06
CPC分类号： G06F13/287 , G06F9/30014 , G06F9/3012 , G06F9/3824 , G06F9/3826 , G06F9/383 , G06F9/3867 , G06F9/3885 , G06F13/16
摘要： The present invention includes an adaptable high-performance node (RXN) with several features that enable it to provide high performance along with adaptability. A preferred embodiment of the RXN includes a run-time configurable data path and control path. The RXN supports multi-precision arithmetic including 8, 16, 24, and 32 bit codes. Data flow can be reconfigured to minimize register accesses for different operations. For example, multiply-accumulate operations can be performed with minimal, or no, register stores by reconfiguration of the data path. Predetermined kernels can be configured during a setup phase so that the RXN can efficiently execute, e.g., Discrete Cosine Transform (DCT), Fast-Fourier Transform (FFT) and other operations. Other features are provided.
摘要翻译：本发明包括具有若干特征的适应性高性能节点（RXN），使其能够提供高性能以及适应性。 RXN的优选实施例包括运行时可配置数据路径和控制路径。 RXN支持包括8,16,24和32位代码的多精度算术。可以重新配置数据流，以最小化不同操作的寄存器访问。例如，通过重新配置数据路径，可以通过最小或不存在寄存器存储来执行乘法累加操作。可以在建立阶段期间配置预定的内核，使得RXN可以有效地执行例如离散余弦变换（DCT），快速傅里叶变换（FFT）和其他操作。提供其他功能。

9. 发明申请

US20090276583A1 External Memory Controller Node 有权
公开(公告)号：US20090276583A1
公开(公告)日：2009-11-05
申请号：US12437303
申请日：2009-05-07
申请人： Frederick Curtis Furtek , Paul L. Master
发明人： Frederick Curtis Furtek , Paul L. Master
IPC分类号： G06F12/00
CPC分类号： G06F15/167 , G06F3/0626 , G06F3/0661 , G06F3/0679 , G06F13/1657 , G11C7/1072 , H04L67/32
摘要： A memory controller to provide memory access services in an adaptive computing engine is provided. The controller comprises: a network interface configured to receive a memory request from a programmable network; and a memory interface configured to access a memory to fulfill the memory request from the programmable network, wherein the memory interface receives and provides data for the memory request to the network interface, the network interface configured to send data to and receive data from the programmable network.

10. 发明授权

US07606943B2 Adaptable datapath for a digital processing system 失效
标题翻译：适用于数字处理系统的数据路径
公开(公告)号：US07606943B2
公开(公告)日：2009-10-20
申请号：US11800577
申请日：2007-05-03
申请人： Amit Ramchandran
发明人： Amit Ramchandran
IPC分类号： G06F3/00
CPC分类号： G06F13/287 , G06F9/30014 , G06F9/3012 , G06F9/3824 , G06F9/3826 , G06F9/383 , G06F9/3867 , G06F9/3885 , G06F13/16
摘要： The present invention includes a adaptable high-performance node (RXN) with several features that enable it to provide high performance along with adaptability. A preferred embodiment of the RXN includes a run-time configurable data path and control path. The RXN supports multi-precision arithmetic including 8, 16, 24, and 32 bit codes. Data flow can be reconfigured to minimize register accesses for different operations. For example, multiply-accumulate operations can be performed with minimal, or no, register stores by reconfiguration of the data path. Predetermined kernels can be configured during a setup phase so that the RXN can efficiently execute, e.g., discrete cosine transform (DCT), fast-Fourier transform (FFT) and other operations. Other features are provided.
摘要翻译：本发明包括具有几个特征的适应性高性能节点（RXN），使其能够提供高性能以及适应性。 RXN的优选实施例包括运行时可配置数据路径和控制路径。 RXN支持包括8,16,24和32位代码的多精度算术。可以重新配置数据流，以最小化不同操作的寄存器访问。例如，通过重新配置数据路径，可以通过最小或不存在寄存器存储来执行乘法累加操作。可以在建立阶段期间配置预定的内核，使得RXN可以有效地执行例如离散余弦变换（DCT），快速傅里叶变换（FFT）和其他操作。提供其他功能。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式