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1. 发明申请

US20110062586A1 Chip for Reliable Stacking on another Chip 审中-公开
标题翻译：芯片可靠堆叠在另一个芯片上
公开(公告)号：US20110062586A1
公开(公告)日：2011-03-17
申请号：US12814458
申请日：2010-06-13
申请人： Leo Lu , Kuei-Wu Chu , Jimmy Liang
发明人： Leo Lu , Kuei-Wu Chu , Jimmy Liang
IPC分类号： H01L23/538
CPC分类号： H01L23/481 , H01L21/76898 , H01L24/13 , H01L24/16 , H01L2224/16 , H01L2924/01079 , H01L2924/14 , H01L2924/00
摘要： A chip includes a device, a passivation layer, two dielectric layers, at least one upper redistribution layer, at least one lower redistribution layer, at least one tunnel, at least one conductor, a redistribution passivation layer and at least one solder ball. The device includes at least one pad. The tunnel is defined in the upper redistribution layer, the first dielectric layer, the passivation layer, the pad, the device, the chip, the second dielectric layer and the lower redistribution layer. The conductor is located in the tunnel and connected to the upper and lower redistribution layers. The redistribution passivation layer is located on the second dielectric layer, the lower redistribution layer and the conductor. The solder ball is located on a portion of the lower redistribution layer through an aperture defined in the redistribution passivation layer. The chip can be connected to a printed circuit board by the solder ball.
摘要翻译：芯片包括器件，钝化层，两个电介质层，至少一个上再分配层，至少一个下再分配层，至少一个隧道，至少一个导体，再分布钝化层和至少一个焊球。该装置包括至少一个垫。隧道定义在上再分配层，第一介电层，钝化层，焊盘，器件，芯片，第二介电层和下再分布层中。导体位于隧道内并与上，下重分布层连接。再分布钝化层位于第二介电层，下再分布层和导体上。焊球通过限定在再分布钝化层中的孔位于下再分布层的一部分上。芯片可以通过焊球连接到印刷电路板。

2. 发明申请

US20110176021A1 Image-Processing Integrated Circuit 审中-公开
标题翻译：图像处理集成电路
公开(公告)号：US20110176021A1
公开(公告)日：2011-07-21
申请号：US12908078
申请日：2010-10-20
申请人： Tse Ming Chu , Ma Sung Chuan
发明人： Tse Ming Chu , Ma Sung Chuan
IPC分类号： H04N5/228
CPC分类号： H01L27/14618 , H01L2924/0002 , H01L2924/00
摘要： An image-processing integrated circuit includes an image-processing die, a conductive layer, first optical units and a second optical unit. The conductive layer is provided on a face of the image-processing die. The first optical units are provided on an opposite face of the image-processing die. The second optical unit is provided on the first optical units.
摘要翻译：图像处理集成电路包括图像处理管芯，导电层，第一光学单元和第二光学单元。导电层设置在图像处理模具的表面上。第一光学单元设置在图像处理模具的相对面上。第二光学单元设置在第一光学单元上。

3. 发明申请

US20110062590A1 Chip Stacking Device Having Re-Distribution Layer 审中-公开
标题翻译：具有再分配层的芯片堆叠装置
公开(公告)号：US20110062590A1
公开(公告)日：2011-03-17
申请号：US12832776
申请日：2010-07-08
申请人： Leo Lu , Kuei-Wu Chu , Jimmy Liang
发明人： Leo Lu , Kuei-Wu Chu , Jimmy Liang
IPC分类号： H01L23/482
CPC分类号： H01L23/525 , H01L23/3171 , H01L23/4828 , H01L23/5328 , H01L2924/0002 , H01L2924/19041 , H01L2924/00
摘要： A chip stacking device uses nano particle silver paste for re-distribution interconnection to form a structure having low resistance through trench filling or printing. Thus, due to its low resistance, it can effectively reduce the electrical instability due to voltage drop after current flows. Furthermore, power consumption is reduced too, with energy saved. With its stable electrical signal, its utilization scope can be further expanded to high frequency product.
摘要翻译：芯片堆叠装置使用纳米颗粒银浆进行再分配互连，以通过沟槽填充或印刷形成具有低电阻的结构。因此，由于其低电阻，可以有效地降低电流流动后由于电压降引起的电不稳定性。而且，节省能源也减少了功耗。凭借其稳定的电气信号，其利用范围可以进一步扩大到高频产品。

4. 发明申请

US20110108983A1 Integrated Circuit 审中-公开
标题翻译：集成电路
公开(公告)号：US20110108983A1
公开(公告)日：2011-05-12
申请号：US12832765
申请日：2010-07-08
申请人： Leo Lu , Kuei-Wu Chu , Jimmy Liang
发明人： Leo Lu , Kuei-Wu Chu , Jimmy Liang
IPC分类号： H01L23/498
CPC分类号： H01L24/05 , H01L24/03 , H01L24/11 , H01L24/13 , H01L2224/02311 , H01L2224/0401 , H01L2224/05005 , H01L2224/0501 , H01L2224/0502 , H01L2224/05099 , H01L2224/0556 , H01L2224/05599 , H01L2224/11334 , H01L2924/0002 , H01L2924/01047 , H01L2924/0105 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2224/05552 , H01L2924/00
摘要： An integrated circuit includes a die including contacts formed thereon. A first dielectric layer is formed on the die. The first dielectric layer includes apertures defined therein corresponding to the contacts. A second dielectric layer is formed on the second dielectric layer. The second dielectric layer includes apertures defined therein corresponding to the apertures of the first dielectric layer. Redistribution layers are located in the apertures of the first and second dielectric layers and connected to the contacts. A passivation layer is located on the second dielectric layer and the redistribution layers. The passivation layer includes apertures corresponding to the redistribution layers. A solder ball is located in each of the apertures of the passivation layer and connected to a related one of the redistribution layers.
摘要翻译：集成电路包括其上形成有触点的模具。在模具上形成第一电介质层。第一电介质层包括对应于触点的限定在其中的孔。第二电介质层形成在第二电介质层上。第二电介质层包括与第一介电层的孔对应的孔。再分布层位于第一和第二电介质层的孔中并连接到触点。钝化层位于第二介电层和再分配层上。钝化层包括对应于再分布层的孔。焊球位于钝化层的每个孔中并连接到相关的再分布层之一。

5. 发明申请

US20110031635A1 Stacked Integrated Circuit Device 审中-公开
标题翻译：堆叠集成电路器件
公开(公告)号：US20110031635A1
公开(公告)日：2011-02-10
申请号：US12908057
申请日：2010-10-20
申请人： Tse Ming Chu , Sung Chuan MA
发明人： Tse Ming Chu , Sung Chuan MA
IPC分类号： H01L23/52
CPC分类号： H01L25/0657 , H01L23/481 , H01L2225/06513 , H01L2225/06541 , H01L2225/06551 , H01L2924/0002 , H01L2924/00
摘要： A device having stacked integrated circuit (IC) chips is provided. The chips and other wires are connected through circuit contacts and notches or apertures. The notches or apertures are filled with a conductive material. Thus, flexibility of circuit layout is achieved with easy fabrication and enhanced reliability.
摘要翻译：提供具有堆叠集成电路（IC）芯片的器件。芯片和其他电线通过电路触点和凹口或孔连接。缺口或孔被导电材料填充。因此，通过易于制造和增强的可靠性实现电路布局的灵活性。

6. 发明授权

US09559265B2 Flip-chip LED, method for manufacturing the same and flip-chip package of the same 有权
标题翻译：倒装芯片LED，其制造方法和倒装芯片封装相同
公开(公告)号：US09559265B2
公开(公告)日：2017-01-31
申请号：US14664037
申请日：2015-03-20
申请人： Mao Bang Electronic Co., Ltd.
发明人： Christopher Chyu , Ta-Lun Sung , Tung-Sheng Lai
IPC分类号： H01L33/00 , H01L33/46 , H01L33/48
CPC分类号： H01L33/46 , H01L33/0095 , H01L33/486 , H01L2933/0016 , H01L2933/0025
摘要： A flip-chip LED, a method for manufacturing the same and a flip-chip LED package are revealed. The LED includes at least one multi-layer reflective layer covered over the outermost layer thereof. The multi-layer reflective layer includes non-conductive reflective layer or combination of the non-conductive reflective layer with conductive reflective layer. The multi-layer reflective layer is manufactured by physical vapor deposition (PVD) with a mask at one time. The mask is used to form a pattern of the multi-layer reflective layer. Thus a photoresist layer is further formed on surface of exposed electrodes. Then a pumping and venting process is used only once during to complete vacuum deposition of each layer of the multi-layer reflective layer in turn.
摘要翻译：揭示了倒装芯片LED，其制造方法和倒装芯片LED封装。 LED包括覆盖在其最外层上的至少一个多层反射层。多层反射层包括非导电反射层或非导电反射层与导电反射层的组合。多层反射层通过具有掩模的物理气相沉积（PVD）一次制造。该掩模用于形成多层反射层的图案。因此，在暴露的电极的表面上进一步形成光致抗蚀剂层。然后在多层反射层的每层完成真空沉积期间仅使用一次泵送和排气过程。

7. 发明申请

US20120091595A1 Layered Integrated Circuit Apparatus 审中-公开
标题翻译：分层集成电路设备
公开(公告)号：US20120091595A1
公开(公告)日：2012-04-19
申请号：US12906791
申请日：2010-10-18
申请人： Sung Chuan MA , Jimmy Liang
发明人： Sung Chuan MA , Jimmy Liang
IPC分类号： H01L23/52
CPC分类号： H01L29/0657 , H01L24/24 , H01L24/25 , H01L24/82 , H01L25/0657 , H01L2224/02371 , H01L2224/02375 , H01L2224/24146 , H01L2224/245 , H01L2224/2512 , H01L2224/82365 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2225/06551 , H01L2225/06565 , H01L2225/06568 , H01L2924/14 , H01L2924/01047 , H01L2924/00
摘要： A device having layered integrated circuit (IC) chips is provided. The chip comprises notches, conductive area, apertures, and routing pool. A conductive material is set in the apertures. The second chip is layered on the first chip. The notches of the second chip are corresponding to the first conducting area of the first chip. A conductive material is also set in the notch between the conductive area of the first chip and the notches of the second chip. Thus, a system is integrated by layering the first chip and the second chip for enhancing flexibility and reliability of circuit layout.
摘要翻译：提供了具有分层集成电路（IC）芯片的器件。芯片包括缺口，导电区域，孔径和路由池。导电材料设置在孔中。第二芯片分层在第一芯片上。第二芯片的凹口对应于第一芯片的第一导电区域。导电材料也设置在第一芯片的导电区域和第二芯片的凹口之间的凹口中。因此，通过分层第一芯片和第二芯片来集成系统，以增强电路布局的灵活性和可靠性。

8. 发明申请

US20110260300A1 Wafer-Bump Structure 有权
标题翻译：晶圆结构
公开(公告)号：US20110260300A1
公开(公告)日：2011-10-27
申请号：US13083745
申请日：2011-04-11
申请人： Kuei-Wu Chu , Tse Ming Chu
发明人： Kuei-Wu Chu , Tse Ming Chu
IPC分类号： H01L23/58
CPC分类号： H01L24/11 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/0401 , H01L2224/05082 , H01L2224/05118 , H01L2224/05155 , H01L2224/05573 , H01L2224/05644 , H01L2224/1132 , H01L2224/11462 , H01L2224/11464 , H01L2224/131 , H01L2224/13139 , H01L2224/13144 , H01L2224/13582 , H01L2224/13644 , H01L2224/13655 , H01L2224/274 , H01L2924/00013 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/00015 , H01L2924/00014 , H01L2224/13099
摘要： A wafer-bump structure includes a wafer-state semiconductor die, a pre-treatment layer, a first ENIG laminate and at least one pillar bump. The wafer-state semiconductor die includes at least one die pad embedded therein and a passivation layer formed on the wafer-state semiconductor die and the die pad. The passivation layer includes an aperture for allowing access to a portion of the die pad. The pre-treatment layer is formed on the un-covered portion of the die pad. The first ENIG laminate is formed on the pre-treatment layer and an annular portion of the passivation layer around the pre-treatment layer. The pillar bump includes a conductive metal layer and a second ENIG laminate. The conductive metal layer is formed on the first ENIG laminate and another annular portion of the passivation layer around the first ENIG laminate. The second ENIG laminate is formed on the conductive metal layer and another annular portion of the passivation layer around the conductive metal layer.
摘要翻译：晶片凸块结构包括晶片状半导体管芯，预处理层，第一ENIG层压板和至少一个柱状凸块。晶片状半导体管芯包括嵌入其中的至少一个管芯焊盘和形成在晶片状态半导体管芯和管芯焊盘上的钝化层。钝化层包括用于允许访问管芯焊盘的一部分的孔。预处理层形成在管芯焊盘的未覆盖部分上。在预处理层上形成第一个ENIG层压板，在预处理层周围形成钝化层的环形部分。支柱凸块包括导电金属层和第二ENIG层压板。导电金属层形成在第一ENIG层压板上，钝化层的环形部分围绕第一ENIG层压板形成。第二个ENIG层压体形成在导电金属层和围绕导电金属层的钝化层的另一环形部分上。

9. 发明申请

US20110228487A1 Integrated Circuit Card 有权
标题翻译：集成电路卡
公开(公告)号：US20110228487A1
公开(公告)日：2011-09-22
申请号：US12796867
申请日：2010-06-09
申请人： Tse Min Chu , Jimmy Liang
发明人： Tse Min Chu , Jimmy Liang
IPC分类号： H05K1/14
CPC分类号： H01L23/3121 , H01L23/49855 , H01L2224/48091 , H01L2224/48228 , H01L2224/73265 , H01L2224/92247 , H05K3/24 , H05K3/4038 , H05K2201/0305 , H05K2201/0394 , H01L2924/00014
摘要： An integrated circuit card includes a laminate, solder bumps, a die and a package. The laminate includes a core board sandwiched between two conductive layers. The conductive layers are connected to each other with solder bumps filled in apertures defined in the core board. The die is provided on one of the conductive layers. The package is provided on the die and an area of the conductive layer around the die.
摘要翻译：集成电路卡包括层压体，焊料凸块，管芯和封装。层压体包括夹在两个导电层之间的芯板。导电层通过填充在芯板中限定的孔中的焊料凸块相互连接。芯片设置在导电层之一上。该封装设置在管芯上，并且导体层周围的区域。

10. 发明申请

US20110057318A1 Die Package 审中-公开
标题翻译：模具包装
公开(公告)号：US20110057318A1
公开(公告)日：2011-03-10
申请号：US12354348
申请日：2009-01-15
申请人： Sung Chuan MA , Tse Min Chu
发明人： Sung Chuan MA , Tse Min Chu
IPC分类号： H01L23/48
CPC分类号： H01L24/05 , H01L24/03 , H01L2224/05599 , H01L2924/00014 , H01L2924/01005 , H01L2924/01033 , H01L2924/014
摘要： A die is packaged. The package of the die has a line groove filled with a conductive material. A metal pad is exposed out of a solder mask. And the metal pad is connected with a die pad on the die through the line groove in a deflective way. In this way, a wiring space of a wafer is efficiently used; and a manufacturing yield of the wafer is enhanced.
摘要翻译：一个模具被打包。模具的包装具有填充有导电材料的线槽。金属焊盘从焊接掩模露出。并且金属垫通过线槽以偏转的方式与模具上的芯片焊盘连接。以这种方式，有效地使用晶片的布线空间; 并且提高了晶片的制造成品率。

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