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1. 发明授权

US08166090B2 Tiled architecture for stationary-method iterative linear solvers 有权
标题翻译：用于固定方法迭代线性求解器的平铺架构
公开(公告)号：US08166090B2
公开(公告)日：2012-04-24
申请号：US11966633
申请日：2007-12-28
申请人： Matthew Pascal DeLaquil , Deepak Prasanna , Scott Michael Burkart , Joshua D. Anderson , Antone Lee Kusmanoff
发明人： Matthew Pascal DeLaquil , Deepak Prasanna , Scott Michael Burkart , Joshua D. Anderson , Antone Lee Kusmanoff
IPC分类号： G06F7/38
CPC分类号： G06F17/12
摘要： A system for solving linear equations comprises a first circuit including a first multiplication module for multiplying a first row of a matrix by a first instance of a vector variable to generate a first product, and a first linear solver module for calculating an updated first element of the vector variable using the first product. A second circuit includes a second multiplication module for multiplying a second row of the matrix by a second instance of the vector variable to generate a second product, and a second linear solver module for calculating an updated second element of the vector variable using the second product. An interface module updates the second instance of the vector variable with the first updated element, and updates the first instance of the vector variable with the second updated element.
摘要翻译：一种用于求解线性方程的系统包括第一电路，其包括第一乘法模块，用于将矩阵的第一行乘以矢量变量的第一实例以产生第一乘积;以及第一线性求解器模块，用于计算更新的第一元素矢量变量使用第一个产品。第二电路包括第二乘法模块，用于将矩阵的第二行乘以矢量变量的第二实例以产生第二乘积;以及第二线性求解器模块，用于使用第二乘积来计算向量变量的更新的第二元素。接口模块使用第一更新元素更新矢量变量的第二实例，并用第二更新元素更新矢量变量的第一实例。

2. 发明授权

US08149975B2 Method and computer program for identifying a transition in a phase-shift keying or frequency-shift keying signal 有权
标题翻译：用于识别相移键控或频移键控信号中的转换的方法和计算机程序
公开(公告)号：US08149975B2
公开(公告)日：2012-04-03
申请号：US12559207
申请日：2009-09-14
申请人： Stephen Ha
发明人： Stephen Ha
IPC分类号： H04L7/00
CPC分类号： H04L27/2337 , H04L27/144 , H04L27/1563
摘要： A system for identifying at least one phase transition in a phase-shift keying signal comprising a plurality of data samples corresponding to phase values. The system comprises a memory operable to store computing device executable instructions; and a computing device. The computing device is operable to generate a first falling edge region function for each data sample; generate a first rising edge function for each data sample; generate a first level function for each data sample; and generate a second falling edge function for each data sample. The second falling edge function equals the first falling edge function if the first falling edge function is greater than the first rising edge function and the first level function, and the second falling edge function equals zero.
摘要翻译：一种用于识别包括对应于相位值的多个数据样本的相移键控信号中的至少一个相变的系统。该系统包括可操作以存储计算设备可执行指令的存储器; 和计算设备。所述计算装置可操作以产生每个数据样本的第一下降沿区域函数; 为每个数据样本生成第一个上升沿函数; 为每个数据样本生成一级函数; 并为每个数据样本生成第二个下降沿函数。如果第一个下降沿功能大于第一个上升沿功能和第一个上升沿功能，而第二个下降沿功能等于零，则第二个下降沿功能等于第一个下降沿功能。

3. 发明申请

US20110010509A1 SYSTEM AND METHOD OF SORTING AND CALCULATING STATISTICS ON LARGE DATA SETS WITH A KNOWN VALUE RANGE 审中-公开
标题翻译：使用已知值范围对大数据集进行统计和计算统计的系统和方法
公开(公告)号：US20110010509A1
公开(公告)日：2011-01-13
申请号：US12498824
申请日：2009-07-07
申请人： Juan Esteban Flores , Michael O'Neal Fox , Jim D. Allen
发明人： Juan Esteban Flores , Michael O'Neal Fox , Jim D. Allen
IPC分类号： G06F12/00
CPC分类号： G06F7/24
摘要： A system for sorting data and calculating statistics on large data sets with a known value range includes a memory element and a processing element configured to execute steps of the methods. Methods for sorting data include establishing an array of counters such that each counter corresponds to a value in the data set, reading the numbers and incrementing the counter corresponding to the value of each number, and listing the values in sequential order wherein each value occurs in the list according to the count of the corresponding counter. Methods for calculating statistics utilize the count stored in each counter from the sorted data and the value that corresponds thereto.
摘要翻译：用于对具有已知值范围的大数据集进行数据排序和计算统计的系统包括存储元件和被配置为执行所述方法的步骤的处理元件。用于分类数据的方法包括建立一个计数器阵列，使得每个计数器对应于数据集中的值，读取数字并递增对应于每个数字的值的计数器，并且按顺序列出其中每个值出现在该列表根据相应计数器的计数。计算统计量的方法利用从排序数据和与其对应的值存储在每个计数器中的计数。

4. 发明申请

US20110010409A1 SYSTEM FOR CONJUGATE GRADIENT LINEAR ITERATIVE SOLVERS 失效
标题翻译：用于并联梯度线性迭代解算器的系统
公开(公告)号：US20110010409A1
公开(公告)日：2011-01-13
申请号：US12498800
申请日：2009-07-07
申请人： Matthew P. DeLaquil , Deepak Prasanna , Antone L. Kusmanoff
发明人： Matthew P. DeLaquil , Deepak Prasanna , Antone L. Kusmanoff
IPC分类号： G06F7/38 , G06F7/32
CPC分类号： G06F17/12
摘要： A system for a conjugate gradient iterative linear solver that calculates the solution to a matrix equation comprises a plurality of gamma processing elements, a plurality of direction vector processing elements, a plurality of x-vector processing elements, an alpha processing element, and a beta processing element. The gamma processing elements may receive an A-matrix and a direction vector, and may calculate a q-vector and a gamma scalar. The direction vector processing elements may receive a beta scalar and a residual vector, and may calculate the direction vector. The x-vector processing elements may receive an alpha scalar, the direction vector, and the q-vector, and may calculate an x-vector and the residual vector. The alpha processing element may receive the gamma scalar and a delta scalar, and may calculate the alpha scalar. The beta processing element may receive the residual vector, and may calculate the delta scalar and the beta scalar.
摘要翻译：用于计算矩阵方程的解的共轭梯度迭代线性求解器的系统包括多个伽马处理元件，多个方向向量处理元件，多个x向量处理元件，α处理元件和β 处理元件。伽马处理元件可以接收A矩阵和方向向量，并且可以计算q向量和伽马标量。方向向量处理元件可以接收β标量和残差向量，并且可以计算方向向量。 x向量处理元件可以接收α标量，方向向量和q向量，并且可以计算x向量和残差向量。阿尔法处理元件可以接收伽马标量和三角形标量，并且可以计算阿尔法标量。 β处理单元可以接收剩余向量，并且可以计算Δ标量和β标量。

5. 发明申请

US20100157854A1 SYSTEMS AND METHODS FOR SENDING DATA PACKETS BETWEEN MULTIPLE FPGA DEVICES 有权
标题翻译：用于发送多个FPGA器件之间的数据包的系统和方法
公开(公告)号：US20100157854A1
公开(公告)日：2010-06-24
申请号：US12340094
申请日：2008-12-19
申请人： Joshua D. Anderson , Scott M. Burkart , Matthew P. DeLaquil , Deepak Prasanna
发明人： Joshua D. Anderson , Scott M. Burkart , Matthew P. DeLaquil , Deepak Prasanna
IPC分类号： H04L12/56 , H04L29/02 , H04L5/14
CPC分类号： H04L45/00 , H04L49/10 , H04L49/25
摘要： Application Specific Integrated Circuit (“ASIC”) devices, such as Field Programmable Gate Arrays (“FPGAs”), may be interconnected using serial I/O connections, such as high speed multi-gigabit serial transceiver (“MGT”) connections. For example, serial I/O connections may be employed to interconnect a pair of ASICs to create a high bandwidth, low signal count connection, and in a manner so that any given pair of multiple ASIC devices on a single circuit card may communicate with each other through no more than one serial data communication link connection step. A reconfigurable hardware architecture (“RHA”) may be configured to include a communications infrastructure that uses a high-bandwidth packet router to establish standard communications protocols between multiple interfaces and/or multiple devices that may be present on a single circuit card. Dynamically-sized data packets, sized in accordance with the amount of data ready to be sent, are transferred between the devices and/or interfaces on the card.
摘要翻译：诸如现场可编程门阵列（“FPGA”）的专用集成电路（“ASIC”）器件可以使用诸如高速多吉比特串行收发器（“MGT”）连接的串行I / O连接进行互连。例如，可以采用串行I / O连接来互连一对ASIC以产生高带宽，低信号计数连接，并且以使得单个电路卡上的任何给定的一对多个ASIC器件可以与每个ASIC通信其他通过不超过一个串行数据通信链路连接步骤。可重新配置的硬件架构（“RHA”）可以被配置为包括使用高带宽分组路由器的通信基础设施，以在可能存在于单个电路卡上的多个接口和/或多个设备之间建立标准通信协议。根据准备发送的数据量大小的动态尺寸数据包在卡上的设备和/或接口之间传送。

6. 发明申请

US20090178043A1 SWITCH-BASED PARALLEL DISTRIBUTED CACHE ARCHITECTURE FOR MEMORY ACCESS ON RECONFIGURABLE COMPUTING PLATFORMS 失效
标题翻译：基于开关的并行分配高速缓存架构，用于可重构计算平台的存储器访问
公开(公告)号：US20090178043A1
公开(公告)日：2009-07-09
申请号：US11969003
申请日：2008-01-03
申请人： Deepak Prasanna , Matthew Pascal DeLaquil
发明人： Deepak Prasanna , Matthew Pascal DeLaquil
IPC分类号： G06F15/76 , G06F9/46 , G06F9/30
CPC分类号： G06F15/17375
摘要： A computing architecture comprises a plurality of processing elements to perform data processing calculations, a plurality of memory elements to store the data processing results, and a reconfigurable interconnect network to couple the processing elements to the memory elements. The reconfigurable interconnect network includes a switching element, a control element, a plurality of processor interface units, a plurality of memory interface units, and a plurality of application control units. In various embodiments, the processing elements and the interconnect network may be implemented in a field-programmable gate array.
摘要翻译：计算架构包括用于执行数据处理计算的多个处理元件，用于存储数据处理结果的多个存储器元件以及将处理元件耦合到存储器元件的可重配置互连网络。可重构互连网络包括开关元件，控制元件，多个处理器接口单元，多个存储器接口单元和多个应用控制单元。在各种实施例中，处理元件和互连网络可以在现场可编程门阵列中实现。

7. 发明申请

US20090175158A1 CODED VIRTUAL CHANNEL NETWORK 审中-公开
标题翻译：编码虚拟通道网络
公开(公告)号：US20090175158A1
公开(公告)日：2009-07-09
申请号：US11969008
申请日：2008-01-03
申请人： Kenneth Shamburger
发明人： Kenneth Shamburger
IPC分类号： H04J11/00
CPC分类号： H04J13/004 , H04B1/69
摘要： A data coding/decoding system for use with a plurality of users includes an encoder, a transmitter, a receiver, and a decoder. The encoder encodes data to be transmitted over a shared physical transmission medium using an orthogonal or convolution code associated with a receiving user. The transmitter transmits the encoded data. Generally, data may be transmitted simultaneously by a plurality of users. The receiver receives a stream of encoded data and forwards it to the decoder, which decodes it based on the orthogonal or convolution code of the receiving user.
摘要翻译：用于多个用户的数据编码/解码系统包括编码器，发射机，接收机和解码器。编码器使用与接收用户相关联的正交或卷积码对通过共享物理传输介质进行传输的数据进行编码。发射机发送编码数据。通常，数据可以由多个用户同时发送。接收器接收编码数据流并将其转发到解码器，解码器基于接收用户的正交或卷积码进行解码。

8. 发明申请

US20090171632A1 AUTOMATIC BNE SEED CALCULATOR 有权
标题翻译：自动BNE种子计算器
公开(公告)号：US20090171632A1
公开(公告)日：2009-07-02
申请号：US11967404
申请日：2007-12-31
申请人： Mark Allen Chivers , Sujit Ravindran
发明人： Mark Allen Chivers , Sujit Ravindran
IPC分类号： G06F17/11
CPC分类号： H03K19/177
摘要： An automatic background noise estimator (BNE) seed calculator for determining a starting point for a BNE circuit which tracks the noise floor received by a receiver. The BNE seed calculator may sample a plurality of data points from the receiver and calculate the magnitude of each point. The seed calculator may then determine the peak magnitude value, a plurality of mean values, and the variance of the sampled points. A plurality of lookup tables are used to compare the peak, mean, and variance values with simulated peak, mean, and variance values to estimate the noise floor level of the actual signal and use that to determine the optimum BNE seed value. Simulation software such as MATLAB is used to develop the lookup tables by simulating peak, mean, and variance values based on a plurality of signal-to-noise ratios (SNR).
摘要翻译：一种自动背景噪声估计器（BNE）种子计算器，用于确定跟踪由接收机接收的噪声基底的BNE电路的起始点。 BNE种子计算器可以从接收器采样多个数据点并计算每个点的幅度。种子计算器然后可以确定峰值幅度值，多个平均值和采样点的方差。使用多个查找表将峰值，平均值和方差值与模拟峰值，平均值和方差值进行比较，以估计实际信号的基底噪声水平，并使用它来确定最佳BNE种子值。仿真软件如MATLAB用于通过基于多个信噪比（SNR）模拟峰值，平均值和方差值来开发查找表。

9. 发明申请

US20090168932A1 MULTIPLE STREAM MULTIPLE RATE RESAMPLING COMPONENT 失效
标题翻译：多流程多速率重载组件
公开(公告)号：US20090168932A1
公开(公告)日：2009-07-02
申请号：US11966590
申请日：2007-12-28
申请人： Scott M. Fornero
发明人： Scott M. Fornero
IPC分类号： H04B1/10
CPC分类号： H04L25/05
摘要： A method of resampling a digital signal involves serially receiving a plurality of samples of said digital signal and applying a plurality of filter coefficients to a first subset of the plurality of samples to generate a first plurality of intermediate results and to a second subset of the samples to generate a second plurality of intermediate results. The first plurality of intermediate results is accumulated to generate a first resampled value, and the second plurality of intermediate results is accumulated to generate a second resampled value. Upon receipt, each signal sample may be used to update each of a plurality of running accumulation values and then discarded before receipt of a next signal sample. Furthermore, multiple signals may be resampled concurrently using a single filter path by multiplexing circuit components, such as memory blocks.
摘要翻译：重新采样数字信号的方法涉及串行地接收所述数字信号的多个样本，并将多个滤波器系数应用于多个采样的第一子集，以产生第一多个中间结果，并产生样本的第二子集以产生第二多个中间结果。累积第一多个中间结果以产生第一重采样值，并且累积第二多个中间结果以产生第二重采样值。在接收时，每个信号样本可用于更新多个运行累加值中的每一个，然后在接收下一个信号样本之前被丢弃。此外，可以通过复用诸如存储器块的电路组件，使用单个滤波器路径来同时重采样多个信号。

10. 发明授权

US08188919B2 Globally-convergent geo-location algorithm 有权
标题翻译：全球收敛地理位置算法
公开(公告)号：US08188919B2
公开(公告)日：2012-05-29
申请号：US12485409
申请日：2009-06-16
申请人： Michael T. Grabbe , Bryan Lloyd Westcott
发明人： Michael T. Grabbe , Bryan Lloyd Westcott
IPC分类号： G01S3/02 , G01S1/08 , G01S5/04
CPC分类号： G01S5/12 , G01S5/0205
摘要： A system and method for estimating a geolocation of a non-cooperative target using any reasonable target location estimate. Collectors may acquire actual signal measurements including a direction of arrival (DOA), a target range, a time difference of arrival (TDOA), a range rate, a range sum, and/or a frequency difference of arrival (FDOA). A processing device may receive the actual signal measurements and navigational data regarding the collectors. Then, the processing device may calculate an estimated target location as a solution to a nonlinear optimization problem where an objective function to be minimized is a weighted sum-of-squares of differences between the actual signal measurements and calculated values corresponding to signal measurements that theoretically should be produced for a particular target location. The algorithm used to solve this problem may be a globally convergent algorithm, such as a Levenberg-Marquardt algorithm.
摘要翻译：一种用于使用任何合理的目标位置估计来估计非合作目标的地理位置的系统和方法。收集器可以获取包括到达方向（DOA），目标范围，到达时间差（TDOA），范围速率，范围和和/或到达频率差（FDOA）的实际信号测量。处理设备可以接收关于收集器的实际信号测量和导航数据。然后，处理装置可以将估计的目标位置计算为非线性优化问题的解决方案，其中要最小化的目标函数是实际信号测量值与理论上对应于信号测量值的计算值之间的加权平方和应为特定目标地点生产。用于解决这个问题的算法可能是全局收敛算法，如Levenberg-Marquardt算法。

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