专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US10806030B2 Multi-layer circuit using metal layers as a moisture diffusion barrier for electrical performance 有权
公开(公告)号：US10806030B2
公开(公告)日：2020-10-13
申请号：US14597730
申请日：2015-01-15
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , Kyocera Circuit Solutions Inc.
发明人： Jean Audet , Edmund D. Blackshear , Masahiro Fukui , Charles L. Reynolds , Kenji Terada , Tomoyuki Yamada
IPC分类号： H05K1/03 , H01L23/498 , H01L23/00 , H01L51/44 , H01L51/10 , H01L51/52 , H01L23/14
摘要： A multi-layer substrate with metal layers as a moisture diffusion barrier for reduced electrical performance degradation over time after moisture exposure and methods of design and manufacture. The method includes determining a diffusion rate of an insulator material provided between an upper metal layer and an underlying signal line. The method further includes calculating a diffusion distance between a plane opening of the upper metal layer and the underlying signal line using the diffusion rate of the insulator material.

2. 发明申请

US20160227643A1 PRINTED WIRING BOARD AND METHOD OF PRODUCING THE SAME 审中-公开
标题翻译：印刷线路板及其制造方法
公开(公告)号：US20160227643A1
公开(公告)日：2016-08-04
申请号：US15010733
申请日：2016-01-29
申请人： National University Corporation Okayama University , KYOCERA Circuit Solutions, Inc.
发明人： Yoshitaka TOYOTA , Kengo IOKIBE , Yuki YAMASHITA , Masanori NAITO , Toshiyuki KANEKO , Kiyohiko KAIYA , Toshihisa UEHARA , Koichi KONDO
IPC分类号： H05K1/02 , H05K3/10
CPC分类号： H05K1/0236 , H05K2201/086 , H05K2201/09972
摘要： A printed wiring board includes a digital circuit, an analog circuit, and a power supply path that is disposed on an insulating layer between the digital circuit and the analog circuit. EBG unit cells are disposed on a boundary between the digital circuit and the analog circuit one dimensionally or two dimensionally and periodically, and an interdigital electrode is formed. A magnetic body film is formed over the printed wiring board, partially formed on the EBG unit cells, or formed avoiding the EBG unit cells.
摘要翻译：印刷电路板包括数字电路，模拟电路和设置在数字电路和模拟电路之间的绝缘层上的电源路径。 EBG单电池一维或二维和周期地设置在数字电路和模拟电路之间的边界上，形成叉指电极。在印刷电路板上形成一部分形成在EBG单元电池上的磁性体膜，或者形成为避免EBG单元电池。

3. 发明授权

US09295154B2 Wiring board 有权
标题翻译：接线板
公开(公告)号：US09295154B2
公开(公告)日：2016-03-22
申请号：US14317657
申请日：2014-06-27
申请人： KYOCERA SLC Technologies Corporation
发明人： Makoto Shiroshita
IPC分类号： H05K1/00 , H05K1/11 , H01L23/498 , H05K1/02
CPC分类号： H05K1/113 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L2224/131 , H01L2224/81193 , H05K1/025 , H05K2201/0175 , H05K2201/0317 , H05K2201/0338 , H05K2201/10674 , H01L2924/014
摘要： A wiring board according to the present invention is provided with an insulating board and a connection pad, wherein the connection pad includes a main conductor layer formed of a low resistance material, a thin film resistor layer formed of a high resistance material and having a low soldering wettability, and a covering layer having a high soldering wettability, the main conductor layer, the thin film resistor layer, and the covering layer being sequentially laminated at the surface of the insulating layer in such a manner as to be electrically connected in series to each other, and the thin film resistor layer covers a main surface and a side surface of the main conductor layer, and further, a side surface of the thin film resistor layer is exposed from the covering layer.
摘要翻译：根据本发明的布线板设置有绝缘板和连接焊盘，其中连接焊盘包括由低电阻材料形成的主导体层，由高电阻材料形成并具有低电阻材料的薄膜电阻层焊接润湿性，以及具有高焊接润湿性的覆盖层，主导体层，薄膜电阻层和覆盖层依次层叠在绝缘层的表面上，使其与并且薄膜电阻层覆盖主导体层的主表面和侧表面，此外，薄膜电阻层的侧表面从覆盖层露出。

4. 发明申请

US20150144390A1 WIRING BOARD AND METHOD FOR MOUNTING SEMICONDUCTOR ELEMENT ON WIRING BOARD 审中-公开
标题翻译：接线板和方法，用于安装接线板上的半导体元件
公开(公告)号：US20150144390A1
公开(公告)日：2015-05-28
申请号：US14552928
申请日：2014-11-25
申请人： KYOCERA CIRCUIT SOLUTIONS, INC.
发明人： Takayuki NEJIME
IPC分类号： H01L23/00 , H05K3/34 , H05K1/11
CPC分类号： H01L24/81 , H01L23/49811 , H01L23/49816 , H01L23/49838 , H01L24/16 , H01L24/17 , H01L2224/131 , H01L2224/16059 , H01L2224/16106 , H01L2224/16108 , H01L2224/17051 , H01L2224/17517 , H01L2224/8114 , H01L2224/81193 , H01L2224/81194 , H01L2224/81447 , H01L2224/81815 , H01L2924/351 , H01L2924/381 , H05K3/3436 , H05K2201/09781 , H05K2201/10674 , H05K2203/167 , Y02P70/613 , H01L2924/00014 , H01L2924/014
摘要： A wiring board of the present invention includes an insulating board having a mounting portion on an upper surface to mount a semiconductor element, and semiconductor element connection pads formed on the mounting portion, on which at least three first dummy pads arranged on a center portion of the mounting portion, and at least three second dummy pads arranged on a peripheral portion of the mounting portion, are formed, and a dummy solder bump is formed on each of the first dummy pad and the second dummy pad.
摘要翻译：本发明的布线基板包括：绝缘板，其上表面具有安装半导体元件的安装部分，以及形成在安装部分上的半导体元件连接焊盘，至少三个第一虚设焊盘布置在安装部分和布置在安装部分的周边部分上的至少三个第二虚拟焊盘，并且在第一虚拟焊盘和第二虚拟焊盘的每一个上形成虚拟焊料凸块。

5. 发明申请

US20150116967A1 WIRING BOARD AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：接线板及其制造方法
公开(公告)号：US20150116967A1
公开(公告)日：2015-04-30
申请号：US14518082
申请日：2014-10-20
申请人： KYOCERA Circuit Solutions, Inc.
发明人： Mitsuzo YOKOYAMA
IPC分类号： H05K1/11 , H05K3/40 , H05K1/18
CPC分类号： H05K3/3452 , H01L2224/16225 , H01L2924/15174 , H05K1/113 , H05K3/3436 , H05K3/4007 , H05K3/4644 , H05K2201/0191 , H05K2201/09972 , Y10T29/49124
摘要： Provided is a wiring board including: an insulating board having a mounting portion configured such that a semiconductor element is mounted on an upper surface thereof; a semiconductor element connection pad formed on the mounting portion; a conductor pillar formed on the semiconductor element connection pad; and a solder resist layer adhered on the insulating board. The solder resist layer has a first region with a thickness such that the semiconductor element connection pad and a lower end portion of the conductor pillar are embedded while an upper end portion of the conductor pillar protrudes, and a second region having a thickness larger than that of the first region and surrounding the first region.
摘要翻译：本发明提供一种布线基板，包括：绝缘基板，具有将半导体元件安装在其上表面上的安装部，形成在所述安装部上的半导体元件连接焊盘; 形成在所述半导体元件连接焊盘上的导体柱; 以及粘附在绝缘板上的阻焊层。阻焊层具有第一区域，其厚度使得半导体元件连接焊盘和导体柱的下端部分嵌入，同时导体柱的上端部突出，并且具有大于该导体柱的厚度的第二区域的第一个地区，并围绕第一个地区。

6. 发明授权

US10813215B2 Multi-layer circuit using metal layers as a moisture diffusion barrier for electrical performance 有权
公开(公告)号：US10813215B2
公开(公告)日：2020-10-20
申请号：US15068891
申请日：2016-03-14
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Jean Audet , Edmund D. Blackshear , Masahiro Fukui , Charles L. Reynolds , Kenji Terada , Tomoyuki Yamada
IPC分类号： H05K1/03 , H01L23/498 , H01L23/00 , H01L51/44 , H01L51/10 , H01L51/52 , H01L23/14
摘要： A multi-layer substrate with metal layers as a moisture diffusion barrier for reduced electrical performance degradation over time after moisture exposure and methods of design and manufacture. The method includes determining a diffusion rate of an insulator material provided between an upper metal layer and an underlying signal line. The method further includes calculating a diffusion distance between a plane opening of the upper metal layer and the underlying signal line using the diffusion rate of the insulator material.

7. 发明申请

US20160284636A1 WIRING BOARD 有权
标题翻译：接线板
公开(公告)号：US20160284636A1
公开(公告)日：2016-09-29
申请号：US15078061
申请日：2016-03-23
申请人： KYOCERA Circuit Solutions, Inc.
发明人： Hiroki MATSUWAKA , Hisayoshi WADA
IPC分类号： H01L23/498 , H05K1/11
CPC分类号： H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L2224/81
摘要： A wiring board includes an insulating substrate having a plurality of laminated insulating layers and a mounting part in one surface of the insulating substrate, a large number of semiconductor element connection pads, a large number of external connection pads, and a solid pattern extending from a region corresponding to the mounting part to the peripheral portion of the insulating substrate, and including a straight line shaped current path without intervention of gas vent openings.
摘要翻译：布线基板包括绝缘基板，绝缘基板具有多个叠层绝缘层和绝缘基板的一个表面中的安装部分，多个半导体元件连接焊盘，大量外部连接焊盘和从对应于绝缘基板的周边部分的安装部分的区域，并且包括直线形状的电流路径而不介入排气口。

8. 发明申请

US20160224811A1 WIRING BOARD AND METHOD FOR RECOGNIZING CODE INFORMATION THEREOF 有权
标题翻译：接线板和识别代码信息的方法
公开(公告)号：US20160224811A1
公开(公告)日：2016-08-04
申请号：US15011823
申请日：2016-02-01
申请人： KYOCERA Circuit Solutions, Inc.
发明人： Takafumi KAWASHIMA
IPC分类号： G06K7/06 , H05K1/11 , H05K1/18 , H05K1/02
CPC分类号： G06K7/065 , H01L2224/16225 , H05K1/0268 , H05K1/0298 , H05K1/111 , H05K1/113 , H05K1/181 , H05K2201/0959 , H05K2201/10674 , H05K2201/10734
摘要： A wiring board of the present invention includes an insulating board including a core insulating plate and an insulating layer laminated on at least one surface of the insulating plate. A plurality of code information reading pads formed of a conductor layer are disposed on a surface of the insulating layer formed uppermost. A common conductor is disposed oppositely to the code information reading pads by interposing therebetween the insulating layer formed uppermost. At least one of the code information reading pads and the common conductor are electrically connected to each other through a via conductor penetrating through the insulating layer formed uppermost.
摘要翻译：本发明的布线基板包括绝缘板，该绝缘板包括层叠在绝缘板的至少一个表面上的芯绝缘板和绝缘层。由导体层形成的多个代码信息读取焊盘设置在最上层形成的绝缘层的表面上。公共导体通过插入其间形成最上层的绝缘层而相对于码信息读取垫布置。代码信息读取焊盘和公共导体中的至少一个通过穿过最上层形成的绝缘层的通孔导体彼此电连接。

9. 发明申请

US20160219698A1 WIRING BOARD 审中-公开
标题翻译：接线板
公开(公告)号：US20160219698A1
公开(公告)日：2016-07-28
申请号：US15001362
申请日：2016-01-20
申请人： KYOCERA Circuit Solutions, Inc.
发明人： Masaharu YASUDA
IPC分类号： H05K1/02
CPC分类号： H05K1/0296 , H05K3/465
摘要： A wiring board of the present invention includes a build-up layer having a plurality of insulating layers laminated one upon another, a groove formed on a major surface of each of the insulating layers, and a wiring conductor formed in the groove. A surface of the wiring conductor lies lower than the major surface of each of the insulating layers which is formed in the wiring conductor in the groove.
摘要翻译：本发明的布线基板具有叠层而成的多个绝缘层的堆积层，形成在各绝缘层的主表面上的沟槽和形成在沟槽中的布线导体。布线导体的表面比形成在槽中的布线导体中的每个绝缘层的主表面低。

10. 发明申请

US20160219690A1 WIRING BOARD 审中-公开
标题翻译：接线板
公开(公告)号：US20160219690A1
公开(公告)日：2016-07-28
申请号：US15001383
申请日：2016-01-20
申请人： KYOCERA Circuit Solutions, Inc.
发明人： Yasuki ITOH
IPC分类号： H05K1/02
CPC分类号： H05K3/4644 , H01L2224/16225 , H01L2924/15174 , H05K1/0271 , H05K3/3436 , H05K2201/09736
摘要： A wiring board of the present invention includes a core substrate, insulating layers laminated on upper and lower surfaces of the core substrate, and a conductor layer deposited on the upper and lower surfaces of the core substrate and a surface of each of the insulating layers, in such a manner as to make a difference in area occupation ratio between the upper and lower surfaces of the core substrate. A thickness of a conductor that has a large area occupation ratio is smaller than a thickness of a conductor that has a small area occupation ratio between the conductor layers deposited on the upper and lower surfaces of the core substrate, and between the conductor layers deposited on the surface of each of the insulating layers laminated at an identical level on upper and lower surface sides with the core substrate as a center.
摘要翻译：本发明的布线基板包括芯基板，层叠在芯基板的上表面和下表面上的绝缘层，以及沉积在芯基板的上表面和下表面上的导体层和每个绝缘层的表面，以使得芯基板的上表面和下表面之间的面积占有率不同。具有大面积占有率的导体的厚度小于在芯基板的上表面和下表面之间以及沉积在芯基板上的导体层之间的导体层之间具有小面积占有率的导体的厚度每个绝缘层的表面以芯基板为中心在上表面和下表面侧以相同的水平层压。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式