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1. 发明授权

US08592831B2 Integrated circuit device 有权
标题翻译：集成电路器件
公开(公告)号：US08592831B2
公开(公告)日：2013-11-26
申请号：US11588490
申请日：2006-10-26
申请人： Avner Badehi
发明人： Avner Badehi
IPC分类号： H01L27/15
CPC分类号： H01L31/02327 , H01L21/56 , H01L21/82 , H01L23/3114 , H01L24/02 , H01L24/97 , H01L25/105 , H01L27/14618 , H01L27/14632 , H01L27/14687 , H01L27/15 , H01L31/02002 , H01L31/0203 , H01L31/02164 , H01L31/0232 , H01L31/125 , H01L31/186 , H01L33/0095 , H01L33/44 , H01L33/483 , H01L33/486 , H01L33/52 , H01L33/56 , H01L33/62 , H01L2221/68327 , H01L2224/0401 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01051 , H01L2924/01057 , H01L2924/01068 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/00
摘要： An integrally packaged optronic integrated circuit device including an integrated circuit die containing at least one of a radiation emitter and radiation receiver and having a transparent packaging layer overlying a surface of the die, the transparent packaging layer having an opaque coating adjacent to edges of the layer.
摘要翻译：一种整体封装的光电集成电路器件，包括集成电路管芯，其包含辐射发射器和辐射接收器中的至少一个，并且具有覆盖在管芯表面上的透明封装层，透明封装层具有邻近层的边缘的不透明涂层。

2. 发明申请

US20130070437A1 HYBRID INTERPOSER 审中-公开
标题翻译：混合插件
公开(公告)号：US20130070437A1
公开(公告)日：2013-03-21
申请号：US13236830
申请日：2011-09-20
申请人： Ilyas Mohammed , Terrence Caskey
发明人： Ilyas Mohammed , Terrence Caskey
IPC分类号： H05K7/06 , H05K1/11 , H05K1/00 , H01R43/00
CPC分类号： H01L23/145 , H01L23/13 , H01L23/49816 , H01L23/5384 , H01L23/5386 , H01L2224/16145 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/15153 , H01L2924/15192 , H01L2924/15311 , Y10T29/49117 , H01L2924/00
摘要： An interconnection component includes a low coefficient of thermal expansion (“CTE”) element having first and second surfaces defining a thickness, the element consisting essentially of a material having a first CTE of less than 10 parts per million per degree Celsius, the element having a plurality of contacts exposed at a first surface thereof. The component further includes a circuit panel having a dielectric element with first and second surfaces defining a thickness and a plurality of terminals exposed at the first surface, the circuit panel having a thickness greater than 50% of the thickness of the low-CTE element. A bonding layer including a dielectric material bonds the second surfaces of the circuit panel and the low CTE element to one another. Metalized vias are electrically connected with the terminals and the contacts, at least some vias extending through the bonding layer and through the thickness of the low-CTE element.
摘要翻译：互连部件包括具有限定厚度的第一和第二表面的低热膨胀系数（CTE）元件，所述元件基本上由具有小于每摄氏度百万分之10的第一CTE的材料组成，所述元件具有多个的触点在其第一表面露出。所述部件还包括具有介电元件的电路板，所述电介质元件具有限定厚度的第一表面和第二表面，以及在所述第一表面处暴露的多个端子，所述电路板的厚度大于所述低CTE元件的厚度的50％。包括电介质的接合层将电路板的第二表面和低CTE元件彼此结合。金属化通孔与端子和触点电连接，至少一些通孔延伸穿过结合层并通过低CTE元件的厚度。

3. 发明授权

US08735287B2 Semiconductor packaging process using through silicon vias 有权
标题翻译：半导体封装工艺使用硅通孔
公开(公告)号：US08735287B2
公开(公告)日：2014-05-27
申请号：US13488930
申请日：2012-06-05
申请人： Belgacem Haba , Giles Humpston , Moti Margalit
发明人： Belgacem Haba , Giles Humpston , Moti Margalit
IPC分类号： H01L21/441
CPC分类号： H01L21/76898 , H01L21/76805 , H01L23/3114 , H01L23/481 , H01L24/12 , H01L24/24 , H01L24/82 , H01L24/95 , H01L24/96 , H01L25/0657 , H01L25/50 , H01L2224/02372 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/13024 , H01L2224/13025 , H01L2224/2518 , H01L2224/82039 , H01L2225/06513 , H01L2225/06541 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01027 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/10329 , H01L2924/12042 , H01L2924/12044 , H01L2924/00
摘要： A microelectronic unit can include a semiconductor element having a front surface, a microelectronic semiconductor device adjacent to the front surface, contacts at the front surface and a rear surface remote from the front surface. The semiconductor element can have through holes extending from the rear surface through the semiconductor element and through the contacts. A dielectric layer can line the through holes. A conductive layer may overlie the dielectric layer within the through holes. The conductive layer can conductively interconnect the contacts with unit contacts.
摘要翻译：微电子单元可以包括具有前表面的半导体元件，与前表面相邻的微电子半导体器件，在前表面处的接触和远离前表面的后表面。半导体元件可以具有从后表面穿过半导体元件并通过触点延伸的通孔。电介质层可以对通孔进行排列。导电层可覆盖通孔内的电介质层。导电层可以将触点与单元触点导电互连。

4. 发明授权

US08604605B2 Microelectronic assembly with multi-layer support structure 有权
标题翻译：微电子组件具有多层支撑结构
公开(公告)号：US08604605B2
公开(公告)日：2013-12-10
申请号：US11650356
申请日：2007-01-05
申请人： Michael J. Nystrom , Giles Humpston
发明人： Michael J. Nystrom , Giles Humpston
IPC分类号： H01L23/12
CPC分类号： H01B13/00 , H01L23/10 , H01L2224/48091 , H01L2224/48463 , Y10T29/49126 , Y10T156/1062 , Y10T156/1092 , H01L2924/00014
摘要： A method of forming a microelectronic assembly includes positioning a support structure adjacent to an active region of a device but not extending onto the active region. The support structure has planar sections. Each planar section has a substantially uniform composition. The composition of at least one of the planar sections differs from the composition of at least one of the other planar sections. A lid is positioned in contact with the support structure and extends over the active region. The support structure is bonded to the device and to the lid.
摘要翻译：形成微电子组件的方法包括将支撑结构定位在与器件的有源区相邻但不延伸到有源区上。支撑结构具有平面部分。每个平面部分具有基本均匀的组成。至少一个平面部分的组成不同于其它平面部分中的至少一个的组成。盖子定位成与支撑结构接触并在有源区域上延伸。支撑结构结合到装置和盖子上。

5. 发明申请

US20130063918A1 LOW CTE INTERPOSER 有权
公开(公告)号：US20130063918A1
公开(公告)日：2013-03-14
申请号：US13232436
申请日：2011-09-14
申请人： Belgacem Haba , Kishor Desai
发明人： Belgacem Haba , Kishor Desai
IPC分类号： H05K7/00 , B32B38/08 , H05K1/00 , H05K1/11 , H05K1/16
CPC分类号： H01L23/49827 , H01L21/4857 , H01L21/486 , H01L23/498 , H01L23/49811 , H01L23/49833 , H01L24/17 , H01L24/73 , H01L2224/16225 , H01L2224/17104 , H01L2224/32225 , H01L2224/48227 , H01L2224/4911 , H01L2224/73204 , H01L2224/73265 , H01L2924/15311 , H01L2924/19107 , Y10T29/49128 , Y10T428/24521 , Y10T428/24802 , H01L2924/00 , H01L2924/00012
摘要： An interconnection component includes a first support portion has a plurality of first conductive vias extending therethrough substantially perpendicular to surfaces thereof such that each via has a first end adjacent a first surface and a second end adjacent a second surface. A second support portion has a plurality of second conductive vias extending therethrough substantially perpendicular to surfaces thereof such that each via has a first end adjacent the first surface and a second end adjacent the second surface. A redistribution layer is disposed between the second surfaces of the first and second support portions, electrically connecting at least some of the first vias with at least some of the second vias. The first and second support portions can have a coefficient of thermal expansion (“CTE”) of less than 12 parts per million per degree, Celsius (“ppm/° C.”).
摘要翻译：互连部件包括第一支撑部分，其具有大致垂直于其表面延伸的多个第一导电通孔，使得每个通孔具有邻近第一表面的第一端和邻近第二表面的第二端。第二支撑部分具有大致垂直于其表面延伸穿过的多个第二导电通路，使得每个通孔具有邻近第一表面的第一端和邻近第二表面的第二端。再分配层设置在第一和第二支撑部分的第二表面之间，将至少一些第一通孔与至少一些第二通孔电连接。第一和第二支撑部分的热膨胀系数（CTE）可以低于每百万摄氏度（ppm /℃）的百万分之十二。

6. 发明申请

US20130119520A1 CHIPS WITH HIGH FRACTURE TOUGHNESS THROUGH A METAL RING 有权
标题翻译：通过金属环具有高断裂韧性的CHIPS
公开(公告)号：US20130119520A1
公开(公告)日：2013-05-16
申请号：US13294226
申请日：2011-11-11
申请人： Ilyas Mohammed
发明人： Ilyas Mohammed
IPC分类号： H01L23/58 , H01L21/78
CPC分类号： H01L21/78 , H01L23/3107 , H01L23/562 , H01L23/585 , H01L29/0657 , H01L2924/0002 , H01L2924/00
摘要： A microelectronic element is disclosed that includes a semiconductor chip and a continuous monolithic metallic edge-reinforcement ring that covers each of the plurality of edge surfaces of the semiconductor chip and extending onto the front surface. The semiconductor chip may have front and rear opposed surfaces and a plurality of contacts at the front surface and edge surfaces extending between the front and rear surfaces. The semiconductor chip may also embody at least an active device or a passive device.
摘要翻译：公开了一种微电子元件，其包括覆盖半导体芯片的多个边缘表面中的每一个并延伸到前表面上的半导体芯片和连续的单片金属边缘加强环。半导体芯片可以具有前表面和后相对表面以及在前表面和在前表面和后表面之间延伸的边缘表面的多个触点。半导体芯片还可以具有至少一个有源器件或无源器件。

7. 发明申请

US20130099387A1 MICROELECTRONIC PACKAGE WITH STACKED MICROELECTRONIC UNITS AND METHOD FOR MANUFACTURE THEREOF 有权
标题翻译：具有堆叠微电子单元的微电子封装及其制造方法
公开(公告)号：US20130099387A1
公开(公告)日：2013-04-25
申请号：US13277330
申请日：2011-10-20
申请人： Terrence Caskey , Ilyas Mohammed
发明人： Terrence Caskey , Ilyas Mohammed
IPC分类号： H01L23/522 , H01L21/66
CPC分类号： H01L25/18 , H01L21/565 , H01L21/568 , H01L21/6835 , H01L21/76802 , H01L21/76877 , H01L23/13 , H01L23/3107 , H01L23/3114 , H01L23/3185 , H01L23/49816 , H01L23/5389 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/19 , H01L24/20 , H01L24/29 , H01L24/32 , H01L24/43 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/96 , H01L25/0657 , H01L25/105 , H01L25/117 , H01L25/50 , H01L2224/0401 , H01L2224/04042 , H01L2224/04105 , H01L2224/05124 , H01L2224/05147 , H01L2224/05548 , H01L2224/05554 , H01L2224/05571 , H01L2224/05624 , H01L2224/05647 , H01L2224/06155 , H01L2224/12105 , H01L2224/13023 , H01L2224/131 , H01L2224/13109 , H01L2224/13111 , H01L2224/13144 , H01L2224/1329 , H01L2224/133 , H01L2224/14131 , H01L2224/27334 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48108 , H01L2224/48145 , H01L2224/4824 , H01L2224/73207 , H01L2224/73215 , H01L2224/73217 , H01L2224/73265 , H01L2224/73267 , H01L2224/82031 , H01L2224/82039 , H01L2224/82047 , H01L2224/83005 , H01L2224/83192 , H01L2224/852 , H01L2224/92144 , H01L2224/92147 , H01L2225/06506 , H01L2225/0651 , H01L2225/06548 , H01L2225/06562 , H01L2225/06596 , H01L2225/1035 , H01L2225/1052 , H01L2225/1076 , H01L2225/1082 , H01L2924/00014 , H01L2924/0665 , H01L2924/12042 , H01L2924/1431 , H01L2924/1434 , H01L2924/15311 , H01L2924/18162 , H01L2924/186 , H01L2924/00012 , H01L2924/00 , H01L2924/014 , H01L2224/05552
摘要： A microelectronic package may include a first microelectronic unit including a semiconductor chip having first chip contacts, an encapsulant contacting an edge of the semiconductor chip, and first unit contacts exposed at a surface of the encapsulant and electrically connected with the first chip contacts. The package may include a second microelectronic unit including a semiconductor chip having second chip contacts at a surface thereof, and an encapsulant contacting an edge of the chip of the second unit and having a surface extending away from the edge. The surfaces of the chip and the encapsulant of the second unit define a face of the second unit. Package terminals at the face may be electrically connected with the first unit contacts through bond wires electrically connected with the first unit contacts, and the second chip contacts through metallized vias and traces formed in contact with the second chip contacts.
摘要翻译：微电子封装可以包括第一微电子单元，其包括具有第一芯片触点的半导体芯片，与半导体芯片的边缘接触的密封剂以及暴露在密封剂的表面处并与第一芯片触点电连接的第一单元触点。封装可以包括第二微电子单元，其包括在其表面具有第二芯片触点的半导体芯片，以及与第二单元的芯片的边缘接触并且具有远离边缘延伸的表面的密封剂。芯片的表面和第二单元的密封剂的表面限定了第二单元的面。表面处的封装端子可以通过与第一单元触点电连接的接合线与第一单元触点电连接，并且第二芯片通过金属化通孔和与第二芯片触点接触形成的迹线接触。

8. 发明申请

US20140055942A1 CO-SUPPORT MODULE AND MICROELECTRONIC ASSEMBLY 有权
标题翻译： CO支持模块和微电子组件
公开(公告)号：US20140055942A1
公开(公告)日：2014-02-27
申请号：US13840542
申请日：2013-03-15
申请人： INVENSAS CORP.
发明人： Richard Dewitt Crisp , Belgacem Haba , Wael Zohni
IPC分类号： B81B7/00
CPC分类号： B81B7/007 , H01L23/5384 , H01L25/0652 , H01L2224/12105 , H01L2224/20
摘要： A module may be configured for connection with a microelectronic assembly having terminals and a microelectronic element. The module may include a circuit panel bearing conductors configured to carry command and address information, co-support contacts coupled to the conductors, and module contacts coupled to the conductors. The co-support contacts may include first contacts having address and command information assignments arranged according to a first predetermined arrangement for connection with a first type of microelectronic assembly in which the microelectronic element is configured to sample command and address information coupled thereto through the first contacts at a first sampling rate, and according to a second predetermined arrangement for connection with a second type of the microelectronic assembly in which the microelectronic element is configured to sample the command and address information coupled thereto through a subset of the first contacts at a second sampling rate greater than the first sampling rate.
摘要翻译：模块可以被配置为与具有端子和微电子元件的微电子组件连接。模块可以包括电路板轴承导体，其被配置为承载命令和地址信息，共同支撑联接到导体的触点以及耦合到导体的模块触点。共同支持触点可以包括具有根据第一预定布置布置的地址和命令信息分配的第一触点，用于与第一类型的微电子组件连接，其中微电子元件被配置为对通过第一触点耦合到其上的命令和地址信息进行采样并且根据用于与第二类型的微电子组件连接的第二预定布置，其中微电子元件被配置为在第二采样中通过第一触点的子集对耦合到其的命令和地址信息进行采样速率大于第一采样率。

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