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1. 发明申请

US20170074819A1 SELF ALIGNED AND SCALABLE NANOGAP POST PROCESSING FOR DNA SEQUENCING 审中-公开
标题翻译：自定义和可扩展的NANOGAP后处理用于DNA测序
公开(公告)号：US20170074819A1
公开(公告)日：2017-03-16
申请号：US15122111
申请日：2014-03-28
申请人： Intel Corporation
发明人： Oguz H. ELIBOL
IPC分类号： G01N27/327 , G01N33/487 , C23C18/16 , C12Q1/68 , C23C14/34 , C23C16/455
CPC分类号： G01N27/3278 , C12Q1/6869 , C23C14/34 , C23C16/45525 , C23C18/1633 , G01N33/48721
摘要： An apparatus including a circuit substrate including a contact in a metal layer; and a transducer including a first electrode deposited on and coupled to a sidewall of the contact and a second electrode coupled to a conductor through which voltage can be applied, wherein the second electrode includes a profile aligned to the sidewall of the contact and separated from the first electrode by a gap. A method including forming a transducer adjacent a contact in a metal layer on a substrate, the transducer including a first electrode disposed on a sidewall of the contact and a second electrode coupled to a conductor through which voltage can be applied, wherein the second electrode includes a profile aligned to the sidewall of the contact and separated from the first electrode by a gap.
摘要翻译：一种包括在金属层中包括接触的电路基板的设备; 以及换能器，其包括沉积在所述接触件的侧壁上并且耦合到所述接触件的侧壁的第一电极和耦合到可以施加电压的导体的第二电极，其中所述第二电极包括与所述接触件的侧壁对准的轮廓并与所述接触件分离第一电极间隙。一种方法，包括在衬底上的金属层中形成与接触件相邻的换能器，所述换能器包括设置在所述触点的侧壁上的第一电极和耦合到可以施加电压的导体的第二电极，其中所述第二电极包括该轮廓与该接触件的侧壁对齐并且与该第一电极分开一间隙。

2. 发明申请

US20170125524A1 GE AND III-V CHANNEL SEMICONDUCTOR DEVICES HAVING MAXIMIZED COMPLIANCE AND FREE SURFACE RELAXATION 审中-公开
公开(公告)号：US20170125524A1
公开(公告)日：2017-05-04
申请号：US15405182
申请日：2017-01-12
申请人： Intel Corporation
发明人： RAVI PILLARISETTY , SANSAPTAK DASGUPTA , NITI GOEL , VAN H. LE , MARKO RADOSAVLJEVIC , GILBERT DEWEY , NILOY MUKHERJEE , MATTHEW V. METZ , WILLY RACHMADY , JACK T. KAVALIEROS , BENJAMIN CHU-KUNG , HAROLD W. KENNEL , STEPHEN M. CEA , ROBERT S. CHAU
IPC分类号： H01L29/10 , H01L29/165 , H01L29/20 , H01L21/762 , H01L29/78 , H01L29/06 , H01L29/66 , H01L29/16 , H01L29/267
CPC分类号： H01L29/785 , H01L21/76224 , H01L21/823431 , H01L21/823437 , H01L21/823462 , H01L27/0886 , H01L29/0653 , H01L29/1054 , H01L29/16 , H01L29/165 , H01L29/20 , H01L29/267 , H01L29/66545 , H01L29/66795 , H01L29/7842 , H01L29/7851
摘要： Ge and III-V channel semiconductor devices having maximized compliance and free surface relaxation and methods of fabricating such Ge and III-V channel semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a semiconductor substrate. The semiconductor fin has a central protruding or recessed segment spaced apart from a pair of protruding outer segments along a length of the semiconductor fin. A cladding layer region is disposed on the central protruding or recessed segment of the semiconductor fin. A gate stack is disposed on the cladding layer region. Source/drain regions are disposed in the pair of protruding outer segments of the semiconductor fin.

3. 发明申请

US20170012126A1 SELECTIVELY REGROWN TOP CONTACT FOR VERTICAL SEMICONDUCTOR DEVICES 审中-公开
标题翻译：选择垂直半导体器件的注册顶级联系人
公开(公告)号：US20170012126A1
公开(公告)日：2017-01-12
申请号：US15119674
申请日：2014-03-28
申请人： INTEL CORPORATION
发明人： Benjamin CHU-KUNG , Gilbert DEWEY , Van H. LE , Jack T. KAVALIEROS , Marko RADOSAVLJEVIC , Ravi PILLARISETTY , Han Wui THEN , Niloy MUKHERJEE , Sansaptak DASGUPTA
IPC分类号： H01L29/78 , H01L29/06 , H01L29/66 , H01L29/423 , H01L29/786
摘要： Vertical semiconductor devices having selectively regrown top contacts and method of fabricating vertical semiconductor devices having selectively regrown top contacts are described. For example, a semiconductor device includes a substrate having a surface. A first source/drain region is disposed on the surface of the substrate. A vertical channel region is disposed on the first source/drain region and has a first width parallel with the surface of the substrate. A second source/drain region is disposed on the vertical channel region and has a second width parallel with and substantially greater than the first width. A gate stack is disposed on and completely surrounds a portion of the vertical channel region.
摘要翻译：描述了具有选择性再生长顶端触点的垂直半导体器件和制造具有选择性再生长顶端触点的垂直半导体器件的方法。例如，半导体器件包括具有表面的衬底。第一源极/漏极区域设置在衬底的表面上。垂直沟道区域设置在第一源极/漏极区域上并且具有与衬底的表面平行的第一宽度。第二源极/漏极区域设置在垂直沟道区域上并且具有与第一宽度平行并且基本上大于第一宽度的第二宽度。栅堆叠设置在垂直沟道区的一部分上并完全环绕。

4. 发明申请

US20160172477A1 METHODS TO ACHIEVE HIGH MOBILITY IN CLADDED III-V CHANNEL MATERIALS 审中-公开
标题翻译：在III-V通道材料中实现高移动性的方法
公开(公告)号：US20160172477A1
公开(公告)日：2016-06-16
申请号：US14909090
申请日：2013-09-27
申请人： INTEL CORPORATION
发明人： Gilbert DEWEY , Matthew V. METZ , Niloy MUKHERJEE , Robert S. CHAU , Marko RADOSAVLJEVIC , Ravi PILLARISETTY , Benjamin CHU-KUNG
IPC分类号： H01L29/778 , H01L29/78 , H01L29/66 , H01L29/205
CPC分类号： H01L29/7786 , H01L29/1054 , H01L29/205 , H01L29/66462 , H01L29/66795 , H01L29/785 , H01L29/7851
摘要： An apparatus including a heterostructure disposed on a substrate and defining a channel region, the heterostructure including a first material having a first band gap less than a band gap of a material of the substrate and a second material having a second band gap that is greater than the first band gap; and a gate stack on the channel region, wherein the second material is disposed between the first material and the gate stack. A method including forming a first material having a first band gap on a substrate; forming a second material having a second band gap greater than the first band gap on the first material; and forming a gate stack on the second material.
摘要翻译：一种包括设置在衬底上并限定沟道区的异质结构的装置，所述异质结构包括具有小于所述衬底的材料的带隙的第一带隙的第一材料和具有大于所述衬底的材料的第二带隙的第二材料第一个带隙; 以及栅极堆叠，其中所述第二材料设置在所述第一材料和所述栅极叠层之间。一种方法，包括在基板上形成具有第一带隙的第一材料; 形成具有大于所述第一材料上的所述第一带隙的第二带隙的第二材料; 以及在所述第二材料上形成栅叠层。

5. 发明申请

US20190114283A1 ZERO COPY HOST INTERFACE IN A SCALABLE INPUT/OUTPUT (I/O) VIRTUALIZATION (S-IOV) ARCHITECTURE 审中-公开
公开(公告)号：US20190114283A1
公开(公告)日：2019-04-18
申请号：US16211924
申请日：2018-12-06
申请人： Intel Corporation
发明人： Manasi DEVAL , Nrupal JANI , Anjali SINGHAI , Parthasarathy SARANGAM , Mitu AGGARWAL , Neerav PARIKH , Kiran PATIL , Rajesh M. SANKARAN , Sanjay K. KUMAR , Utkarsh Y. KAKAIYA , Philip LANTZ , Kun TIAN
IPC分类号： G06F13/42 , G06F9/455
摘要： Examples may include a computing platform having a host driver to get a packet descriptor of a received packet stored in a receive queue and to modify the packet descriptor from a first format to a second format. The computing platform also includes a guest virtual machine including a guest driver coupled to the host driver, the guest driver to receive the modified packet descriptor and to read a packet buffer stored in the receive queue using the modified packet descriptor, the packet buffer corresponding to the packet descriptor.

6. 发明申请

US20170345476A1 AMORHPOUS SEED LAYER FOR IMPROVED STABILITY IN PERPENDICULAR STTM STACK 审中-公开
公开(公告)号：US20170345476A1
公开(公告)日：2017-11-30
申请号：US15503359
申请日：2014-09-26
申请人： Intel Corporation
发明人： Mark L. DOCZY , Kaan OGUZ , Brian S. DOYLE , Charles C. KUO , Robert S. CHAU , Satyarth SURI
IPC分类号： G11C11/16 , H01L43/10 , H01L27/22 , H01L43/12 , H01F10/32
CPC分类号： G11C11/161 , H01F10/3286 , H01L27/222 , H01L43/10 , H01L43/12
摘要： A material layer stack for a magnetic tunneling junction, the material layer stack including a fixed magnetic layer; a dielectric layer; a free magnetic layer; and an amorphous electrically-conductive seed layer, wherein the fixed magnetic layer is disposed between the dielectric layer and the seed layer. A non-volatile memory device including a material stack including an amorphous electrically-conductive seed layer; and a fixed magnetic layer juxtaposed and in contact with the seed layer. A method including forming an amorphous seed layer on a first electrode of a memory device; forming a material layer stack on the amorphous seed layer, the material stack including a dielectric layer disposed between a fixed magnetic layer and a free magnetic layer, wherein the fixed magnetic layer.

7. 发明申请

US20160204246A1 Ge and III-V Channel Semiconductor Devices having Maximized Compliance and Free Surface Relaxation 有权
标题翻译： Ge和III-V通道半导体器件具有最大限度的合规性和自由表面松弛
公开(公告)号：US20160204246A1
公开(公告)日：2016-07-14
申请号：US14914102
申请日：2013-09-27
申请人： INTEL CORPORATION
发明人： RAVI PILLARISETTY , SANSAPTAK DASGUPTA , NITI GOEL , VAN H. LE , MARKO RADOSAVLJEVIC , GILBERT DEWEY , NILOY MUKHERJEE , MATTHEW V. METZ , WILLY RACHMADY , JACK T. KAVALIEROS , BENJAMIN CHU-KUNG , HAROLD W. KENNEL , STEPHEN M. CEA , ROBERT S. CHAU
IPC分类号： H01L29/78 , H01L21/8234 , H01L27/088 , H01L29/165 , H01L29/267
CPC分类号： H01L29/785 , H01L21/76224 , H01L21/823431 , H01L21/823437 , H01L21/823462 , H01L27/0886 , H01L29/0653 , H01L29/1054 , H01L29/16 , H01L29/165 , H01L29/20 , H01L29/267 , H01L29/66545 , H01L29/66795 , H01L29/7842 , H01L29/7851
摘要： Ge and III-V channel semiconductor devices having maximized compliance and free surface relaxation and methods of fabricating such Ge and III-V channel semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a semiconductor substrate. The semiconductor fin has a central protruding or recessed segment spaced apart from a pair of protruding outer segments along a length of the semiconductor fin. A cladding layer region is disposed on the central protruding or recessed segment of the semiconductor fin. A gate stack is disposed on the cladding layer region. Source/drain regions are disposed in the pair of protruding outer segments of the semiconductor fin.
摘要翻译：描述了具有最大化顺应性和自由表面弛豫的Ge和III-V沟道半导体器件以及制造这种Ge和III-V沟道半导体器件的方法。例如，半导体器件包括设置在半导体衬底之上的半导体鳍。半导体鳍片具有沿着半导体鳍片的长度与一对突出外部部分间隔开的中心突出或凹陷部分。在半导体翅片的中央突出或凹陷部分上设置包覆层区域。栅极堆叠设置在包覆层区域上。源极/漏极区域设置在半导体鳍片的一对突出的外部段中。

8. 发明公开

US20240388439A1 System and Method for High Performance Secure Access to a Trusted Platform Module on a Hardware Virtualization Platform 审中-公开
公开(公告)号：US20240388439A1
公开(公告)日：2024-11-21
申请号：US18750817
申请日：2024-06-21
申请人： Intel Corporation
发明人： Ravi L. Sahita , Travis T. Schluessler
IPC分类号： H04L9/32 , G06F9/455 , G06F12/14 , G06F21/53 , G06F21/72
CPC分类号： H04L9/3234 , G06F9/45558 , G06F12/1433 , G06F12/1491 , G06F21/53 , G06F21/72 , G06F2009/45587 , G06F2221/034 , G06F2221/2149 , G06F2221/2153
摘要： A system and method for high performance secure access to a trusted platform module on a hardware virtualization platform. Example instructions partition resources of the host system to allocate (a) first resources of the host system for a first virtual machine and (b) second resources of the host system for a second virtual machine, wherein the resources of the host system include memory resources and a trusted platform module, the first virtual machine to run a first guest operating system and the second virtual machine to run a second guest operating system, wherein the first guest operating system is to run in a first isolated environment, the second guest operating system is to run in a second isolated environment; implement a virtual trusted platform module to support encryption for the first virtual machine; and protect the first resources and the second resources from unauthorized access.

9. 发明公开

US20240388067A1 INTEGRATED SEMICONDUCTOR OPTICAL AMPLIFIERS FOR SILICON PHOTONICS 审中-公开
公开(公告)号：US20240388067A1
公开(公告)日：2024-11-21
申请号：US18787825
申请日：2024-07-29
申请人： Intel Corporation
发明人： Jin Hong , Ranjeet Kumar , Meer Nazmus Sakib , Haisheng Rong , Kimchau Nguyen , Mengyuan Huang , Aliasghar Eftekhar , Christian Malouin , Siamak Amiralizadeh Asl , Saeed Fathololoumi , Ling Liao , Yuliya Akulova , Olufemi Dosunmu , Ansheng Liu
IPC分类号： H01S5/50 , G02B27/28 , H01S5/026 , H01S5/30
CPC分类号： H01S5/50 , G02B27/283 , G02B27/286 , H01S5/026 , H01S5/3013
摘要： Embodiments of the present disclosure are directed to a silicon photonics integrated apparatus that includes an input to receive an optical signal, a splitter optically coupled to the input to split the optical signal at a first path and a second path, a polarization beam splitter and rotator (PBSR) optically coupled with the first path or the second path, and a semiconductor optical amplifier (SOA) optically coupled with the first path or the second path and disposed between the splitter and the PBSR. Other embodiments may be described and/or claimed.

10. 发明公开

US20240387396A1 SURFACE FINISHES FOR CONTACTS AND FIDUCIAL MARKERS ON INTEGRATED CIRCUIT PACKAGE SUBSTRATES AND ASSOCIATED METHODS 审中-公开
公开(公告)号：US20240387396A1
公开(公告)日：2024-11-21
申请号：US18319164
申请日：2023-05-17
申请人： Intel Corporation
发明人： Jung Kyu Han , Gang Duan , Srinivas Pietambaram
IPC分类号： H01L23/544 , H01L21/48 , H01L23/00 , H01L23/498
CPC分类号： H01L23/544 , H01L21/4853 , H01L23/49811 , H01L24/11 , H01L24/13 , H01L24/16 , H01L2223/54426 , H01L2224/11462 , H01L2224/11464 , H01L2224/11849 , H01L2224/13021 , H01L2224/13111 , H01L2224/16227
摘要： Surface finishes for contacts and fiducial marks on integrated circuit package substrates and associated methods are disclosed. An example integrated circuit (IC) package substrate includes a first solder resist layer; a second solder resist layer opposite the first solder resist layer; and a fiducial marker including tin in an opening in the first solder resist layer.

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