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    • 5. 发明授权
    • Sensing pixel arrays and sensing devices using the same
    • 感测像素阵列和使用其的感测装置
    • US08456556B2
    • 2013-06-04
    • US13010470
    • 2011-01-20
    • Ping-Hung YinShuenn-Ren Hsiao
    • Ping-Hung YinShuenn-Ren Hsiao
    • H04N3/14
    • H04N5/3745
    • A sensing pixel array is provided and includes a plurality of pixels disposed in an array. Each pixel operates during an exposure period and a readout period and generates a readout signal. Each pixel includes a sensing unit and a sampling unit. The sensing unit senses light to generate a sensing signal during the exposure period. The sampling unit samples the sensing signal to generate a sensing output signal which serves as the readout signal during the readout period. During the exposure period, the sampling unit acts as a memory unit for storing an input signal and outputting an accessed output signal which serves as the readout signal.
    • 提供感测像素阵列并且包括以阵列布置的多个像素。 每个像素在曝光期间和读出期间进行动作,生成读出信号。 每个像素包括感测单元和采样单元。 感测单元在曝光期间感测光以产生感测信号。 采样单元对感测信号进行采样以产生在读出期间用作读出信号的感测输出信号。 在曝光期间,采样单元用作存储单元,用于存储输入信号并输出​​用作读出信号的存取的输出信号。
    • 8. 发明申请
    • Pipelined Recycling ADC with Shared Operational Amplifier Function
    • 具有共享运算放大器功能的流水回收ADC
    • US20120182170A1
    • 2012-07-19
    • US13008361
    • 2011-01-18
    • Ping-Hung YinShih-Feng Chen
    • Ping-Hung YinShih-Feng Chen
    • H03M1/34
    • H03M1/144H03M1/44
    • A pipelined recycling analog-to-digital converter (ADC), which converts a first analog input signal into a first digital output signal, including a first conversion stage and a second conversion stage is disclosed. The first conversion stage includes a first processing unit and a second processing unit. The first and the second processing units execute a number of conversion operations. For each conversion operation, an analog value and a digital code are generated by the first or the second processing unit. The first and the second processing units share an operational amplifier, and for each conversion operation. The second conversion stage includes a comparing unit which determines a specific analog value among the analog values generated by the first and the second processing units. When the specific analog value is not located within a predetermined range, the comparing unit generates a reset pulse to reset the operational amplifier.
    • 公开了一种流水线再循环模数转换器(ADC),其将第一模拟输入信号转换为包括第一转换级和第二转换级的第一数字输出信号。 第一转换级包括第一处理单元和第二处理单元。 第一和第二处理单元执行多个转换操作。 对于每个转换操作,由第一或第二处理单元生成模拟值和数字代码。 第一和第二处理单元共享运算放大器,并且用于每个转换操作。 第二转换级包括比较单元,其确定由第一处理单元和第二处理单元生成的模拟值之间的特定模拟值。 当特定模拟值不在预定范围内时,比较单元产生复位脉冲以复位运算放大器。
    • 9. 发明授权
    • Multi-phase black level calibration method and system
    • 多相黑电平校准方法及系统
    • US08218038B2
    • 2012-07-10
    • US12635711
    • 2009-12-11
    • Nguyen DongAmit MittraRay-Chi Chang
    • Nguyen DongAmit MittraRay-Chi Chang
    • H04N9/64
    • H04N5/361H04N5/3655H04N5/367
    • Multi-phase black level calibration (BLC) methods and systems are generally disclosed. According to one embodiment of the present invention, an image sensor comprises a pixel sensor array, a timing generator, and a front-end processing block. The front-end processing block also includes a first summing junction, a first BLC block, and a second BLC block. According to a first timing signal from the timing generator, the first BLC block is configured to iteratively generate a first calibration signal in a first phase based on a first set of adjusted black level signals associated with a first set of black pixels, a changing accumulator step, and a predetermined condition associated with a first target black level. According to a second timing signal from the timing generator, the second BLC block is configured to generate a second calibration signal for a second summing junction to apply to an image signal associated with one or more active pixels in the frame in a second phase.
    • 通常公开了多相黑电平校准(BLC)方法和系统。 根据本发明的一个实施例,图像传感器包括像素传感器阵列,定时发生器和前端处理块。 前端处理块还包括第一求和结,第一BLC块和第二BLC块。 根据来自定时发生器的第一定时信号,第一BLC块被配置为基于与第一组黑色像素相关联的第一组经调整的黑电平信号来迭代地产生第一相位中的第一校准信号,改变累加器 步骤和与第一目标黑色电平相关联的预定条件。 根据来自定时发生器的第二定时信号,第二BLC块被配置为产生用于第二加法结的第二校准信号,以应用于与第二阶段中的帧中的一个或多个有源像素相关联的图像信号。