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1. 发明申请

US20030070098A1 Processing machine, method of administering processing machine, program and system 审中-公开
标题翻译：加工机，管理加工机的方法，程序和系统
公开(公告)号：US20030070098A1
公开(公告)日：2003-04-10
申请号：US09970799
申请日：2001-10-05
申请人： Fujitsu Limited Kawasaki, Japan
发明人： Shinobu Tokita
IPC分类号： H04L009/32
CPC分类号： G06F21/575
摘要： A technology of providing a function of increasing a frequency of changing authentication information when starting up a machine irrespective of whether a user is aware of it, is disclosed. A processing machine having an operating state and a stopping state comprises a control unit (2, 8) making a request for inputting the predetermined authentication information at a transition from the stopping state to the operating state, and restraining this transition if the authentication information is not inputted, and an authentication setting unit (2, 8) confirming an intention for executing a process of changing the authentication information when executing a predetermined process.
摘要翻译：公开了一种在启动机器时提供改变认证信息的频率的功能的技术，而不管用户是否知道它。具有操作状态和停止状态的处理机器包括：控制单元（2,8），在从停止状态到运行状态的转变中进行输入预定认证信息的请求，并且如果认证信息为以及认证设定单元（2,8），其确认在执行预定处理时执行改变认证信息的处理的意图。

2. 发明申请

US20020051163A1 Printer apparatus and printer control method 审中-公开
标题翻译：打印机设备和打印机控制方法
公开(公告)号：US20020051163A1
公开(公告)日：2002-05-02
申请号：US09822231
申请日：2001-04-02
申请人： Fujitsu Limited, Kawasaki, Japan
发明人： Kiyoaki Fujikura
IPC分类号： G06F015/00
CPC分类号： G06K15/02 , G06K15/186
摘要： The printer prints in logical-page units, and is capable of printing a plurality of logical pages on the same physical page when printing a plurality of logical pages on one physical page. This printer apparatus comprises: a mechanical controller for receiving printing commands and controls the printing engine that prints on the printing medium; and a printer controller for receiving printing instructions from the host to print in logical-page units and creating printing data. The printer controller calculates the total physical length of the logical-pages after creating the printing data, then references the physical length of one page of the printing medium, and depending on the results, sends a printing command and the printing data to the mechanical control unit, and also according to the reference results, controls the detection operation of the mechanical controller for detecting when there is no printing medium.
摘要翻译：打印机以逻辑页面单位打印，并且当在一个物理页面上打印多个逻辑页面时能够在同一物理页面上打印多个逻辑页面。该打印机装置包括：机械控制器，用于接收打印命令并控制在打印介质上打印的打印引擎; 以及打印机控制器，用于从主机接收打印指令，以逻辑页面单元打印并创建打印数据。打印机控制器在创建打印数据之后计算逻辑页面的总物理长度，然后参考打印介质的一页的物理长度，根据结果，将打印命令和打印数据发送到机械控制单元，并且根据参考结果，控制机械控制器的检测操作，用于当没有打印介质时检测。

3. 发明申请

US20020040421A1 Cache controlling device and processor 失效
标题翻译：缓存控制设备和处理器
公开(公告)号：US20020040421A1
公开(公告)日：2002-04-04
申请号：US09817258
申请日：2001-03-27
申请人： FUJITSU LIMITED KAWASAKI, JAPAN
发明人： Toshiyuki Muta
IPC分类号： G06F012/08 , G06F012/00
CPC分类号： G06F9/383 , G06F12/0862
摘要： To perform a data replace control activated prior to the execution of a cache memory reference instruction so as to reduce the latency when a miss occurs to a cache memory. In a cache replace control of a load store unit, a load store unit controlling device comprises a first queue selection logical circuit 41, a second queue selection logical circuit 42 and a mediating unit 43, wherein the first queue selection logical circuit sequentially selects access instructions to access the cache memory which are stored in queues 31, wherein the second queue selection logical circuit selects unissued access instructions of the access instructions to access the cache memory which are stored in the queues prior to the selections by the first queue selection logical circuit, and wherein the mediating unit mediates between the access instructions selected by the first queue selection logical circuit and the pre-access instructions selected by the second queue selection logical circuit for accessing the cache memory.
摘要翻译：执行在执行高速缓存存储器参考指令之前激活的数据替换控制，以便在高速缓存存储器发生未命中时减少等待时间。在加载存储单元的高速缓存替换控制中，加载存储单元控制装置包括第一队列选择逻辑电路41，第二队列选择逻辑电路42和中介单元43，其中第一队列选择逻辑电路顺序地选择访问指令访问存储在队列31中的高速缓冲存储器，其中第二队列选择逻辑电路选择访问指令的未发布的访问指令以访问由第一队列选择逻辑电路进行选择之前存储在队列中的高速缓冲存储器，并且其中所述中介单元在由所述第一队列选择逻辑电路选择的访问指令与由所述第二队列选择逻辑电路选择的用于访问所述高速缓冲存储器的所述预访问指令之间进行中介。

4. 发明申请

US20010009279A1 Semiconductor device and manufacturing method of the same 有权
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US20010009279A1
公开(公告)日：2001-07-26
申请号：US09764114
申请日：2001-01-19
申请人： Fujitsu Limited, Kawasaki, Japan
发明人： Toshihide Kikkawa
IPC分类号： H01L029/06 , H01L031/0256 , H01L031/0328 , H01L031/0336 , H01L031/072
CPC分类号： H01L29/66318 , H01L21/28587 , H01L29/66462 , H01L29/7371 , H01L29/7782
摘要： A semiconductor device is a hetero-junction bipolar transistor structured by having a gallium arsenide film among laminated films, which has an indium gallium phosphide (InGaP) film which is connected to the gallium arsenide film and functions as an emitter, wherein the indium gallium phosphide film includes antimony (Sb). By including antimony, a carrier density can be deterred from decreasing near an interface between the gallium arsenide film and the indium gallium phosphide film and an emitter resistance can be reduced to a minimum.
摘要翻译：半导体器件是通过在层叠膜中具有砷化镓膜构成的异质结双极晶体管，其具有连接到砷化镓膜并用作发射极的铟镓磷（InGaP）膜，其中磷化铟镓薄膜包括锑（Sb）。通过包括锑，可以防止载流子密度在砷化镓膜和磷酸铟镓膜之间的界面附近降低，并且可以将发射极电阻降低到最小。

5. 发明授权

US11645574B2 Recording medium, reinforcement learning method, and reinforcement learning apparatus 有权
公开(公告)号：US11645574B2
公开(公告)日：2023-05-09
申请号：US16130482
申请日：2018-09-13
申请人： FUJITSU LIMITED , Okinawa Institute of Science and Technology School Corporation
发明人： Tomotake Sasaki , Eiji Uchibe , Kenji Doya , Hirokazu Anai , Hitoshi Yanami , Hidenao Iwane
IPC分类号： G06N3/00 , G06N20/00 , H04L41/0816 , G06N3/006 , H04L41/16 , H04L43/08
CPC分类号： G06N20/00 , G06N3/006 , H04L41/0816 , H04L41/16 , H04L43/08
摘要： A non-transitory, computer-readable recording medium stores therein a reinforcement learning program that uses a value function and causes a computer to execute a process comprising: estimating first coefficients of the value function represented in a quadratic form of inputs at times in the past than a present time and outputs at the present time and the times in the past, the first coefficients being estimated based on inputs at the times in the past, the outputs at the present time and the times in the past, and costs or rewards that corresponds to the inputs at the times in the past; and determining second coefficients that defines a control law, based on the value function that uses the estimated first coefficients and determining input values at times after estimation of the first coefficients.

6. 发明申请

US20020099820A1 Co-evaluation system 审中-公开
标题翻译：共同评价体系
公开(公告)号：US20020099820A1
公开(公告)日：2002-07-25
申请号：US10096929
申请日：2002-03-14
申请人： FUJITSU LIMITED., Kawasaki , JAPAN
发明人： Kenichi Kishi , Hiromasa Kimura , Takeshi Yabuta , Masaru Seita , Yujiro Yoshida , Kazumasa Moriya
IPC分类号： G06F015/173
CPC分类号： G06Q10/06 , H04L67/02 , H04L67/12 , H04L69/329
摘要： A server displays a co-evaluation request containing an evaluation scheme of a first evaluator on a homepage. A second evaluator browsing the co-evaluation request through a terminal device transmits a proportion of user's own assignment as an answer to the server. The server displays the proportion of assignment of the second evaluator on the homepage. Thereafter, each of the first and second evaluators respectively transmits evaluation results of the co-evaluation to the server. The server displays each evaluation result received on the homepage.
摘要翻译：服务器在主页上显示包含第一评估者的评估方案的共同评估请求。通过终端设备浏览共同评估请求的第二评估者将一部分用户自己的分配作为答案发送给服务器。服务器显示第二个评估者在主页上的分配比例。此后，第一和第二评估器中的每一个分别将共同评估的评估结果发送到服务器。服务器显示主页上收到的各种评估结果。

7. 发明申请

US20020033956A1 Image processing apparatus and image forming apparatus 失效
标题翻译：图像处理装置和图像形成装置
公开(公告)号：US20020033956A1
公开(公告)日：2002-03-21
申请号：US09779521
申请日：2001-02-09
申请人： Fujitsu Limited, Kawasaki, Japan
发明人： Mikio Koga
IPC分类号： G06K015/02 , G06T005/00 , G06K009/44 , G06T003/40 , H04N001/409 , G06K009/54 , G06K009/64 , G06T005/20
CPC分类号： G06T3/4023 , G06K15/128 , G06K2215/0057 , G06T5/20 , H04N1/4092
摘要： The image processing equipment produces an image of enhanced quality, having dots with higher density than in an original image, by collating an original image with templates. The present invention reduces required number of templates. Original image data in a collation window is either mirror-converted, flip-converted or flip-and-mirror-converted in an array converter (33) and selected on a time-division basis to collate with a single template pattern (34). The effect is equivalent to the collation with maximum four templates. Thus the number of template patterns to be prepared is greatly reduced. Also, by preparing additional patterns to be stored into an area that became vacant attributed to the reduction of patterns, more sophisticated image enhancement may be attained.
摘要翻译：图像处理设备通过将原始图像与模板整理来产生具有增强质量的图像，其具有比原始图像中更高密度的点。本发明减少了所需数量的模板。在排序规则窗口中的原始图像数据在阵列转换器（33）中进行镜像转换，翻转转换或翻转 - 镜像转换，并且以时分方式选择以与单个模板图案（34）进行比较。效果等同于最多四个模板的排序规则。因此，要准备的模板图案的数量大大减少。此外，通过准备要存储到由于图案减少引起的空白区域中的附加图案，可以获得更复杂的图像增强。

8. 发明申请

US20020019953A1 Clock supply control apparatus and method 失效
标题翻译：时钟供应控制装置及方法
公开(公告)号：US20020019953A1
公开(公告)日：2002-02-14
申请号：US09811572
申请日：2001-03-20
申请人： Fujitsu Limited, Kawasaki, Japan
发明人： Kenji Urita
IPC分类号： G06F001/12 , G06F005/06 , G06F001/04
CPC分类号： G06F1/3237 , G06F1/3203 , G06F13/4221 , Y02D10/128 , Y02D10/151
摘要： In a clock supply control apparatus and method of the invention, a clock signal is generated, and supply of the generated clock signal from a clock supply logic unit to a second device of a computer system is controlled in response to a clock control signal, the second device being operable with the clock signal supplied from the clock supply logic unit. The clock control signal is set at one of a supply inhibition level and a supply allowance level in response to a state of a clock run signal line, the resulting clock control signal being supplied to the clock supply logic unit. A first device of the computer system is operable with the generated clock signal and outputs an interrupt signal to an interrupt signal line regardless of whether the clock control signal is set at the clock supply inhibition level or the clock supply allowance level.
摘要翻译：在本发明的时钟供给控制装置和方法中，产生时钟信号，并且响应于时钟控制信号来控制从时钟供给逻辑单元向计算机系统的第二装置的产生的时钟信号的供给，第二设备可与从时钟供应逻辑单元提供的时钟信号一起工作。响应于时钟运行信号线的状态，时钟控制信号被设置在电源禁止电平和电源允许电平之一，所产生的时钟控制信号被提供给时钟供应逻辑单元。无论时钟控制信号是设置在时钟供给禁止电平还是时钟供给允许电平，计算机系统的第一装置可利用生成的时钟信号进行操作，并将中断信号输出到中断信号线。

9. 发明申请

US20020000926A1 Data reproduction device with simplified circuit structure 失效
标题翻译：具有简化电路结构的数据再现装置
公开(公告)号：US20020000926A1
公开(公告)日：2002-01-03
申请号：US09774100
申请日：2001-01-31
申请人： Fujitsu Limited, Kawasaki, Japan
发明人： Akira Nanba , Kenichi Hamada , Masakazu Taguchi
IPC分类号： H03M001/12
CPC分类号： G11B20/1403 , G11B20/10009
摘要： A data reproduction device includes an A/D converter quantizing a reproduction signal read from data recorded on a recording medium to produce quantized data based on a sampling clock; a reproduction signal determination unit determining rising and falling parts of the reproduction signal based on the quantized data, and outputting a gate signal corresponding to a result of determining the rising and falling parts; a leading-edge clock generation unit generating a leading-edge clock signal synchronous to a leading edge indicating a rising part of the reproduction signal; a trailingedge clock generation unit generating a trailingedge clock signal synchronous to a trailing edge indicating a falling part of the reproduction signal; a signal switch unit generating the sampling clock by selecting one of the leading-edge clock signal and the trailing-edge clock signal based on a value of the gate signal; and a signal supply unit supplying the sampling clock to the A/D converter, wherein the data reproduction device reproduces the data recorded on the recording medium by executing digital signal processing on the quantized data. The data reproduction device can share a single A/D converter and a single decoder used for reproducing recorded data based on clocks synchronous to a leading edge and a trailing edge of the recording pit. As a result, a circuit structure of the data reproduction device is simplified, thereby achieving decreases in a size of an implementation area and in the number of implemented parts in the circuit structure of the data reproduction device.
摘要翻译：数据再现装置包括：量化从记录在记录介质上的数据读取的再现信号的A / D转换器，以产生基于采样时钟的量化数据; 再现信号确定单元，基于量化数据确定再现信号的上升和下降部分，并输出与确定上升和下降部分的结果相对应的门信号; 前沿时钟产生单元，产生与指示再现信号的上升部分的前沿同步的前沿时钟信号; 后沿时钟生成单元，产生与指示再现信号的下降部分的后沿同步的后沿时钟信号; 信号切换单元，基于所述门信号的值，选择所述前沿时钟信号和所述后沿时钟信号之一，生成所述采样时钟; 以及将采样时钟提供给A / D转换器的信号供给单元，其中数据再现装置通过对量化数据执行数字信号处理来再现记录在记录介质上的数据。数据再现装置可以基于与记录凹坑的前沿和后沿同步的时钟来共享单个A / D转换器和用于再现记录数据的单个解码器。结果，简化了数据再现装置的电路结构，从而实现了数据再现装置的电路结构中的实现区域的大小和实现部分的数量的减少。

10. 发明申请

US20010014885A1 IC card and its controller, and a method for selection of IC card applications 审中-公开
标题翻译： IC卡及其控制器，以及选择IC卡应用的方法
公开(公告)号：US20010014885A1
公开(公告)日：2001-08-16
申请号：US09824010
申请日：2001-04-03
申请人： Fujitsu Limited, Kawasaki, Japan
发明人： Ryoichi Yanagi
IPC分类号： G06F017/60
CPC分类号： G07F7/1008 , G06Q20/341 , G06Q20/3572 , G06Q20/3574 , G06Q20/35765 , G06Q20/3578 , G06Q20/363 , G06Q20/367
摘要： Each application is provided with amounts and conditions for selection of applications, which are previously stored in an application selection table (22) of an IC card (100). Thereby, the amounts within predetermined ranges are corresponded to specific applications. The above IC card (100) performs automatic selection of applications corresponding to the amounts by an application selection section (23) based on amount information received from an external device.
摘要翻译：向每个应用程序提供用于选择预先存储在IC卡（100）的应用程序选择表（22）中的应用程序的数量和条件。因此，预定范围内的量对应于具体应用。上述IC卡（100）基于从外部设备接收的量信息，对应用程序选择部（23）的数量进行自动选择。

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