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1. 发明授权

US09054091B2 Hybrid packaged lead frame based multi-chip semiconductor device with multiple semiconductor chips and multiple interconnecting structures 有权
标题翻译：具有多个半导体芯片和多个互连结构的混合封装引线框架多芯片半导体器件
公开(公告)号：US09054091B2
公开(公告)日：2015-06-09
申请号：US13913770
申请日：2013-06-10
申请人： Hamza Yilmaz , Yan Xun Xue , Jun Lu , Peter Wilson , Yan Huo , Zhiqiang Niu , Ming-Chen Lu
发明人： Hamza Yilmaz , Yan Xun Xue , Jun Lu , Peter Wilson , Yan Huo , Zhiqiang Niu , Ming-Chen Lu
IPC分类号： H01L23/495 , H01L23/48 , H01L23/52 , H01L23/02 , H01L23/34 , H01L23/00 , H01L23/31 , H01L21/56
CPC分类号： H01L23/49568 , H01L21/4825 , H01L21/561 , H01L21/565 , H01L21/768 , H01L21/78 , H01L23/3107 , H01L23/3114 , H01L23/49503 , H01L23/4952 , H01L23/49524 , H01L23/49537 , H01L23/49541 , H01L23/49555 , H01L23/49562 , H01L23/49575 , H01L23/544 , H01L24/40 , H01L24/41 , H01L24/83 , H01L25/0655 , H01L25/50 , H01L2223/5446 , H01L2224/0401 , H01L2224/04026 , H01L2224/06181 , H01L2224/32245 , H01L2224/40095 , H01L2224/40137 , H01L2224/40139 , H01L2224/40245 , H01L2224/4103 , H01L2224/48091 , H01L2224/48465 , H01L2224/73104 , H01L2224/73221 , H01L2224/83801 , H01L2224/8385 , H01L2224/83851 , H01L2224/84801 , H01L2224/94 , H01L2924/00014 , H01L2924/13091 , H01L2924/181 , H01L2224/11 , H01L2224/03 , H01L2224/27 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： A hybrid packaging multi-chip semiconductor device comprises a lead frame unit, a first semiconductor chip, a second semiconductor chip, a first interconnecting structure and a second interconnecting structure, wherein the first semiconductor chip is attached on a first die paddle and the second semiconductor chip is flipped and attached on a third pin and a second die paddle, the first interconnecting structure electrically connecting a first electrode at a front surface of the first semiconductor chip and a third electrode at a back surface of the second semiconductor chip and a second electrode at the front surface of the first semiconductor chip is electrically connected by second interconnecting structure.
摘要翻译：一种混合封装多芯片半导体器件，包括引线框单元，第一半导体芯片，第二半导体芯片，第一互连结构和第二互连结构，其中第一半导体芯片附接在第一裸片上，第二半导体芯片被翻转并附接在第三引脚和第二管芯焊盘上，第一互连结构电连接第一半导体芯片的前表面处的第一电极和第二半导体芯片的后表面处的第三电极和第二电极在第一半导体芯片的前表面通过第二互连结构电连接。

2. 发明授权

US08933550B2 Structure of mixed semiconductor encapsulation structure with multiple chips and capacitors 有权
标题翻译：具有多个芯片和电容器的混合半导体封装结构的结构
公开(公告)号：US08933550B2
公开(公告)日：2015-01-13
申请号：US13442757
申请日：2012-04-09
申请人： Yan Xun Xue , Anup Bhalla , Jun Lu
发明人： Yan Xun Xue , Anup Bhalla , Jun Lu
IPC分类号： H01L23/22 , H01L29/40 , H01L23/495 , H01L23/00
CPC分类号： H01L23/49575 , H01L23/49562 , H01L23/49589 , H01L24/37 , H01L24/39 , H01L24/40 , H01L24/41 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/32145 , H01L2224/32245 , H01L2224/371 , H01L2224/40245 , H01L2224/45014 , H01L2224/451 , H01L2224/48091 , H01L2224/48137 , H01L2224/48247 , H01L2224/48257 , H01L2224/49111 , H01L2224/49171 , H01L2224/49175 , H01L2224/49177 , H01L2224/73219 , H01L2224/73221 , H01L2224/73265 , H01L2225/06562 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01027 , H01L2924/01033 , H01L2924/01082 , H01L2924/13091 , H01L2924/19041 , H01L2924/19104 , H01L2924/19105 , H01L2924/30107 , H01L2924/00 , H01L2924/00012 , H01L2224/84
摘要： A semiconductor package for power converter application comprises a low-side MOSFET chip and a high-side MOSFET chip stacking one over the other. The semiconductor package may further enclose a capacitor whereas the capacitor may be a discrete component or an integrated component on chip level with the low-side MOSFET. The semiconductor package may further comprise a PIC chip to provide a complete power converter on semiconductor chip assembly package level.
摘要翻译：用于功率转换器应用的半导体封装包括低边MOSFET芯片和高边MOSFET芯片。半导体封装可以进一步包围电容器，而电容器可以是分立元件或芯片级与低边MOSFET的集成元件。半导体封装还可以包括PIC芯片，以在半导体芯片组件封装级别上提供完整的功率转换器。

3. 发明授权

US08933545B2 Double-side exposed semiconductor device 有权
标题翻译：双面裸露半导体器件
公开(公告)号：US08933545B2
公开(公告)日：2015-01-13
申请号：US13865340
申请日：2013-04-18
申请人： Alpha and Omega Semiconductor(Cayman), Ltd.
发明人： Yuping Gong , Yan Xun Xue
IPC分类号： H01L23/495 , H01L23/31 , H01L23/367
CPC分类号： H01L23/49568 , H01L21/561 , H01L23/3107 , H01L23/3114 , H01L23/3157 , H01L23/3171 , H01L23/3675 , H01L23/49537 , H01L23/49555 , H01L23/49562 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L2224/0384 , H01L2224/0401 , H01L2224/05555 , H01L2224/1184 , H01L2224/1191 , H01L2224/13022 , H01L2224/131 , H01L2224/16245 , H01L2224/94 , H01L2924/181 , H01L2924/18161 , H01L2224/11 , H01L2924/014 , H01L2224/03 , H01L2924/00
摘要： A double-side exposed semiconductor device includes an electric conductive first lead frame attached on top of a thermal conductive but electrical nonconductive second lead frame and a semiconductor chip flipped and attached on top of the first lead frame. The gate and source electrodes on top of the flipped chip form electrical connections with gate and source pins of the first lead frame respectively. The flipped chip and center portions of the first and second lead frames are then encapsulated with a molding compound, such that the heat sink formed at the center of the second lead frame and the drain electrode at bottom of the semiconductor chip are exposed on two opposite sides of the semiconductor device. Thus, heat dissipation performance of the semiconductor device is effectively improved without increasing the size of the semiconductor device.
摘要翻译：双面露出的半导体器件包括安装在导热但不导电的第二引线框架的顶部的导电第一引线框架和翻转并附接在第一引线框架顶部上的半导体芯片。翻转芯片顶部的栅极和源极电极分别与第一引线框架的栅极和源极引脚形成电连接。第一和第二引线框架的翻转芯片和中心部分然后用模塑料封装，使得形成在第二引线框架的中心处的散热器和在半导体芯片的底部的漏电极暴露在两个相对的半导体器件的侧面。因此，在不增加半导体器件的尺寸的情况下，有效地提高了半导体器件的散热性能。

4. 发明授权

US08884600B2 Average inductor current control using variable reference voltage 有权
标题翻译：使用可变参考电压的平均电感电流控制
公开(公告)号：US08884600B2
公开(公告)日：2014-11-11
申请号：US13324121
申请日：2011-12-13
申请人： Yung-I Chang
发明人： Yung-I Chang
IPC分类号： H02M3/156 , G05F1/46 , H02M1/00
CPC分类号： G05F1/46 , H02M3/156 , H02M2001/0025
摘要： A variable reference voltage generation unit used in DC/DC converter includes a sample-hold valley inductor current unit electrically connected to a reference voltage generation unit. The sample-hold valley inductor current unit receives the valley inductor current and converts it into the valley voltage. The reference voltage generation unit receives and converts a current signal two times of a designated current into a voltage signal two times of a designated voltage. The voltage signal two times of reference voltage is then subtracted by the valley voltage to produce the new reference voltage to compare with an inductor voltage for controlling the switching of a switching transistor of the DC/DC convertor.
摘要翻译：在DC / DC转换器中使用的可变参考电压产生单元包括电连接到参考电压产生单元的采样保持谷值电感器电流单元。采样保持谷电感电流单元接收谷值电感电流并将其转换为谷值电压。参考电压产生单元将指定电流的两倍的电流信号接收并转换成指定电压的两倍的电压信号。然后将参考电压的两倍的电压信号除以谷值电压以产生新的参考电压，以与用于控制DC / DC转换器的开关晶体管的开关的电感器电压进行比较。

5. 发明授权

US08853003B2 Wafer level chip scale package with thick bottom metal exposed and preparation method thereof 有权
标题翻译：具有厚底金属露面的晶圆级芯片级封装及其制备方法
公开(公告)号：US08853003B2
公开(公告)日：2014-10-07
申请号：US13602144
申请日：2012-09-01
申请人： Yan Xun Xue
发明人： Yan Xun Xue
IPC分类号： H01L23/495 , H01L21/60 , H01L21/56 , H01L23/492 , H01L21/768 , H01L21/78 , H01L23/00 , H01L23/31
CPC分类号： H01L23/49827 , H01L21/561 , H01L21/76898 , H01L21/78 , H01L23/3114 , H01L23/492 , H01L23/49562 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/32 , H01L24/73 , H01L24/83 , H01L24/94 , H01L2224/02371 , H01L2224/0401 , H01L2224/04026 , H01L2224/05025 , H01L2224/0557 , H01L2224/05571 , H01L2224/06181 , H01L2224/11009 , H01L2224/13013 , H01L2224/13014 , H01L2224/13022 , H01L2224/131 , H01L2224/32245 , H01L2224/73104 , H01L2224/73153 , H01L2224/83005 , H01L2224/94 , H01L2924/00014 , H01L2924/1306 , H01L2924/13091 , H01L2924/014 , H01L2224/03 , H01L2224/11 , H01L2224/83 , H01L2924/00 , H01L2224/05552
摘要： A method for forming a wafer level chip scale (WLCS) package device with a thick bottom metal comprising the step of attaching a lead frame comprising a plurality of thick bottom metals onto a back metal layer of a semiconductor wafer including a plurality of semiconductor chips having a plurality of bonding pads formed on a front surface of each chip, each thick bottom metal is aligned to a central portion of each chip; a plurality of back side cutting grooves are formed along the scribe lines and filled with a package material, the package material are cut through thus forming a plurality of singulated WLCS package devices.
摘要翻译：一种形成具有厚底金属的晶片级芯片级（WLCS）封装器件的方法，包括将包括多个厚底金属的引线框架附接到半导体晶片的背金属层上的步骤，该半导体晶片包括多个半导体芯片，形成在每个芯片的前表面上的多个接合焊盘，每个厚的底部金属与每个芯片的中心部分对准; 沿着划线形成多个后侧切割槽并填充有封装材料，从而切割包装材料从而形成多个单个WLCS封装装置。

6. 发明授权

US08722466B2 Semiconductor packaging and fabrication method using connecting plate for internal connection 有权
标题翻译：使用连接板进行内部连接的半导体封装和制造方法
公开(公告)号：US08722466B2
公开(公告)日：2014-05-13
申请号：US12722528
申请日：2010-03-12
申请人： Jun Lu , Kai Liu , Yan Xun Xue
发明人： Jun Lu , Kai Liu , Yan Xun Xue
IPC分类号： H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H01L21/565 , H01L23/3107 , H01L23/49517 , H01L23/49524 , H01L23/49551 , H01L23/49562 , H01L23/49575 , H01L24/34 , H01L24/37 , H01L24/40 , H01L24/48 , H01L25/07 , H01L2224/32245 , H01L2224/37011 , H01L2224/37147 , H01L2224/4007 , H01L2224/40095 , H01L2224/40137 , H01L2224/40245 , H01L2224/48091 , H01L2224/48247 , H01L2224/73263 , H01L2224/73265 , H01L2224/8385 , H01L2224/84801 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01082 , H01L2924/014 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package with connecting plate for internal connection comprise: a plurality of chips each having a plurality of contact areas on a top surface; one or more connecting plates having a plurality of electrically isolated connecting plate portions each connecting a contact area of the semiconductor chips. The method of making the semiconductor package includes the steps of connecting one or more connecting plates to a plurality of semiconductor chips, applying a molding material to encapsulate the chips and the connecting plates, separating a plurality of connecting plate portions of the connecting plates by shallow cutting through or by grinding.
摘要翻译：具有用于内部连接的连接板的半导体封装包括：多个芯片，每个芯片在顶表面上具有多个接触区域; 一个或多个连接板具有多个电隔离的连接板部分，每个连接板部分连接半导体芯片的接触区域。制造半导体封装的方法包括将一个或多个连接板连接到多个半导体芯片的步骤，施加模制材料以封装芯片和连接板，将连接板的多个连接板部分分开浅切割或磨削。

7. 发明授权

US08669613B2 Semiconductor device die with integrated MOSFET and low forward voltage diode-connected enhancement mode JFET and method 有权
标题翻译：具有集成MOSFET和低正压二极管连接增强型JFET和方法的半导体器件裸片
公开(公告)号：US08669613B2
公开(公告)日：2014-03-11
申请号：US12893978
申请日：2010-09-29
申请人： Sik Lui , Wei Wang
发明人： Sik Lui , Wei Wang
IPC分类号： H01L29/66
CPC分类号： H01L27/0617 , H01L27/098
摘要： A semiconductor die with integrated MOSFET and diode-connected enhancement mode JFET is disclosed. The MOSFET-JFET die includes common semiconductor substrate region (CSSR) of type-1 conductivity. A MOSFET device and a diode-connected enhancement mode JFET (DCE-JFET) device are located upon CSSR. The DCE-JFET device has the CSSR as its DCE-JFET drain. At least two DCE-JFET gate regions of type-2 conductivity located upon the DCE-JFET drain and laterally separated from each other with a DCE-JFET gate spacing. At least a DCE-JFET source of type-1 conductivity located upon the CSSR and between the DCE-JFET gates. A top DCE-JFET electrode, located atop and in contact with the DCE-JFET gate regions and DCE-JFET source regions. When properly configured, the DCE-JFET simultaneously exhibits a forward voltage Vf substantially lower than that of a PN junction diode while the reverse leakage current can be made comparable to that of a PN junction diode.
摘要翻译：公开了具有集成MOSFET和二极管连接的增强型JFET的半导体管芯。 MOSFET-JFET管芯包括类型1导电性的公共半导体衬底区域（CSSR）。 MOSFET器件和二极管连接的增强型JFET（DCE-JFET）器件位于CSSR上。 DCE-JFET器件具有CSSR作为其DCE-JFET漏极。至少两个DCE-JFET栅极区域，位于DCE-JFET漏极上，并以DCE-JFET栅极间隔彼此横向分离。至少一个位于CSSR上和DCE-JFET门之间的类型1电导率的DCE-JFET源。位于顶部并与DCE-JFET栅极区域和DCE-JFET源极区域接触的顶部DCE-JFET电极。当正确配置时，DCE-JFET同时呈现基本上低于PN结二极管的正向电压Vf，而反向漏电流可以与PN结二极管的相反。

8. 发明授权

US08642397B1 Semiconductor wafer level package (WLP) and method of manufacture thereof 有权
标题翻译：半导体晶片级封装（WLP）及其制造方法
公开(公告)号：US08642397B1
公开(公告)日：2014-02-04
申请号：US13607775
申请日：2012-09-09
申请人： Yuping Gong , Yan Xun Xue , Ping Huang
发明人： Yuping Gong , Yan Xun Xue , Ping Huang
IPC分类号： H01L21/44
CPC分类号： H01L23/3114 , H01L23/3121 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/8592 , H01L2924/13091 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A wafer-level semiconductor package method comprising the step of providing a first wafer comprising a plurality of first dies each having a first, a second and a third electrodes formed on its front surface; attaching a second die having a fourth and a fifth electrodes formed on its front surface and a sixth electrode formed at its back surface onto each of the first die of the first wafer with the sixth electrode at the back surface of the second die attached and electrically connected to the second electrode at the front surface of the first die; and cutting the first wafer to singulate individual semiconductor packages.
摘要翻译：一种晶片级半导体封装方法，包括提供包括多个第一裸片的第一晶片的步骤，所述第一晶片具有形成在其前表面上的第一，第二和第三电极; 将具有在其前表面上形成的第四和第五电极的第二管芯和在其后表面上形成的第六电极连接到第一晶片的每个第一管芯上，第二电极的后表面上的第六电极被附接并电连接在第一模具的前表面处连接到第二电极; 并切割第一晶片以单独的半导体封装。

9. 发明授权

US08481368B2 Semiconductor package of a flipped MOSFET and its manufacturing method 有权
标题翻译：一种倒装MOSFET的半导体封装及其制造方法
公开(公告)号：US08481368B2
公开(公告)日：2013-07-09
申请号：US13092059
申请日：2011-04-21
申请人： Yan Xun Xue , Yueh-Se Ho , Hamza Yilmaz , Jun Lu
发明人： Yan Xun Xue , Yueh-Se Ho , Hamza Yilmaz , Jun Lu
IPC分类号： H01L21/44
CPC分类号： H01L24/49 , H01L23/3107 , H01L23/492 , H01L23/49503 , H01L23/49548 , H01L23/49562 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/33 , H01L24/37 , H01L24/40 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/91 , H01L2224/13099 , H01L2224/26175 , H01L2224/27013 , H01L2224/291 , H01L2224/29111 , H01L2224/29139 , H01L2224/29294 , H01L2224/29339 , H01L2224/32057 , H01L2224/32245 , H01L2224/32506 , H01L2224/371 , H01L2224/40245 , H01L2224/451 , H01L2224/48091 , H01L2224/48247 , H01L2224/49111 , H01L2224/73153 , H01L2224/73255 , H01L2224/73257 , H01L2224/73265 , H01L2224/83051 , H01L2224/83385 , H01L2224/838 , H01L2224/83801 , H01L2224/92247 , H01L2224/97 , H01L2924/00014 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/01322 , H01L2924/014 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2224/85 , H01L2224/81 , H01L2224/84 , H01L2224/83 , H01L2924/00 , H01L2224/05599 , H01L2924/00012
摘要： The invention relates to a semiconductor package of a flip chip and a method for making the semiconductor package. The semiconductor chip comprises a metal-oxide-semiconductor field effect transistor. On a die paddle including a first base, a second base and a third base, half-etching or punching is performed on the top surfaces of the first base and the second base to obtain plurality of grooves that divide the top surface of the first base into a plurality of areas comprising multiple first connecting areas, and divide the top surface of the second base into a plurality of areas comprising at least a second connecting area. The semiconductor chip is connected to the die paddle at the first connecting areas and the second connecting area.
摘要翻译：本发明涉及倒装芯片的半导体封装以及制造半导体封装的方法。半导体芯片包括金属氧化物半导体场效应晶体管。在包括第一基底，第二基底和第三基底的裸片上，在第一基底和第二基底的顶表面上进行半蚀刻或冲孔，以获得多个凹槽，该凹槽将第一基底进入包括多个第一连接区域的多个区域，并且将第二基座的顶表面分成包括至少第二连接区域的多个区域。半导体芯片在第一连接区域和第二连接区域处连接到管芯焊盘。

10. 发明授权

US08450152B2 Double-side exposed semiconductor device and its manufacturing method 有权
标题翻译：双面裸露半导体器件及其制造方法
公开(公告)号：US08450152B2
公开(公告)日：2013-05-28
申请号：US13193474
申请日：2011-07-28
申请人： Yuping Gong , Yan Xun Xue
发明人： Yuping Gong , Yan Xun Xue
IPC分类号： H01L21/00
CPC分类号： H01L23/49537 , H01L23/3107 , H01L23/4334 , H01L23/49562 , H01L23/49568 , H01L2224/16245 , H01L2224/32245
摘要： A double-side exposed semiconductor device includes an electric conductive first lead frame attached on top of a thermal conductive but electrical nonconductive second lead frame and a semiconductor chip flipped and attached on top of the first lead frame. The gate and source electrodes on top of the flipped chip form electrical connections with gate and source pins of the first lead frame respectively. The flipped chip and center portions of the first and second lead frames are then encapsulated with a molding compound, such that the heat sink formed at the center of the second lead frame and the drain electrode at bottom of the semiconductor chip are exposed on two opposite sides of the semiconductor device. Thus, heat dissipation performance of the semiconductor device is effectively improved without increasing the size of the semiconductor device.
摘要翻译：双面露出的半导体器件包括安装在导热但不导电的第二引线框架的顶部的导电第一引线框架和翻转并附接在第一引线框架顶部上的半导体芯片。翻转芯片顶部的栅极和源极电极分别与第一引线框架的栅极和源极引脚形成电连接。第一和第二引线框架的翻转芯片和中心部分然后用模塑料封装，使得形成在第二引线框架的中心处的散热器和在半导体芯片的底部的漏电极暴露在两个相对的半导体器件的侧面。因此，在不增加半导体器件的尺寸的情况下，有效地提高了半导体器件的散热性能。

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