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1. 发明授权

US4964142A Receiver synchronization in encoder/decoder 失效
标题翻译：编码器/解码器中的接收器同步
公开(公告)号：US4964142A
公开(公告)日：1990-10-16
申请号：US72955
申请日：1987-07-15
申请人： Kadiresan Annamalai
发明人： Kadiresan Annamalai
IPC分类号： H04L7/00 , H04J3/06
CPC分类号： H04J3/0632
摘要： Method and apparatus suited for use with a decoder receiving data serially from a network is disclosed providing synchronization throughout reception and decoding of packets of symbols. An appropriately-delayed read pointer initialization strobe used by an elastic buffer portion of the receiver provides the sequence of synchronization signals which avoids deletion of bits of packet preamble.

2. 发明授权

US4617478A Emitter coupled logic having enhanced speed characteristic for turn-on and turn-off 失效
标题翻译：发射极耦合逻辑具有增强的开启和关断速度特性
公开(公告)号：US4617478A
公开(公告)日：1986-10-14
申请号：US530176
申请日：1983-09-07
申请人： Hemmige D. Varadarajan
发明人： Hemmige D. Varadarajan
IPC分类号： H03K17/04 , H03K17/60 , H03K19/013 , H03K19/086 , H03K19/082 , H03K19/092
CPC分类号： H03K19/086 , H03K19/013
摘要： In accordance with the invention, the reference portion of a primitive current switch used in emitter coupled logic or current mode logic is modified by introducing a slow device as the reference element in order to enhance the speed of turn on and turn off of the input elements. In particular, the reference transistor of a conventional ECL inverter gate or conventional CML inverter gate is replaced with a slow transistor or slow diode in order to bypass the emitter dynamic resistance. The emitter time constant of the reference element Q.sub.R is thereby increased so that the voltage on the common current source node (node 3) does not change substantially when the base of the input elements change transiently. As a consequence, the collector output of the input element, such as transistor Q.sub.A is switched on or off significantly faster.
摘要翻译：根据本发明，在发射极耦合逻辑或电流模式逻辑中使用的原始电流开关的参考部分通过引入一个慢速装置作为参考元件来修改，以增强输入元件的导通和关断速度。特别地，传统的ECL逆变器栅极或常规CML反相器栅极的参考晶体管被替换为慢晶体管或慢二极管，以便绕过发射极动态电阻。因此，参考元件QR的发射极时间常数增加，使得当输入元件的基极瞬时变化时，公共电流源节点（节点3）上的电压基本上不变化。因此，诸如晶体管QA的输入元件的集电极输出明显更快地被接通或断开。

3. 发明公开

US20240321706A1 BACK END OF LINE OPTIMIZED TO FUNCTION IN A 3D STACK CONFIGURATION 审中-公开
公开(公告)号：US20240321706A1
公开(公告)日：2024-09-26
申请号：US18474151
申请日：2023-09-25
申请人： Advanced Micro Devices, Inc.
发明人： William George En , Samuel Naffziger , Regina T. Schmidt , Omar Zia , John Wuu
IPC分类号： H01L23/498 , H01L23/48 , H01L25/065
CPC分类号： H01L23/49827 , H01L23/481 , H01L23/49816 , H01L25/0657 , H01L2225/06541
摘要： A method for implementing shared metal connectivity between 3D stacked circuit dies can include providing a first circuit die having a first metal stack. The method can additionally include providing a second circuit die having a second metal stack, wherein at least one metal layer of the second metal stack is utilized by both the first circuit die and the second circuit die. The method can also include connecting the second metal stack to the first metal stack of the first circuit die. Various other methods, systems, and computer-readable media are also disclosed.

4. 发明公开

US20240320293A1 SMART THREADING IN MATRIX MULTIPLICATION 审中-公开
公开(公告)号：US20240320293A1
公开(公告)日：2024-09-26
申请号：US18125454
申请日：2023-03-23
申请人： ADVANCED MICRO DEVICES, INC.
发明人： Nallani Bhaskar , Mithun Mohan Kadavil Madana Mohanan
IPC分类号： G06F17/16 , G06F9/48
CPC分类号： G06F17/16 , G06F9/4881
摘要： Techniques are described in which an estimated optimal thread quantity for matrix multiplication is determined and implemented based on dimensions of the input matrices being multiplied and one or more kernel parameters that vary based on processor architecture. An efficient factorization of the estimated optimal thread quantity is based on a number of blocks along a first dimension of a first input matrix, and a number of blocks along a dimension n of a second input matrix B, with both numbers being based on the kernel parameters. In certain embodiments, a command processor of a parallel processor determines an estimated optimal thread quantity for performing a matrix multiplication command responsive to receiving the matrix multiplication command, and then schedules that estimated optimal thread quantity of kernel threads to execute the matrix multiplication command in parallel.

5. 发明公开

US20240319911A1 Alleviating Interconnect Traffic in a Disaggregated Memory System 审中-公开
公开(公告)号：US20240319911A1
公开(公告)日：2024-09-26
申请号：US18731089
申请日：2024-05-31
申请人： Advanced Micro Devices, Inc.
发明人： Vamsee Reddy Kommareddy , SeyedMohammad SeyedzadehDelcheh , Sergey Blagodurov
IPC分类号： G06F3/06 , G06F9/50 , G06F12/0802
CPC分类号： G06F3/0655 , G06F3/0602 , G06F3/065 , G06F3/0653 , G06F9/5027 , G06F12/0802 , G06F2212/60
摘要： One or both of read and write accesses to a fabric-attached memory module via a fabric interconnect are monitored. In one or more implementations, offloading of one or more tasks accessing the fabric-attached memory module to a processor of a routing system associated with the fabric-attached memory module is initiated based on the read and write accesses to the fabric-attached memory module. Additionally or alternatively, replicating memory of the fabric-attached memory module to a cache memory of a computing node in the disaggregated memory system executing one or more tasks of a host application is initiated based on the write accesses to the fabric-attached memory module.

6. 发明公开

US20240319712A1 Dynamic Range-Aware Conversion of Sensor Readings 审中-公开
公开(公告)号：US20240319712A1
公开(公告)日：2024-09-26
申请号：US18187848
申请日：2023-03-22
申请人： Advanced Micro Devices, Inc , ATI Technologies ULC
发明人： Jerry Anton Ahrens , Grant Evan Ley , Anil Harwani , Amitabh Mehra , Joshua Taylor Knight , William Robert Alverson , Adam Neil Calder Clark
IPC分类号： G05B19/4155 , G01K7/01
CPC分类号： G05B19/4155 , G01K7/01 , G05B2219/49216
摘要： Dynamic range aware conversion of sensor readings is described. A system includes one or more sensors to sense conditions of a component and output sensor readings and a system manager. The system manager is configured to convert the sensor readings into condition measurements by converting the sensor readings into the condition measurements using a first transformation while operating in a first conversion mode or converting the sensor readings into the condition measurements using a second transformation while operating in a second conversion mode. The system manager then adjusts operation of the component based on the condition measurements.

7. 发明授权

US12101135B2 Noise mitigation in single-ended links 有权
公开(公告)号：US12101135B2
公开(公告)日：2024-09-24
申请号：US18243243
申请日：2023-09-07
申请人： Advanced Micro Devices, Inc.
发明人： Ramon Mangaser , Karthik Gopalakrishnan , Andy Huei Chu , Pradeep Jayaraman
IPC分类号： H04B3/56 , G05F1/46 , H04B3/06
CPC分类号： H04B3/56 , G05F1/46 , H04B3/06
摘要： An integrated circuit includes a first terminal for receiving a data signal, a second terminal for receiving an external reference voltage, a receiver, and a reference voltage generation circuit. The receiver is powered by a power supply voltage with respect to ground and has a first input coupled to the first terminal, a second input for receiving a shared reference voltage, and an output for providing a data input signal. The reference voltage generation circuit is coupled to the second terminal and receives the power supply voltage. The reference voltage generation circuit is operable to form the shared reference voltage by mixing noise from the power supply voltage and noise from the second terminal.

8. 发明授权

US12100464B2 Repairable latch array 有权
公开(公告)号：US12100464B2
公开(公告)日：2024-09-24
申请号：US18302510
申请日：2023-04-18
申请人： ADVANCED MICRO DEVICES, INC.
发明人： Joel Thornton Irby , Grady L. Giles
IPC分类号： G11C7/10 , G11C29/12 , G11C29/44 , G11C29/46
CPC分类号： G11C29/4401 , G11C7/1012 , G11C7/1036 , G11C7/106 , G11C7/1087 , G11C29/1201 , G11C29/46 , G11C2029/1202
摘要： An integrated circuit includes a latch array including a plurality of latches logically configured in rows and columns, a plurality of repair latches operatively coupled to the plurality of latches and latch array built in self-test and repair logic (LABISTRL) coupled to the plurality of latches. In some implementations the LABISTRL configures latches in the array as one or more column serial test shift register, detects one or more defective latches of the plurality of latches based on applied test data, and selects at least one repair latch in response to detection of at least one defective latch.

9. 发明授权

US12099866B2 Address mapping-aware tasking mechanism 有权
公开(公告)号：US12099866B2
公开(公告)日：2024-09-24
申请号：US17135381
申请日：2020-12-28
申请人： Advanced Micro Devices, Inc.
发明人： Jonathan Alsop , Shaizeen Aga , Nuwan Jayasena
IPC分类号： G06F9/48 , G06F3/06 , G06F12/02 , G06F12/14
CPC分类号： G06F9/485 , G06F3/0604 , G06F3/0659 , G06F3/0673 , G06F12/0284 , G06F12/0292 , G06F12/145
摘要： An Address Mapping-Aware Tasking (AMAT) mechanism manages compute task data and issues compute tasks on behalf of threads that created the compute task data. The AMAT mechanism stores compute task data generated by host threads in a set of partitions, where each partition is designated for a particular memory module. The AMAT mechanism maintains address mapping data that maps address information to partitions. Threads push compute task data to the AMAT mechanism instead of generating and issuing their own compute tasks. The AMAT mechanism uses address information included in the compute task data and the address mapping data to determine partitions in which to store the compute task data. The AMAT mechanism then issues compute tasks to be executed near the corresponding memory modules (i.e., in PIM execution units or NUMA compute nodes) based upon the compute task data stored in the partitions.

10. 发明授权

US12099789B2 FPGA-based programmable data analysis and compression front end for GPU 有权
公开(公告)号：US12099789B2
公开(公告)日：2024-09-24
申请号：US17118442
申请日：2020-12-10
申请人： Advanced Micro Devices, Inc.
发明人： Kevin Y. Cheng , Sooraj Puthoor , Onur Kayiran
IPC分类号： G06F30/331 , G06F9/38 , G06F30/34
CPC分类号： G06F30/331 , G06F9/3877 , G06F30/34
摘要： Methods, devices, and systems for information communication. Information transmitted from a host to a graphics processing unit (GPU) is received by information analysis circuitry of a field-programmable gate array (FPGA). A pattern in the information is determined by the information analysis circuitry. A predicted information pattern is determined, by the information analysis circuitry, based on the information. An indication of the predicted information pattern is transmitted to the host. Responsive to a signal from the host based on the predicted information pattern, the FPGA is reprogrammed to implement decompression circuitry based on the predicted information pattern. In some implementations, the information includes a plurality of packets. In some implementations, the predicted information pattern includes a pattern in a plurality of packets. In some implementations, the predicted information pattern includes a zero data pattern.

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