专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US4964142A Receiver synchronization in encoder/decoder 失效
标题翻译：编码器/解码器中的接收器同步
公开(公告)号：US4964142A
公开(公告)日：1990-10-16
申请号：US72955
申请日：1987-07-15
申请人： Kadiresan Annamalai
发明人： Kadiresan Annamalai
IPC分类号： H04L7/00 , H04J3/06
CPC分类号： H04J3/0632
摘要： Method and apparatus suited for use with a decoder receiving data serially from a network is disclosed providing synchronization throughout reception and decoding of packets of symbols. An appropriately-delayed read pointer initialization strobe used by an elastic buffer portion of the receiver provides the sequence of synchronization signals which avoids deletion of bits of packet preamble.

2. 发明授权

US4617478A Emitter coupled logic having enhanced speed characteristic for turn-on and turn-off 失效
标题翻译：发射极耦合逻辑具有增强的开启和关断速度特性
公开(公告)号：US4617478A
公开(公告)日：1986-10-14
申请号：US530176
申请日：1983-09-07
申请人： Hemmige D. Varadarajan
发明人： Hemmige D. Varadarajan
IPC分类号： H03K17/04 , H03K17/60 , H03K19/013 , H03K19/086 , H03K19/082 , H03K19/092
CPC分类号： H03K19/086 , H03K19/013
摘要： In accordance with the invention, the reference portion of a primitive current switch used in emitter coupled logic or current mode logic is modified by introducing a slow device as the reference element in order to enhance the speed of turn on and turn off of the input elements. In particular, the reference transistor of a conventional ECL inverter gate or conventional CML inverter gate is replaced with a slow transistor or slow diode in order to bypass the emitter dynamic resistance. The emitter time constant of the reference element Q.sub.R is thereby increased so that the voltage on the common current source node (node 3) does not change substantially when the base of the input elements change transiently. As a consequence, the collector output of the input element, such as transistor Q.sub.A is switched on or off significantly faster.
摘要翻译：根据本发明，在发射极耦合逻辑或电流模式逻辑中使用的原始电流开关的参考部分通过引入一个慢速装置作为参考元件来修改，以增强输入元件的导通和关断速度。特别地，传统的ECL逆变器栅极或常规CML反相器栅极的参考晶体管被替换为慢晶体管或慢二极管，以便绕过发射极动态电阻。因此，参考元件QR的发射极时间常数增加，使得当输入元件的基极瞬时变化时，公共电流源节点（节点3）上的电压基本上不变化。因此，诸如晶体管QA的输入元件的集电极输出明显更快地被接通或断开。

3. 发明公开

US20240394346A1 SECURED ACCELERATED UNIT PROCESSING IN A DISTRIBUTED PROCCESING SYSTEM 审中-公开
公开(公告)号：US20240394346A1
公开(公告)日：2024-11-28
申请号：US18201675
申请日：2023-05-24
申请人： ADVANCED MICRO DEVICES, INC.
发明人： Ahmet Artu Yildirim
IPC分类号： G06F21/10 , G06F21/62
CPC分类号： G06F21/109 , G06F21/1015 , G06F21/6218
摘要： A distributed processing system includes one or more accelerated units (AUs) connected to a network. To control access to the AUs by one or more users over the network, the distributed processing system includes a control plane circuitry connected to the network. The control plane circuitry is configured to grant a user access to one or more AUs connected to the network based on user security data stored at the control plane circuitry. The security data stored at the control plane circuitry indicates which resources of one or more AUs connected to the network one or more users are authorized to access.

4. 发明授权

US12153958B2 VMID as a GPU task container for virtualization 有权
公开(公告)号：US12153958B2
公开(公告)日：2024-11-26
申请号：US18045128
申请日：2022-10-07
申请人： Advanced Micro Devices, Inc. , ATI Technologies ULC
发明人： Anirudh R. Acharya , Michael J. Mantor , Rex Eldon McCrary , Anthony Asaro , Jeffrey Gongxian Cheng , Mark Fowler
IPC分类号： G06F9/46 , G06F9/48 , G06F9/52 , G06F9/54 , G06F12/1009 , G06F12/14 , G06T1/20
CPC分类号： G06F9/4881 , G06F9/52 , G06F9/54 , G06F12/1009 , G06F12/145 , G06T1/20
摘要： Systems, apparatuses, and methods for abstracting tasks in virtual memory identifier (VMID) containers are disclosed. A processor coupled to a memory executes a plurality of concurrent tasks including a first task. Responsive to detecting one or more instructions of the first task which correspond to a first operation, the processor retrieves a first identifier (ID) which is used to uniquely identify the first task, wherein the first ID is transparent to the first task. Then, the processor maps the first ID to a second ID and/or a third ID. The processor completes the first operation by using the second ID and/or the third ID to identify the first task to at least a first data structure. In one implementation, the first operation is a memory access operation and the first data structure is a set of page tables. Also, in one implementation, the second ID identifies a first application of the first task and the third ID identifies a first operating system (OS) of the first task.

5. 发明授权

US12153957B2 Hierarchical work scheduling 有权
公开(公告)号：US12153957B2
公开(公告)日：2024-11-26
申请号：US17957714
申请日：2022-09-30
申请人： ADVANCED MICRO DEVICES, INC.
发明人： Matthaeus G. Chajdas , Christopher J. Brennan , Michael Mantor , Robert W. Martin , Nicolai Haehnle
IPC分类号： G06F9/48
CPC分类号： G06F9/4881
摘要： A method for hierarchical work scheduling includes consuming a work item at a first scheduling domain having a local scheduler circuit and one or more workgroup processing elements. Consuming the work item produces a set of new work items. Subsequently, the local scheduler circuit distributes at least one new work item of the set of new work items to be executed locally at the first scheduling domain. If the local scheduler circuit of the first scheduling domain determines that the set of new work items includes one or more work items that would overload the first scheduling domain with work if scheduled for local execution, those work items are distributed to the next higher-level scheduler circuit in a scheduling domain hierarchy for redistribution to one or more other scheduling domains.

6. 发明授权

US12153524B2 Apparatus, system, and method for throttling prefetchers to prevent training on irregular memory accesses 有权
公开(公告)号：US12153524B2
公开(公告)日：2024-11-26
申请号：US17957358
申请日：2022-09-30
申请人： Advanced Micro Devices, Inc.
发明人： John Kalamatianos , Marko Scrbak , Gabriel H. Loh , Akhil Arunkumar
IPC分类号： G06F12/0862
CPC分类号： G06F12/0862 , G06F2212/6028
摘要： A disclosed computing device includes at least one prefetcher and a processing device communicatively coupled to the prefetcher. The processing device is configured to detect a throttling instruction that indicates a start of a throttling region. The computing device is further configured to prevent the prefetcher from being trained on one or more memory instructions included in the throttling region in response to the throttling instruction. Various other apparatuses, systems, and methods are also disclosed.

7. 发明授权

US12141915B2 Load instruction for multi sample anti-aliasing 有权
公开(公告)号：US12141915B2
公开(公告)日：2024-11-12
申请号：US17028811
申请日：2020-09-22
申请人： Advanced Micro Devices, Inc.
发明人： Christopher J. Brennan , Fataneh F. Ghodrat , Tien E. Wei
IPC分类号： G06T1/20 , G06T15/00 , G06T15/50
CPC分类号： G06T15/503 , G06T1/20 , G06T15/005
摘要： Techniques for performing multi-sample anti-aliasing operations are provided. The techniques include detecting an instruction for a multi-sample anti-aliasing load operation; determining a sampling rate of source data for the load operation, data storage format of the source data, and loading mode indicating whether the load operation requests same or different color components, or depth data; and based on the determined sampling rate, data storage format, and loading mode, load data from a multi-sample source into a register.

8. 发明授权

US12141038B2 Error recovery for non-volatile memory modules 有权
公开(公告)号：US12141038B2
公开(公告)日：2024-11-12
申请号：US18084350
申请日：2022-12-19
申请人： Advanced Micro Devices, Inc.
发明人： Jing Wang , James R. Magro , Kedarnath Balakrishnan
IPC分类号： G06F11/14 , G06F3/06
CPC分类号： G06F11/1474 , G06F3/0619 , G06F3/0659 , G06F3/068 , G06F2201/82
摘要： A memory controller includes a command queue, a memory interface queue, at least one storage queue, and a replay control circuit. The command queue has a first input for receiving memory access commands. The memory interface queue receives commands selected from the command queue and couples to a heterogeneous memory channel which is coupled to at least one non-volatile storage class memory (SCM) module. The at least one storage queue stores memory access commands that are placed in the memory interface queue. The replay control circuit detects that an error has occurred requiring a recovery sequence, and in response to the error, initiates the recovery sequence. In the recovery sequence, the replay control circuit transmits selected memory access commands from the at least one storage queue by grouping non-volatile read commands together separately from all pending volatile reads, volatile writes, and non-volatile writes.

9. 发明授权

US12135653B2 Flexible dictionary sharing for compressed caches 有权
公开(公告)号：US12135653B2
公开(公告)日：2024-11-05
申请号：US18158212
申请日：2023-01-23
申请人： Advanced Micro Devices, Inc.
发明人： Alexander D. Breslow , John Kalamatianos
IPC分类号： G06F12/0895 , H03M7/30
CPC分类号： G06F12/0895 , H03M7/3088 , G06F2212/1044 , G06F2212/608
摘要： Systems, apparatuses, and methods for implementing flexible dictionary sharing techniques for caches are disclosed. A set-associative cache includes a dictionary for each data array set. When a cache line is to be allocated in the cache, a cache controller determines to which set a base index of the cache line address maps. Then, a selector unit determines which dictionary of a group of dictionaries stored by those sets neighboring this set would achieve the most compression for the cache line. This dictionary is then selected to compress the cache line. An offset is added to the base index of the cache line to generate a full index in order to map the cache line to the set corresponding to this chosen dictionary. The compressed cache line is stored in this set with the chosen dictionary, and the offset is stored in the corresponding tag array entry.

10. 发明授权

US12135625B2 Devices, systems, and methods for injecting fabricated errors into machine check architectures 有权
公开(公告)号：US12135625B2
公开(公告)日：2024-11-05
申请号：US18089135
申请日：2022-12-27
申请人： Advanced Micro Devices, Inc.
发明人： Vilas Sridharan , Hanbing Liu , Francisco L. Duran
IPC分类号： G06F11/26 , G06F11/07
CPC分类号： G06F11/261 , G06F11/0784 , G06F11/0787
摘要： An exemplary system includes and/or represents an agent and a machine check architecture. In one example, the machine check architecture includes and/or represents at least one circuit configured to report errors via at least one reporting register. In this example, the machine check architecture also includes and/or represents at least one error-injection register configured to cause the circuit to inject at least one fabricated error report into the reporting register in response to a write operation performed by the agent on at least one bit of the error-injection register. Various other devices, systems, and methods are also disclosed.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式