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1. 发明授权

US08443271B1 Systems and methods for dual process data decoding 有权
标题翻译：双程数据解码的系统和方法
公开(公告)号：US08443271B1
公开(公告)日：2013-05-14
申请号：US13284730
申请日：2011-10-28
申请人： Fan Zhang , Lei Chen , Zongwang Li , Shaohua Yang , Yang Han , Wu Chang
发明人： Fan Zhang , Lei Chen , Zongwang Li , Shaohua Yang , Yang Han , Wu Chang
IPC分类号： H03M13/03
CPC分类号： H03M13/1108 , G11B20/1833 , G11B2020/185 , H03M13/1111 , H03M13/1128 , H03M13/1142 , H03M13/1171 , H03M13/3707 , H03M13/451
摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, data processing systems are disclosed that include a data decoding system. The data decoding system includes a data decoder circuit and a simplified maximum likelihood value modification circuit. The data decoder circuit is operable to apply a data decode algorithm to a decoder input to yield a first decoded output and an indication of at least one point of failure of the first decoded output. The simplified maximum likelihood value modification circuit is operable to identify a symbol of the first decoded output associated with the point of failure, and to modify a subset of values associated with the identified symbol to yield a modified decoded output.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。例如，公开了包括数据解码系统的数据处理系统。数据解码系统包括数据解码器电路和简化的最大似然值修正电路。数据解码器电路可操作以将数据解码算法应用于解码器输入，以产生第一解码输出和第一解码输出的至少一个故障点的指示。简化的最大似然值修改电路可操作以识别与故障点相关联的第一解码输出的符号，并且修改与所识别的符号相关联的值的子集以产生经修改的解码输出。

2. 发明申请

US20130111289A1 SYSTEMS AND METHODS FOR DUAL PROCESS DATA DECODING 有权
标题翻译：双过程数据解码的系统和方法
公开(公告)号：US20130111289A1
公开(公告)日：2013-05-02
申请号：US13284730
申请日：2011-10-28
申请人： Fan Zhang , Lei Chen , Zongwang Li , Shaohua Yang , Yang Han , Wu Chang
发明人： Fan Zhang , Lei Chen , Zongwang Li , Shaohua Yang , Yang Han , Wu Chang
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/1108 , G11B20/1833 , G11B2020/185 , H03M13/1111 , H03M13/1128 , H03M13/1142 , H03M13/1171 , H03M13/3707 , H03M13/451
摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, data processing systems are disclosed that include a data decoding system. The data decoding system includes a data decoder circuit and a simplified maximum likelihood value modification circuit. The data decoder circuit is operable to apply a data decode algorithm to a decoder input to yield a first decoded output and an indication of at least one point of failure of the first decoded output. The simplified maximum likelihood value modification circuit is operable to identify a symbol of the first decoded output associated with the point of failure, and to modify a subset of values associated with the identified symbol to yield a modified decoded output.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。例如，公开了包括数据解码系统的数据处理系统。数据解码系统包括数据解码器电路和简化的最大似然值修正电路。数据解码器电路可操作以将数据解码算法应用于解码器输入，以产生第一解码输出和第一解码输出的至少一个故障点的指示。简化的最大似然值修改电路可操作以识别与故障点相关联的第一解码输出的符号，并且修改与所识别的符号相关联的值的子集以产生经修改的解码输出。

3. 发明申请

US20120262814A1 Systems and Methods for Data Processing 有权
标题翻译：数据处理系统和方法
公开(公告)号：US20120262814A1
公开(公告)日：2012-10-18
申请号：US13088146
申请日：2011-04-15
申请人： Zongwang Li , Fan Zhang , Wu Chang , Shaohua Yang
发明人： Zongwang Li , Fan Zhang , Wu Chang , Shaohua Yang
IPC分类号： G11B5/09 , G11B20/10
CPC分类号： G11B20/1833 , G11B20/10046 , G11B20/10296 , G11B2020/185 , G11B2220/2516 , H03M13/1111 , H03M13/1128 , H03M13/6343
摘要： Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes: a data detector circuit, a data decoder circuit, and a multi-path circuit. The data detector circuit is operable to apply a data detection algorithm to a data input and a decoder output to yield a detected output. The data decoder circuit is operable to apply a decoding algorithm to a decoder input to yield the decoder output and a status input. The multi-path circuit is operable to provide the decoder input based at least in part on the detected output and the status input.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。作为示例，公开了一种数据处理电路，其包括：数据检测器电路，数据解码器电路和多路径电路。数据检测器电路可操作以将数据检测算法应用于数据输入和解码器输出以产生检测的输出。数据解码器电路可操作以将解码算法应用于解码器输入以产生解码器输出和状态输入。多路径电路可操作以至少部分地基于检测到的输出和状态输入来提供解码器输入。

4. 发明授权

US08661324B2 Systems and methods for non-binary decoding biasing control 有权
标题翻译：用于非二进制解码偏移控制的系统和方法
公开(公告)号：US08661324B2
公开(公告)日：2014-02-25
申请号：US13227538
申请日：2011-09-08
申请人： Shaohua Yang , Weijun Tan , Zongwang Li , Fan Zhang , Yang Han , Chung-Li Wang , Wu Chang
发明人： Shaohua Yang , Weijun Tan , Zongwang Li , Fan Zhang , Yang Han , Chung-Li Wang , Wu Chang
IPC分类号： H03M13/00
CPC分类号： H03M13/1102 , G11B20/10379 , G11B27/36 , G11B2220/2516 , H03M13/1111 , H03M13/3983 , H03M13/45 , H03M13/6569
摘要： Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a data detector circuit, a biasing circuit, and a data decoder circuit. The data detector circuit is operable to apply a data detection algorithm to a series of symbols to yield a detected output, and the detected output includes a series of soft decision data corresponding to non-binary symbols. The biasing circuit is operable apply a bias to each of the series of soft decision data to yield a series of biased soft decision data. The data decoder circuit is operable to apply a data decoding algorithm to the series of biased soft decision data corresponding to the non-binary symbols.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。作为示例，公开了包括数据检测器电路，偏置电路和数据解码器电路的数据处理电路。数据检测器电路可操作以将数据检测算法应用于一系列符号以产生检测到的输出，并且所检测的输出包括与非二进制符号对应的一系列软判决数据。偏置电路可操作地将偏置应用于该系列软判决数据中的每一个，以产生一系列偏置的软判决数据。数据解码器电路可操作以将数据解码算法应用于对应于非二进制符号的一系列偏置软判决数据。

5. 发明授权

US08611033B2 Systems and methods for selective decoder input data processing 有权
标题翻译：选择性解码器输入数据处理的系统和方法
公开(公告)号：US08611033B2
公开(公告)日：2013-12-17
申请号：US13088146
申请日：2011-04-15
申请人： Zongwang Li , Fan Zhang , Wu Chang , Shaohua Yang
发明人： Zongwang Li , Fan Zhang , Wu Chang , Shaohua Yang
IPC分类号： G11B5/09 , H03M13/00
CPC分类号： G11B20/1833 , G11B20/10046 , G11B20/10296 , G11B2020/185 , G11B2220/2516 , H03M13/1111 , H03M13/1128 , H03M13/6343
摘要： Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes: a data detector circuit, a data decoder circuit, and a multi-path circuit. The data detector circuit is operable to apply a data detection algorithm to a data input and a decoder output to yield a detected output. The data decoder circuit is operable to apply a decoding algorithm to a decoder input to yield the decoder output and a status input. The multi-path circuit is operable to provide the decoder input based at least in part on the detected output and the status input.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。作为示例，公开了一种数据处理电路，其包括：数据检测器电路，数据解码器电路和多路径电路。数据检测器电路可操作以将数据检测算法应用于数据输入和解码器输出以产生检测的输出。数据解码器电路可操作以将解码算法应用于解码器输入以产生解码器输出和状态输入。多路径电路可操作以至少部分地基于检测到的输出和状态输入来提供解码器输入。

6. 发明申请

US20130067297A1 Systems and Methods for Non-Binary Decoding Biasing Control 有权
标题翻译：非二进制解码偏倚控制系统与方法
公开(公告)号：US20130067297A1
公开(公告)日：2013-03-14
申请号：US13227538
申请日：2011-09-08
申请人： Shaohua Yang , Weijun Tan , Zongwang Li , Fan Zhang , Yang Han , Chung-Li Wang , Wu Chang
发明人： Shaohua Yang , Weijun Tan , Zongwang Li , Fan Zhang , Yang Han , Chung-Li Wang , Wu Chang
IPC分类号： H03M13/45 , G06F11/10
CPC分类号： H03M13/1102 , G11B20/10379 , G11B27/36 , G11B2220/2516 , H03M13/1111 , H03M13/3983 , H03M13/45 , H03M13/6569
摘要： Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a data detector circuit, a biasing circuit, and a data decoder circuit. The data detector circuit is operable to apply a data detection algorithm to a series of symbols to yield a detected output, and the detected output includes a series of soft decision data corresponding to non-binary symbols. The biasing circuit is operable apply a bias to each of the series of soft decision data to yield a series of biased soft decision data. The data decoder circuit is operable to apply a data decoding algorithm to the series of biased soft decision data corresponding to the non-binary symbols.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。作为示例，公开了包括数据检测器电路，偏置电路和数据解码器电路的数据处理电路。数据检测器电路可操作以将数据检测算法应用于一系列符号以产生检测到的输出，并且所检测的输出包括与非二进制符号对应的一系列软判决数据。偏置电路可操作地将偏置应用于该系列软判决数据中的每一个，以产生一系列偏置的软判决数据。数据解码器电路可操作以将数据解码算法应用于对应于非二进制符号的一系列偏置软判决数据。

7. 发明授权

US08499231B2 Systems and methods for reduced format non-binary decoding 有权
标题翻译：缩减格式非二进制解码的系统和方法
公开(公告)号：US08499231B2
公开(公告)日：2013-07-30
申请号：US13167771
申请日：2011-06-24
申请人： Zongwang Li , Wu Chang , Chung-Li Wang , Changyou Xu , Shaohua Yang , Yang Han
发明人： Zongwang Li , Wu Chang , Chung-Li Wang , Changyou Xu , Shaohua Yang , Yang Han
IPC分类号： G06F11/00 , H03M13/00
CPC分类号： H03M13/1171 , H03M13/27 , H03M13/3723 , H03M13/612
摘要： Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a data detecting circuit having: a first vector translation circuit, a second vector translation circuit, and a data detector core circuit. The data detecting circuit is operable to receive an input data set and at least one input vector in a first format. The at least one input vector corresponds to a portion of the input data set. The first vector translation circuit is operable to translate the at least one vector to a second format. The data detector core circuit is operable to apply a data detection algorithm to the input data set and the at least one vector in the second format to yield a detected output. The second vector translation circuit operable to translate a derivative of the detected output to the first format to yield an output vector.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。作为示例，公开了一种数据处理电路，其包括具有第一向量转换电路，第二向量转换电路和数据检测器核心电路的数据检测电路。数据检测电路可操作以接收第一格式的输入数据集和至少一个输入向量。至少一个输入向量对应于输入数据集的一部分。第一向量翻译电路可操作以将至少一个向量转换为第二格式。数据检测器核心电路可操作以将数据检测算法应用于输入数据集和第二格式的至少一个向量以产生检测到的输出。第二向量转换电路可操作以将检测到的输出的导数转换为第一格式以产生输出向量。

8. 发明授权

US08560929B2 Systems and methods for non-binary decoding 有权
标题翻译：用于非二进制解码的系统和方法
公开(公告)号：US08560929B2
公开(公告)日：2013-10-15
申请号：US13167764
申请日：2011-06-24
申请人： Zongwang Li , Wu Chang , Chung-Li Wang , Changyou Xu , Shaohua Yang , Yang Han
发明人： Zongwang Li , Wu Chang , Chung-Li Wang , Changyou Xu , Shaohua Yang , Yang Han
IPC分类号： H03M13/00
CPC分类号： H04L1/0047 , H03M13/1171 , H03M13/134 , H03M13/255
摘要： Various embodiments of the present invention provide systems and methods for data processing. A data processing circuit is disclosed that includes: a data detector circuit, a first symbol constrained arrangement circuit, and a second symbol constrained arrangement circuit. The data detector circuit is operable to apply a data detection algorithm to a combination of a first input data set and a decoded data set to yield a detected output that includes a number of non-binary symbols. The first symbol constrained arrangement circuit is operable to receive the detected output and to re-arrange the detected output in accordance with a first arrangement algorithm to yield a re-arranged output. The bits for at least one non-binary symbol from the detected output are maintained together in the re-arranged output. The second symbol constrained arrangement circuit is operable to receive a second input data set and to re-arrange the second data input in accordance with a second arrangement algorithm to yield the decoded data set. The bits for at least one non-binary symbol from the second input data set are maintained together in the decoded data set output.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。公开了一种数据处理电路，其包括：数据检测器电路，第一符号约束布置电路和第二符号约束布置电路。数据检测器电路可操作以将数据检测算法应用于第一输入数据集合和解码数据集合的组合，以产生包括多个非二进制符号的检测输出。第一符号约束布置电路可操作以接收检测到的输出并根据第一布置算法重新布置检测的输出以产生重新排列的输出。来自检测到的输出的至少一个非二进制符号的位在重新布置的输出中保持在一起。第二符号约束布置电路可操作以接收第二输入数据集并且根据第二布置算法重排第二数据输入以产生解码数据集。用于来自第二输入数据集的至少一个非二进制符号的位在解码数据集输出中一起保持。

9. 发明申请

US20120331370A1 Systems and Methods for Non-Binary Decoding 有权
标题翻译：非二进制解码的系统和方法
公开(公告)号：US20120331370A1
公开(公告)日：2012-12-27
申请号：US13167764
申请日：2011-06-24
申请人： Zongwang Li , Wu Chang , Chung-Li Wang , Changyou Xu , Shaohua Yang , Yang Han
发明人： Zongwang Li , Wu Chang , Chung-Li Wang , Changyou Xu , Shaohua Yang , Yang Han
IPC分类号： G06F11/08
CPC分类号： H04L1/0047 , H03M13/1171 , H03M13/134 , H03M13/255
摘要： Various embodiments of the present invention provide systems and methods for data processing. A data processing circuit is disclosed that includes: a data detector circuit, a first symbol constrained arrangement circuit, and a second symbol constrained arrangement circuit. The data detector circuit is operable to apply a data detection algorithm to a combination of a first input data set and a decoded data set to yield a detected output that includes a number of non-binary symbols. The first symbol constrained arrangement circuit is operable to receive the detected output and to re-arrange the detected output in accordance with a first arrangement algorithm to yield a re-arranged output. The bits for at least one non-binary symbol from the detected output are maintained together in the re-arranged output. The second symbol constrained arrangement circuit is operable to receive a second input data set and to re-arrange the second data input in accordance with a second arrangement algorithm to yield the decoded data set. The bits for at least one non-binary symbol from the second input data set are maintained together in the decoded data set output.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。公开了一种数据处理电路，其包括：数据检测器电路，第一符号约束布置电路和第二符号约束布置电路。数据检测器电路可操作以将数据检测算法应用于第一输入数据集合和解码数据集合的组合，以产生包括多个非二进制符号的检测输出。第一符号约束布置电路可操作以接收检测到的输出并根据第一布置算法重新布置检测的输出以产生重新排列的输出。来自检测到的输出的至少一个非二进制符号的位在重新布置的输出中保持在一起。第二符号约束排列电路可操作以接收第二输入数据集并且根据第二布置算法重新布置第二数据输入以产生解码的数据集。用于来自第二输入数据集的至少一个非二进制符号的位在解码数据集输出中一起保持。

10. 发明申请

US20120331363A1 Systems and Methods for Reduced Format Non-Binary Decoding 有权
标题翻译：减少格式非二进制解码的系统和方法
公开(公告)号：US20120331363A1
公开(公告)日：2012-12-27
申请号：US13167771
申请日：2011-06-24
申请人： Zongwang Li , Wu Chang , Chung-Li Wang , Changyou Xu , Shaohua Yang , Yang Han
发明人： Zongwang Li , Wu Chang , Chung-Li Wang , Changyou Xu , Shaohua Yang , Yang Han
IPC分类号： G06F11/07
CPC分类号： H03M13/1171 , H03M13/27 , H03M13/3723 , H03M13/612
摘要： Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a data detecting circuit having: a first vector translation circuit, a second vector translation circuit, and a data detector core circuit. The data detecting circuit is operable to receive an input data set and at least one input vector in a first format. The at least one input vector corresponds to a portion of the input data set. The first vector translation circuit is operable to translate the at least one vector to a second format. The data detector core circuit is operable to apply a data detection algorithm to the input data set and the at least one vector in the second format to yield a detected output. The second vector translation circuit operable to translate a derivative of the detected output to the first format to yield an output vector.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。作为示例，公开了一种数据处理电路，其包括具有第一向量转换电路，第二向量转换电路和数据检测器核心电路的数据检测电路。数据检测电路可操作以接收第一格式的输入数据集和至少一个输入向量。至少一个输入向量对应于输入数据集的一部分。第一向量翻译电路可操作以将至少一个向量转换为第二格式。数据检测器核心电路可操作以将数据检测算法应用于输入数据集和第二格式的至少一个向量以产生检测到的输出。第二向量转换电路可操作以将检测到的输出的导数转换为第一格式以产生输出向量。

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