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    • 3. 发明授权
    • Time borrowing using dynamic clock shift for bus speed performance
    • 时间借用动态时钟转换为总线速度性能
    • US06803783B2
    • 2004-10-12
    • US10355559
    • 2003-01-31
    • Zhubiao ZhuKenneth KochJohn R. Spencer
    • Zhubiao ZhuKenneth KochJohn R. Spencer
    • H03K1706
    • G06F13/4291
    • An apparatus and method for increasing the performance of a common-clock data bus is provided by borrowing time from the common-clock domain timing. The time may be borrowed by dynamically delaying the common-clock before providing it to a receiving path. In a system comprising a plurality of logic devices electrically coupled to a data bus, time may be borrowed from the internal common-clock timing domain of one of the plurality of logic devices when receiving data through the data bus from an external logic device. To prevent race conditions, a logic device of the plurality of logic devices may be configured to switch off the time borrowing when receiving data from an internal driving path. To avoid glitches, the logic device may be configured to switch the time borrowing feature on and off only at select time intervals.
    • 通过从公共时钟域定时借用时间来提供用于增加公共时钟数据总线的性能的装置和方法。 可以在将公共时钟提供给接收路径之前动态地延迟公共时钟来借用该时间。 在包括电耦合到数据总线的多个逻辑器件的系统中,当从外部逻辑器件接收数据通过数据总线时,可以从多个逻辑器件之一的内部公共时钟定时域借入时间。 为了防止竞争条件,多个逻辑设备的逻辑设备可以被配置为在从内部驱动路径接收数据时关闭借用时间。 为了避免毛刺,逻辑器件可以被配置为仅在选定的时间间隔开启和关闭时间借用功能。
    • 9. 发明授权
    • Systems and methods for synchronizing an input signal
    • 用于同步输入信号的系统和方法
    • US08031819B2
    • 2011-10-04
    • US11588459
    • 2006-10-27
    • Zhubiao ZhuCarson Donahue HenrionDaniel Alan Berkram
    • Zhubiao ZhuCarson Donahue HenrionDaniel Alan Berkram
    • H04L7/00
    • H04L7/02H03K3/0375H03K3/35613H03K5/135
    • Systems and methods for synchronizing an input signal with a substantial mitigation of race conditions and a substantial increase in resolving time are provided. One embodiment includes a system comprising a first latching device configured to latch a first output signal from the input signal and a delay element configured to receive the first output signal and output a delay signal that is a delayed version of the first output signal. The system also includes a pass-gate element configured to receive the first output signal and to output a second output signal in response to a logic state of the delay signal. The second output signal has a delayed input edge without a delayed resolving edge. The system can be configured to force the first output signal to a stable logic state in response to the first output signal having a metastable state.
    • 提供了用于同步输入信号与大量减轻竞争条件并大大增加解析时间的系统和方法。 一个实施例包括一种系统,其包括被配置为从输入信号锁存第一输出信号的第一锁存装置和被配置为接收第一输出信号并输出​​作为第一输出信号的延迟版本的延迟信号的延迟元件。 该系统还包括一个通过栅极元件,配置成接收第一输出信号并响应于延迟信号的逻辑状态输出第二输出信号。 第二输出信号具有延迟的输入边沿,而没有延迟的分辨率边缘。 响应于具有亚稳态的第一输出信号,该系统可被配置为迫使第一输出信号处于稳定的逻辑状态。