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1. 发明申请

US20070281405A1 METHODS OF STRESSING TRANSISTOR CHANNEL WITH REPLACED GATE AND RELATED STRUCTURES 审中-公开
标题翻译：使用更换门和相关结构应力晶体管通道的方法
公开(公告)号：US20070281405A1
公开(公告)日：2007-12-06
申请号：US11421910
申请日：2006-06-02
申请人： Zhijiong Luo , Huilong Zhu , Yung Fu Chong , Brian L Tessier
发明人： Zhijiong Luo , Huilong Zhu , Yung Fu Chong , Brian L Tessier
IPC分类号： H01L21/338
CPC分类号： H01L29/6656 , H01L29/665 , H01L29/66545 , H01L29/78 , H01L29/7843 , H01L29/7845
摘要： Methods of stressing a channel of a transistor with a replaced gate and related structures are disclosed. A method may include providing an intrinsically stressed material over the transistor including a gate thereof; removing a portion of the intrinsically stressed material over the gate; removing at least a portion of the gate, allowing stress retained by the gate to be transferred to the channel; replacing (or refilling) the gate with a replacement gate; and removing the intrinsically stressed material. Removing and replacing the gate allows stress retained by the original gate to be transferred to the channel, with the replacement gate maintaining (memorizing) that situation. The methods do not damage the gate dielectric. A structure may include a transistor having a channel including a first stress that is one of a compressive and tensile and a gate including a second stress that is the other of compressive and tensile.
摘要翻译：公开了用替换的栅极和相关结构来施加晶体管的沟道的方法。一种方法可以包括在包括其栅极的晶体管上提供固有应力的材料; 在门上移除一部分本征应力材料; 去除栅极的至少一部分，允许由栅极保持的应力传递到通道; 用更换的门更换（或补充）门; 并去除本征应力材料。拆卸和更换门允许原始闸门保持的应力传递到通道，替换闸门保持（记住）这种情况。这些方法不会损坏栅极电介质。结构可以包括具有通道的晶体管，该沟道包括作为压缩和拉伸之一的第一应力和包括另一个压缩和拉伸的第二应力的栅极。

2. 发明申请

US20080286916A1 METHODS OF STRESSING TRANSISTOR CHANNEL WITH REPLACED GATE 审中-公开
标题翻译：用更换门压制晶体管通道的方法
公开(公告)号：US20080286916A1
公开(公告)日：2008-11-20
申请号：US12179042
申请日：2008-07-24
申请人： Zhijiong Luo , Huilong Zhu , Yung Fu Chong , Brian L. Tessier
发明人： Zhijiong Luo , Huilong Zhu , Yung Fu Chong , Brian L. Tessier
IPC分类号： H01L21/336
CPC分类号： H01L29/6656 , H01L29/665 , H01L29/66545 , H01L29/78 , H01L29/7843 , H01L29/7845
摘要： Methods of stressing a channel of a transistor with a replaced gate and related structures are disclosed. A method may include providing an intrinsically stressed material over the transistor including a gate thereof; removing a portion of the intrinsically stressed material over the gate; removing at least a portion of the gate, allowing stress retained by the gate to be transferred to the channel; replacing (or refilling) the gate with a replacement gate; and removing the intrinsically stressed material. Removing and replacing the gate allows stress retained by the original gate to be transferred to the channel, with the replacement gate maintaining (memorizing) that situation. The methods do not damage the gate dielectric.
摘要翻译：公开了用替换的栅极和相关结构来施加晶体管的沟道的方法。一种方法可以包括在包括其栅极的晶体管上提供固有应力的材料; 在门上移除一部分本征应力材料; 去除栅极的至少一部分，允许由栅极保持的应力传递到通道; 用更换的门更换（或补充）门; 并去除本征应力材料。拆卸和更换门允许原始闸门保持的应力传递到通道，替换闸门保持（记住）这种情况。这些方法不会损坏栅极电介质。

3. 发明授权

US07566609B2 Method of manufacturing a semiconductor structure 失效
标题翻译：制造半导体结构的方法
公开(公告)号：US07566609B2
公开(公告)日：2009-07-28
申请号：US11164568
申请日：2005-11-29
申请人： Zhijiong Luo , Yung Fu Chong , Huilong Zhu
发明人： Zhijiong Luo , Yung Fu Chong , Huilong Zhu
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814 , H01L21/823807 , H01L21/823835 , H01L21/823842 , H01L21/823864 , H01L29/4975 , H01L29/66545 , H01L29/6656 , H01L29/66636 , H01L29/7848
摘要： There is provided a method of manufacturing a field effect transistor (FET) that includes the steps of forming a gate structure on a semiconductor substrate, and forming a recess in the substrate and embedding a second semiconductor material in the recess. The gate structure includes a gate dielectric layer, conductive layers and an insulating layer. Forming said gate structure includes a step of recessing the conductive layer in the gate structure, and the steps of recessing the conductive layer and forming the recess in the substrate are performed in a single step. There is also provided a FET device.
摘要翻译：提供了一种制造场效应晶体管（FET）的方法，该方法包括以下步骤：在半导体衬底上形成栅极结构，并在衬底中形成凹陷并将第二半导体材料嵌入凹槽中。栅极结构包括栅极电介质层，导电层和绝缘层。形成所述栅极结构包括使栅极结构中的导电层凹陷的步骤，并且在单个步骤中执行使导电层凹陷并且在衬底中形成凹部的步骤。还提供了一种FET器件。

4. 发明申请

US20080283934A1 SUBSTANTIALLY L-SHAPED SILICIDE FOR CONTACT AND RELATED METHOD 有权
标题翻译：用于接触的大量L型硅胶和相关方法
公开(公告)号：US20080283934A1
公开(公告)日：2008-11-20
申请号：US12182212
申请日：2008-07-30
申请人： Zhijiong Luo , Huilong Zhu , Yung Fu Chong , Hung Y. Ng , Kern Rim , Nivo Rovedo
发明人： Zhijiong Luo , Huilong Zhu , Yung Fu Chong , Hung Y. Ng , Kern Rim , Nivo Rovedo
IPC分类号： H01L29/78 , H01L21/44
CPC分类号： H01L21/823814 , H01L21/823871 , H01L21/823878 , H01L29/665 , H01L29/6656 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： A structure, semiconductor device and method having a substantially L-shaped silicide element for a contact are disclosed. The substantially L-shaped silicide element, inter alia, reduces contact resistance and may allow increased density of CMOS circuits. In one embodiment, the structure includes a substantially L-shaped silicide element including a base member and an extended member, wherein the base member extends at least partially into a shallow trench isolation (STI) region such that a substantially horizontal surface of the base member directly contacts a substantially horizontal surface of the STI region; and a contact contacting the substantially L-shaped silicide element. The contact may include a notch region for mating with the base member and a portion of the extended member, which increases the silicide-to-contact area and reduces contact resistance. Substantially L-shaped silicide element may be formed about a source/drain region, which increases the silicon-to-silicide area, and reduces crowding and contact resistance.
摘要翻译：公开了具有用于接触的大致L形硅化物元件的结构，半导体器件和方法。基本上L形的硅化物元件尤其降低了接触电阻并且可以允许增加的CMOS电路的密度。在一个实施例中，该结构包括基本上为L形的硅化物元件，其包括基底构件和延伸构件，其中基底构件至少部分地延伸到浅沟槽隔离（STI）区域中，使得基底构件的基本水平的表面直接接触STI区域的基本水平的表面; 以及接触基本上L形的硅化物元件的接触。触点可以包括用于与基底构件和延伸构件的一部分配合的切口区域，这增加了硅化物与接触面积并降低了接触电阻。可以围绕源极/漏极区域形成基本上L形的硅化物元素，这增加了硅 - 硅化物面积，并且减少了拥挤和接触电阻。

5. 发明授权

US07595233B2 Gate stress engineering for MOSFET 失效
标题翻译： MOSFET栅极应力工程
公开(公告)号：US07595233B2
公开(公告)日：2009-09-29
申请号：US11421510
申请日：2006-06-01
申请人： Zhijiong Luo , Yung Fu Chong , Huilong Zhu
发明人： Zhijiong Luo , Yung Fu Chong , Huilong Zhu
IPC分类号： H01L21/8238
CPC分类号： H01L29/7833 , H01L29/66507 , H01L29/7845
摘要： Methods of stressing a channel of a transistor as a result of a material volume change in a gate structure and a related structure are disclosed. In one embodiment, a method includes forming a gate over the channel, wherein the gate includes several materials, such as layers of silicon materials and a conducting material layer, above a gate dielectric, and is surrounded by a spacer, and then providing a volume change to some of the materials in the gate so that a stress is induced in the channel as a result of the volume change. A gate structure for a MOSFET structure may include a layer of silicon material over a gate dielectric and a first silicide and second silicide over the silicon material, where the first silicide induces a stress in a channel of the device. The first and second suicides may be separated by a layer of silicon material or in contact with each other.
摘要翻译：公开了由于栅极结构的材料体积变化和相关结构而对晶体管的沟道施加应力的方法。在一个实施例中，一种方法包括在通道上形成栅极，其中栅极包括若干材料，例如硅材料层和导电材料层，在栅极电介质上方，并被间隔物环绕，然后提供体积改变为门中的一些材料，使得由于体积变化而在通道中引起应力。用于MOSFET结构的栅极结构可以包括在栅极电介质上的硅材料层，以及硅材料上的第一硅化物和第二硅化物，其中第一硅化物在器件的沟道中引起应力。第一和第二自杀剂可以被硅材料层分离或彼此接触。

6. 发明授权

US07442619B2 Method of forming substantially L-shaped silicide contact for a semiconductor device 有权
标题翻译：形成用于半导体器件的基本上L形硅化物接触的方法
公开(公告)号：US07442619B2
公开(公告)日：2008-10-28
申请号：US11383965
申请日：2006-05-18
申请人： Zhijiong Luo , Huilong Zhu , Yung Fu Chong , Hung Y. Ng , Kern Rim , Nivo Rovedo
发明人： Zhijiong Luo , Huilong Zhu , Yung Fu Chong , Hung Y. Ng , Kern Rim , Nivo Rovedo
IPC分类号： H01L21/283 , H01L23/482
CPC分类号： H01L21/823814 , H01L21/823871 , H01L21/823878 , H01L29/665 , H01L29/6656 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a semiconductor device having a substantially L-shaped silicide element forming a contact is disclosed. The substantially L-shaped silicide element, inter alia, reduces contact resistance and may allow increased density of CMOS circuits. In one embodiment, the substantially L-shaped silicide element includes a base member and an extended member, wherein the base member extends at least partially into a shallow trench isolation (STI) region such that a substantially horizontal surface of the base member directly contacts a substantially horizontal surface of the STI region; and a contact contacting the substantially L-shaped silicide element. The contact may include a notch region for mating with the base member and a portion of the extended member, which increases the silicide-to-contact area and reduces contact resistance. Substantially L-shaped silicide element may be formed about a source/drain region, which increases the silicon-to-silicide area, and reduces crowding and contact resistance.
摘要翻译：公开了一种制造具有形成接触的大致L形硅化物元件的半导体器件的方法。基本上L形的硅化物元件尤其降低了接触电阻并且可以允许增加的CMOS电路的密度。在一个实施例中，基本上L形的硅化物元件包括基底构件和延伸构件，其中基底构件至少部分地延伸到浅沟槽隔离（STI）区域中，使得基底构件的基本水平的表面直接接触 STI区域的基本水平的表面; 以及接触基本上L形的硅化物元件的接触。触点可以包括用于与基底构件和延伸构件的一部分配合的切口区域，这增加了硅化物与接触面积并降低了接触电阻。可以围绕源极/漏极区域形成基本上L形的硅化物元素，这增加了硅 - 硅化物面积，并且减少了拥挤和接触电阻。

7. 发明申请

US20070278583A1 GATE STRESS ENGINEERING FOR MOSFET 失效
标题翻译： MOSFET的栅极应力工程
公开(公告)号：US20070278583A1
公开(公告)日：2007-12-06
申请号：US11421510
申请日：2006-06-01
申请人： Zhijiong Luo , Yung Fu Chong , Huilong Zhu
发明人： Zhijiong Luo , Yung Fu Chong , Huilong Zhu
IPC分类号： H01L29/94
CPC分类号： H01L29/7833 , H01L29/66507 , H01L29/7845
摘要： Methods of stressing a channel of a transistor as a result of a material volume change in a gate structure and a related structure are disclosed. In one embodiment, a method includes forming a gate over the channel, wherein the gate includes several materials, such as layers of silicon materials and a conducting material layer, above a gate dielectric, and is surrounded by a spacer, and then providing a volume change to some of the materials in the gate so that a stress is induced in the channel as a result of the volume change. A gate structure for a MOSFET structure may include a layer of silicon material over a gate dielectric and a first silicide and second silicide over the silicon material, where the first silicide induces a stress in a channel of the device. The first and second suicides may be separated by a layer of silicon material or in contact with each other.
摘要翻译：公开了由于栅极结构的材料体积变化和相关结构而对晶体管的沟道施加应力的方法。在一个实施例中，一种方法包括在通道上形成栅极，其中栅极包括若干材料，例如硅材料层和导电材料层，在栅极电介质上方，并被间隔物环绕，然后提供体积改变为门中的一些材料，使得由于体积变化而在通道中引起应力。用于MOSFET结构的栅极结构可以包括在栅极电介质上的硅材料层，以及硅材料上的第一硅化物和第二硅化物，其中第一硅化物在器件的沟道中引起应力。第一和第二自杀剂可以被硅材料层分离或彼此接触。

8. 发明授权

US07482656B2 Method and structure to form self-aligned selective-SOI 失效
标题翻译：形成自对准选择性SOI的方法和结构
公开(公告)号：US07482656B2
公开(公告)日：2009-01-27
申请号：US11421594
申请日：2006-06-01
申请人： Zhijiong Luo , Yung Fu Chong , Kevin K Dezfulian , Huilong Zhu , Judson R Holt
发明人： Zhijiong Luo , Yung Fu Chong , Kevin K Dezfulian , Huilong Zhu , Judson R Holt
IPC分类号： H01L29/76
CPC分类号： H01L29/66628 , H01L29/0653 , H01L29/665 , H01L29/6656 , H01L29/66636
摘要： Methods of forming a self-aligned, selective semiconductor on insulator (SOI) structure and a related structure are disclosed. In one embodiment, a method includes providing a substrate; forming a gate structure over a channel within the substrate; recessing a portion of the substrate adjacent the channel; forming an insulating layer on a bottom of the recessed portion; and forming a semiconductor material above the insulating layer. An upper surface of the semiconductor material may be sloped. A MOSFET structure may include a substrate; a channel; a source region and a drain region adjacent the channel; a gate structure above the channel and the substrate; a shallow trench isolation (STI) distal from the gate structure; a selectively laid insulating layer in at least one of the source region and the drain region; and an epitaxially grown semiconductor material above the selectively laid insulating layer.
摘要翻译：公开了形成自对准选择性半导体绝缘体（SOI）结构和相关结构的方法。在一个实施例中，一种方法包括提供基底; 在所述衬底内的沟道上形成栅极结构; 使靠近通道的衬底的一部分凹陷; 在所述凹部的底部形成绝缘层; 以及在绝缘层上方形成半导体材料。半导体材料的上表面可以是倾斜的。 MOSFET结构可以包括衬底; 一个渠道与沟道相邻的源极区域和漏极区域; 在通道和衬底上方的栅极结构; 远离栅极结构的浅沟槽隔离（STI）; 在源极区域和漏极区域中的至少一个中选择性地铺设绝缘层; 以及在选择性铺设的绝缘层上方的外延生长的半导体材料。

9. 发明授权

US07413961B2 Method of fabricating a transistor structure 有权
标题翻译：制造晶体管结构的方法
公开(公告)号：US07413961B2
公开(公告)日：2008-08-19
申请号：US11383952
申请日：2006-05-17
申请人： Yung Fu Chong , Kevin K. Dezfulian , Zhijiong Luo , Huilong Zhu
发明人： Yung Fu Chong , Kevin K. Dezfulian , Zhijiong Luo , Huilong Zhu
IPC分类号： H01L21/76
CPC分类号： H01L29/7848 , H01L21/3065 , H01L21/31116 , H01L29/165 , H01L29/6653 , H01L29/6659 , H01L29/66628 , H01L29/66636
摘要： The present invention relates to semiconductor integrated circuits. More particularly, but not exclusively, the invention relates to strained channel complimentary metal oxide semiconductor (CMOS) transistor structures and fabrication methods thereof. There is provided a method of forming a strained channel transistor structure on a substrate, comprising the steps of: forming a source stressor recess comprising a deep source recess and a source extension recess; forming a drain stressor recess comprising a deep drain recess and a drain extension recess; and subsequently forming a source stressor in said source stressor recess and a drain stressor in said drain stressor recess. The deep source/drain and source/drain extension stressors are formed by an uninterrupted etch process and an uninterrupted epitaxy process.
摘要翻译：本发明涉及半导体集成电路。更具体地但非唯一地，本发明涉及应变通道互补金属氧化物半导体（CMOS）晶体管结构及其制造方法。提供了一种在衬底上形成应变通道晶体管结构的方法，包括以下步骤：形成包括深源凹槽和源极延伸凹槽的源极应力器凹部; 形成包括深排水凹槽和排水延伸凹槽的排水应力槽; 并且随后在所述源应力器凹部中形成源应力器，以及在所述漏应力器凹部中形成漏应力器。深源/漏极和源极/漏极延伸应力源通过不间断的蚀刻工艺和不间断的外延工艺形成。

10. 发明申请

US20070267753A1 SUBSTANTIALLY L-SHAPED SILICIDE FOR CONTACT AND RELATED METHOD 有权
标题翻译：用于接触的大量L型硅胶和相关方法
公开(公告)号：US20070267753A1
公开(公告)日：2007-11-22
申请号：US11383965
申请日：2006-05-18
申请人： Zhijiong Luo , Huilong Zhu , Yung Fu Chong , Hung Y. Ng , Kern Rim , Nivo Rovedo
发明人： Zhijiong Luo , Huilong Zhu , Yung Fu Chong , Hung Y. Ng , Kern Rim , Nivo Rovedo
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L21/823814 , H01L21/823871 , H01L21/823878 , H01L29/665 , H01L29/6656 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： A structure, semiconductor device and method having a substantially L-shaped silicide element for a contact are disclosed. The substantially L-shaped silicide element, inter alia, reduces contact resistance and may allow increased density of CMOS circuits. In one embodiment, the structure includes a substantially L-shaped silicide element including a base member and an extended member, wherein the base member extends at least partially into a shallow trench isolation (STI) region such that a substantially horizontal surface of the base member directly contacts a substantially horizontal surface of the STI region; and a contact contacting the substantially L-shaped silicide element. The contact may include a notch region for mating with the base member and a portion of the extended member, which increases the silicide-to-contact area and reduces contact resistance. Substantially L-shaped silicide element may be formed about a source/drain region, which increases the silicon-to-silicide area, and reduces crowding and contact resistance.
摘要翻译：公开了具有用于接触的大致L形硅化物元件的结构，半导体器件和方法。基本上L形的硅化物元件尤其降低了接触电阻并且可以允许增加的CMOS电路的密度。在一个实施例中，该结构包括基本上为L形的硅化物元件，其包括基底构件和延伸构件，其中基底构件至少部分地延伸到浅沟槽隔离（STI）区域中，使得基底构件的基本水平的表面直接接触STI区域的基本水平的表面; 以及接触基本上L形的硅化物元件的接触。触点可以包括用于与基底构件和延伸构件的一部分配合的切口区域，这增加了硅化物与接触面积并降低了接触电阻。可以围绕源极/漏极区域形成基本上L形的硅化物元素，这增加了硅 - 硅化物面积，并且减少了拥挤和接触电阻。

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