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1. 发明申请

US20110315961A1 Ultrathin Spacer Formation for Carbon-Based FET 有权
标题翻译：碳基FET的超薄间隔物形成
公开(公告)号：US20110315961A1
公开(公告)日：2011-12-29
申请号：US12826221
申请日：2010-06-29
申请人： Zhihong Chen , Dechao Guo , Shu-Jen Han , Kai Zhao
发明人： Zhihong Chen , Dechao Guo , Shu-Jen Han , Kai Zhao
IPC分类号： H01L29/76 , H01L29/78 , H01L21/334
CPC分类号： H01L29/1606 , H01L29/4908 , H01L29/66742 , H01L29/7781 , H01L29/78684
摘要： A method for formation of a carbon-based field effect transistor (FET) includes depositing a first dielectric layer on a carbon layer located on a substrate; forming a gate electrode on the first dielectric layer; etching an exposed portion of the first dielectric layer to expose a portion of the carbon layer; depositing a second dielectric layer over the gate electrode to form a spacer, wherein the second dielectric layer is deposited by atomic layer deposition (ALD), and wherein the second dielectric layer does not form on the exposed portion of the carbon layer; forming source and drain contacts on the carbon layer and forming a gate contact on the gate electrode to form the carbon-based FET.
摘要翻译：一种用于形成碳基场效应晶体管（FET）的方法包括：在位于衬底上的碳层上沉积第一介电层; 在所述第一电介质层上形成栅电极; 蚀刻第一介电层的暴露部分以暴露碳层的一部分; 在所述栅电极上沉积第二电介质层以形成间隔物，其中所述第二电介质层通过原子层沉积（ALD）沉积，并且其中所述第二电介质层不在所述碳层的暴露部分上形成; 在碳层上形成源极和漏极接触，并在栅电极上形成栅极接触以形成碳基FET。

2. 发明申请

US20120146001A1 ULTRATHIN SPACER FORMATION FOR CARBON-BASED FET 有权
标题翻译：基于碳的FET的超声波分离器形成
公开(公告)号：US20120146001A1
公开(公告)日：2012-06-14
申请号：US13401967
申请日：2012-02-22
申请人： Zhihong Chen , Dechao Guo , Shu-Jen Han , Kai Zhao
发明人： Zhihong Chen , Dechao Guo , Shu-Jen Han , Kai Zhao
IPC分类号： H01L29/78 , B82Y99/00
CPC分类号： H01L29/1606 , H01L29/4908 , H01L29/66742 , H01L29/7781 , H01L29/78684
摘要： A carbon-based field effect transistor (FET) includes a substrate; a carbon layer located on the substrate, the carbon layer comprising a channel region, and source and drain regions located on either side of the channel region; a gate electrode located on the channel region in the carbon layer, the gate electrode comprising a first dielectric layer, a gate metal layer located on the first dielectric layer, and a nitride layer located on the gate metal layer; and a spacer comprising a second dielectric layer located adjacent to the gate electrode, wherein the spacer is not located on the carbon layer.
摘要翻译：碳基场效应晶体管（FET）包括基板; 位于所述基板上的碳层，所述碳层包括沟道区，以及位于所述沟道区两侧的源区和漏区; 位于所述碳层中的沟道区上的栅电极，所述栅电极包括第一电介质层，位于所述第一电介质层上的栅极金属层和位于所述栅极金属层上的氮化物层; 以及间隔件，其包括邻近所述栅电极的第二电介质层，其中所述间隔物不位于所述碳层上。

3. 发明授权

US08193032B2 Ultrathin spacer formation for carbon-based FET 有权
标题翻译：碳基FET的超薄间隔物形成
公开(公告)号：US08193032B2
公开(公告)日：2012-06-05
申请号：US12826221
申请日：2010-06-29
申请人： Zhihong Chen , Dechao Guo , Shu-jen Han , Kai Zhao
发明人： Zhihong Chen , Dechao Guo , Shu-jen Han , Kai Zhao
IPC分类号： H01L21/00
CPC分类号： H01L29/1606 , H01L29/4908 , H01L29/66742 , H01L29/7781 , H01L29/78684
摘要： A method for formation of a carbon-based field effect transistor (FET) includes depositing a first dielectric layer on a carbon layer located on a substrate; forming a gate electrode on the first dielectric layer; etching an exposed portion of the first dielectric layer to expose a portion of the carbon layer; depositing a second dielectric layer over the gate electrode to form a spacer, wherein the second dielectric layer is deposited by atomic layer deposition (ALD), and wherein the second dielectric layer does not form on the exposed portion of the carbon layer; forming source and drain contacts on the carbon layer and forming a gate contact on the gate electrode to form the carbon-based FET.
摘要翻译：一种用于形成碳基场效应晶体管（FET）的方法包括：在位于衬底上的碳层上沉积第一介电层; 在所述第一电介质层上形成栅电极; 蚀刻第一介电层的暴露部分以暴露碳层的一部分; 在所述栅电极上沉积第二电介质层以形成间隔物，其中所述第二电介质层通过原子层沉积（ALD）沉积，并且其中所述第二电介质层不在所述碳层的暴露部分上形成; 在碳层上形成源极和漏极接触，并在栅电极上形成栅极接触以形成碳基FET。

4. 发明授权

US08274072B2 Ultrathin spacer formation for carbon-based FET 有权
标题翻译：碳基FET的超薄间隔物形成
公开(公告)号：US08274072B2
公开(公告)日：2012-09-25
申请号：US13401967
申请日：2012-02-22
申请人： Zhihong Chen , Dechao Guo , Shu-jen Han , Kai Zhao
发明人： Zhihong Chen , Dechao Guo , Shu-jen Han , Kai Zhao
IPC分类号： H01L29/76
CPC分类号： H01L29/1606 , H01L29/4908 , H01L29/66742 , H01L29/7781 , H01L29/78684
摘要： A carbon-based field effect transistor (FET) includes a substrate; a carbon layer located on the substrate, the carbon layer comprising a channel region, and source and drain regions located on either side of the channel region; a gate electrode located on the channel region in the carbon layer, the gate electrode comprising a first dielectric layer, a gate metal layer located on the first dielectric layer, and a nitride layer located on the gate metal layer; and a spacer comprising a second dielectric layer located adjacent to the gate electrode, wherein the spacer is not located on the carbon layer.
摘要翻译：碳基场效应晶体管（FET）包括基板; 位于所述基板上的碳层，所述碳层包括沟道区，以及位于所述沟道区两侧的源区和漏区; 位于所述碳层中的沟道区上的栅电极，所述栅电极包括第一电介质层，位于所述第一电介质层上的栅极金属层和位于所述栅极金属层上的氮化物层; 以及间隔件，其包括邻近所述栅电极的第二电介质层，其中所述间隔物不位于所述碳层上。

5. 发明授权

US08742475B2 Field effect transistor device and fabrication 有权
标题翻译：场效应晶体管器件和制造
公开(公告)号：US08742475B2
公开(公告)日：2014-06-03
申请号：US13554294
申请日：2012-07-20
申请人： Dechao Guo , Shu-Jen Han , Chung-Hsun Lin , Yanfeng Wang
发明人： Dechao Guo , Shu-Jen Han , Chung-Hsun Lin , Yanfeng Wang
IPC分类号： H01L21/02
CPC分类号： H01L29/42368 , H01L21/823842 , H01L21/823857 , H01L21/823871 , H01L29/66477
摘要： In one aspect of the present invention, a field effect transistor (FET) device includes a first FET including a dielectric layer disposed on a substrate, a first portion of a first metal layer disposed on the dielectric layer, and a second metal layer disposed on the first metal layer, a second FET including a second portion of the first metal layer disposed on the dielectric layer, and a boundary region separating the first FET from the second FET.
摘要翻译：在本发明的一个方面中，场效应晶体管（FET）器件包括：第一FET，其包括设置在基板上的电介质层，设置在电介质层上的第一金属层的第一部分和设置在电介质层上的第二金属层第一金属层，包括设置在电介质层上的第一金属层的第二部分的第二FET以及将第一FET与第二FET分离的边界区域。

6. 发明授权

US08519454B2 Structure and process for metal fill in replacement metal gate integration 有权
标题翻译：金属填充金属栅极整合的结构和工艺
公开(公告)号：US08519454B2
公开(公告)日：2013-08-27
申请号：US13075443
申请日：2011-03-30
申请人： Dechao Guo , Shu-Jen Han , Keith Kwong Hon Wong , Jun Yuan
发明人： Dechao Guo , Shu-Jen Han , Keith Kwong Hon Wong , Jun Yuan
IPC分类号： H01L29/76 , H01L21/338 , H01L21/84
CPC分类号： H01L29/4966 , H01L29/66545 , H01L29/7843
摘要： Processes for metal fill in replacement metal gate integration schemes and resultant devices are provided herein. The method includes forming a dummy gate on a semiconductor substrate. The dummy gate includes forming a metal layer between a first material and a second material. The method further includes partially removing the dummy gate to form an opening bounded by a spacer material. The method further includes forming a recess in the spacer material to widen a portion of the opening. The method further includes removing a remaining portion of the dummy gate through the opening to form a trench having the recess forming an upper portion thereof. The method further includes filling the trench and the recess with a replacement metal gate stack.
摘要翻译：本文提供了用于替换金属栅极集成方案和所得器件的金属填充工艺。该方法包括在半导体衬底上形成虚拟栅极。虚拟门包括在第一材料和第二材料之间形成金属层。该方法还包括部分地去除伪栅极以形成由间隔物材料限定的开口。该方法还包括在间隔物材料中形成凹槽以加宽开口的一部分。该方法还包括通过开口去除虚拟栅极的剩余部分以形成具有形成其上部的凹部的沟槽。该方法还包括用替换的金属栅极堆叠填充沟槽和凹部。

7. 发明授权

US08445371B2 Self-aligned contacts 有权
公开(公告)号：US08445371B2
公开(公告)日：2013-05-21
申请号：US12755752
申请日：2010-04-07
申请人： Dechao Guo , Wilfried E. A. Haensch , Shu-Jen Han , Chung-Hsun Lin
发明人： Dechao Guo , Wilfried E. A. Haensch , Shu-Jen Han , Chung-Hsun Lin
IPC分类号： H01L21/3205
CPC分类号： H01L21/28008 , H01L21/28052 , H01L21/28097 , H01L21/76897 , H01L29/517 , H01L29/66507 , H01L29/66545
摘要： A method of forming a gate structure with a self-aligned contact is provided and includes sequentially depositing a sacrificial layer and a secondary layer onto poly-Si disposed at a location of the gate structure, encapsulating the sacrificial layer, the secondary layer and the poly-Si, removing the sacrificial layer through openings formed in the secondary layer and forming silicide within at least the space formally occupied by the sacrificial layer.

8. 发明授权

US08338258B2 Embedded stressor for semiconductor structures 有权
标题翻译：半导体结构的嵌入式应力器
公开(公告)号：US08338258B2
公开(公告)日：2012-12-25
申请号：US12625827
申请日：2009-11-25
申请人： Dechao Guo , Shu-Jen Han , Pranita Kulkarni , Philip J. Oldiges
发明人： Dechao Guo , Shu-Jen Han , Pranita Kulkarni , Philip J. Oldiges
IPC分类号： H01L21/336
CPC分类号： H01L29/1054 , H01L29/517 , H01L29/66651 , H01L29/66772 , H01L29/78687
摘要： A method of fabricating an embedded stressor within a semiconductor structure and a semiconductor structure including the embedded stressor includes forming forming a dummy gate stack over a substrate of stressor material, anistropically etching sidewall portions of the substrate subjacent to the dummy gate stack to form the embedded stressor having angled sidewall portions, forming conductive material onto the angled sidewall portions of the embedded stressor, removing the dummy gate stack, planarizing the conductive material, and forming a gate stack on the conductive material.
摘要翻译：一种在半导体结构内制造嵌入式应力器的方法以及包括所述嵌入式应力器的半导体结构的方法包括在所述应力源材料的衬底上形成形成虚拟栅极叠层的方法，将所述衬底的与所述虚拟栅极堆叠相邻的衬底的侧壁部分，应力器具有成角度的侧壁部分，将导电材料形成在嵌入式应力源的成角度的侧壁部分上，去除虚拟栅极堆叠，平坦化导电材料，以及在导电材料上形成栅极叠层。

9. 发明授权

US08338256B2 Multi-gate transistor having sidewall contacts 有权
标题翻译：具有侧壁接触的多栅极晶体管
公开(公告)号：US08338256B2
公开(公告)日：2012-12-25
申请号：US12832829
申请日：2010-07-08
申请人： Josephine B. Chang , Dechao Guo , Shu-Jen Han , Chung-Hsun Lin
发明人： Josephine B. Chang , Dechao Guo , Shu-Jen Han , Chung-Hsun Lin
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L29/785 , H01L29/66795 , H01L2029/7858
摘要： A multi-gate transistor having a plurality of sidewall contacts and a fabrication method that includes forming a semiconductor fin on a semiconductor substrate and etching a trench within the semiconductor fin, depositing an oxide material within the etched trench, and etching the oxide material to form a dummy oxide layer along exposed walls within the etched trench; and forming a spacer dielectric layer along vertical sidewalls of the dummy oxide layer. The method further includes removing exposed dummy oxide layer in a channel region in the semiconductor fin and beneath the spacer dielectric layer, forming a high-k material liner along sidewalls of the channel region in the semiconductor fin, forming a metal gate stack within the etched trench, and forming a plurality of sidewall contacts within the semiconductor fin along adjacent sidewalls of the dummy oxide layer.
摘要翻译：一种具有多个侧壁触点的多栅极晶体管及其制造方法，包括在半导体衬底上形成半导体鳍片并蚀刻半导体鳍片内的沟槽，在蚀刻沟槽内沉积氧化物材料，并蚀刻氧化物材料以形成沿着蚀刻沟槽内的暴露壁的虚拟氧化物层; 以及沿所述虚拟氧化物层的垂直侧壁形成间隔电介质层。该方法还包括去除半导体鳍片中的沟道区域中的暴露的虚拟氧化物层并且在间隔物电介质层下方形成沿着半导体鳍片中的沟道区域的侧壁形成高k材料衬垫，在蚀刻沟槽，并且在半导体鳍片内沿虚拟氧化物层的相邻侧壁形成多个侧壁接触。

10. 发明申请

US20120261728A1 EMBEDDED STRESSOR FOR SEMICONDUCTOR STRUCTURES 有权
标题翻译：用于半导体结构的嵌入式压电器
公开(公告)号：US20120261728A1
公开(公告)日：2012-10-18
申请号：US13529558
申请日：2012-06-21
申请人： Dechao Guo , Shu-Jen Han , Pranita Kulkarni , Philip J. Oldiges
发明人： Dechao Guo , Shu-Jen Han , Pranita Kulkarni , Philip J. Oldiges
IPC分类号： H01L29/78
CPC分类号： H01L29/1054 , H01L29/517 , H01L29/66651 , H01L29/66772 , H01L29/78687
摘要： A semiconductor structure includes a semiconductor substrate; a gate stack on the semiconductor substrate; a plurality of spacers disposed on laterally opposing sides of the gate stack; source and drain regions proximate to the spacers, and a channel region subjacent to the gate stack and disposed between the source and drain regions; and a stressor subjacent to the channel region, and embedded within the semiconductor substrate, the embedded stressor being formed of a triangular-shape.
摘要翻译：半导体结构包括半导体衬底; 半导体衬底上的栅极堆叠; 设置在所述栅极堆叠的横向相对侧上的多个间隔件; 邻近间隔物的源极和漏极区域以及位于栅极堆叠下方并设置在源极和漏极区域之间的沟道区域; 以及位于所述沟道区域的下方并嵌入在所述半导体衬底内的应力器，所述嵌入式应力器由三角形形成。

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