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    • 7. 发明申请
    • Block matching method for video compression
    • 视频压缩的块匹配方法
    • US20050175105A1
    • 2005-08-11
    • US10991495
    • 2004-11-19
    • Ren-Hao GuYuh-Feng Hsu
    • Ren-Hao GuYuh-Feng Hsu
    • H04N7/12H04N7/26
    • H04N19/533
    • The present invention discloses a block matching method for video compression. Wherein, the video frame currently under process is referred as first frame, and the reconstructed frame obtained from the result of the previous process is referred as second frame. The block matching method of the present invention is able to spot a MB on the second frame using a specified algorithm that the SAD of the spotted MB is the smallest while comparing with a designated MB of the first frame. The characteristic of the method of the present invention can be described as following: While simultaneously searching a plurality of points on the second frame, the threshold SAD can be defined as multiplying the minimal PSAD of each comparison by a parameter such that the threshold SAD can be used for determining the next search location among the plural points, that is, the next search location is the point with minimal SAD and can be found by rejecting the points with PSAD larger than an initial difference and keeping the points with PSAD smaller than the initial difference.
    • 本发明公开了一种用于视频压缩的块匹配方法。 其中,当前正在处理的视频帧被称为第一帧,并且将从先前处理的结果获得的重构帧称为第二帧。 本发明的块匹配方法能够使用指定的算法来识别第二帧上的MB,使得所识别的MB的SAD与第一帧的指定MB相比最小。 本发明方法的特征可以描述如下:在同时搜索第二帧上的多个点的同时,可以将阈值SAD定义为将每个比较的最小PSAD乘以参数,使得阈值SAD可以 用于确定多个点之间的下一个搜索位置,即,下一个搜索位置是具有最小SAD的点,并且可以通过拒绝具有大于初始差异的PSAD的点来保持PSAD小于 初始差异。
    • 8. 发明授权
    • General finite-field multiplier and method of the same
    • 一般有限域乘法器和方法相同
    • US06925479B2
    • 2005-08-02
    • US09843802
    • 2001-04-30
    • Oscal Tzyh-Chiang ChenYuh-Feng Hsu
    • Oscal Tzyh-Chiang ChenYuh-Feng Hsu
    • G06F7/72
    • G06F7/724
    • A general finite-field multiplier and the method of the same are disclosed for the operation of the finite-field multipliers of various specifications. In the multiplier, AND gates and XOR gates are used as primary components, and the inputs include two elements A and B to be multiplied and the coefficients of a variable polynomial p(x). This multiplier can be applied to the finite-field elements of different bit number. After all the coefficients of the A, B and p(x) are input, the values of a desired C can be obtained rapidly. Since the output values are parallel output, the application is very convenient. Furthermore, the multiplier can be used in the RS chip for different specifications.
    • 公开了用于各种规格的有限域乘法器的操作的通用有限域乘法器及其方法。 在乘法器中,AND门和XOR门用作主要组件,并且输入包括要乘以的两个​​元素A和B以及可变多项式p(x)的系数。 该乘法器可以应用于不同位数的有限域元素。 在输入所有A,B和P(x)的系数之后,可以快速获得期望的C值。 由于输出值为并行输出,因此应用非常方便。 此外,乘法器可用于RS芯片中的不同规格。