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1. 发明授权

US07151315B2 Method of a non-metal barrier copper damascene integration 有权
标题翻译：非金属阻挡铜大马士革一体化方法
公开(公告)号：US07151315B2
公开(公告)日：2006-12-19
申请号：US10459222
申请日：2003-06-11
申请人： Zhen-Cheng Wu , Yung-Chen Lu , Syun-Ming Jang
发明人： Zhen-Cheng Wu , Yung-Chen Lu , Syun-Ming Jang
IPC分类号： H01L23/50
CPC分类号： H01L21/76802 , H01L21/76831 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure provides a method, integrated circuit, and interconnect structure utilizing non-metal barrier copper damascene integration. The method is provided for fabricating an interconnect for connecting to one or more front end of line (FEOL) devices. The method includes forming a layer of doped oxide on the one or more FEOL devices and forming a first barrier layer on the layer of doped oxide, the first barrier layer comprising such material as silicon oxycarbide (SiOC) or silicon carbonitride (SiCN). The method further includes forming a plurality of refractory metal plugs in the first barrier layer and the doped oxide layer, forming a low dielectric constant film over the first barrier layer and the plurality of refractory metal plugs, and performing a first etch to create trenches through the low dielectric constant film. The plurality of refractory metal plugs and the first barrier layer perform as an etch-stop.
摘要翻译：本公开提供了利用非金属阻挡铜镶嵌一体化的方法，集成电路和互连结构。该方法用于制造用于连接到一个或多个前端（FEOL）装置的互连件。该方法包括在一个或多个FEOL器件上形成掺杂氧化物层，并在掺杂氧化物层上形成第一势垒层，第一势垒层包含碳氧化硅（SiOC）或碳氮化硅（SiCN）等材料。该方法还包括在第一阻挡层和掺杂氧化物层中形成多个难熔金属塞，在第一阻挡层和多个耐火金属插塞上形成低介电常数膜，并进行第一蚀刻以产生沟槽低介电常数膜。多个难熔金属插塞和第一阻挡层执行蚀刻停止。

2. 发明授权

US07056826B2 Method of forming copper interconnects 失效
标题翻译：形成铜互连的方法
公开(公告)号：US07056826B2
公开(公告)日：2006-06-06
申请号：US10337684
申请日：2003-01-07
申请人： Zhen-Cheng Wu , Yung-Cheng Lu , Ying-Tsung Chen , Syun-Ming Jang
发明人： Zhen-Cheng Wu , Yung-Cheng Lu , Ying-Tsung Chen , Syun-Ming Jang
IPC分类号： H01L21/4763
CPC分类号： H01L23/5226 , H01L21/76807 , H01L21/76829 , H01L21/76831 , H01L21/76832 , H01L21/76834 , H01L21/7684 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method of forming copper interconnects for an integrated circuit is provided. An antireflective coating layer is formed over an insulating layer formed over a semiconductor substrate. An interconnect pattern is patterned and etched into said insulating layer. A diffusion barrier layer is then conformally deposited in a deposition chamber along the etched interconnect pattern, wherein the antireflective coating is removed in said chamber before deposition of the barrier layer. Copper interconnects are then formed in the interconnect pattern etched in the insulating layer.
摘要翻译：提供一种形成用于集成电路的铜互连的方法。在半导体衬底上形成的绝缘层上形成抗反射涂层。将互连图案图案化并蚀刻到所述绝缘层中。然后沿着蚀刻的互连图案将扩散阻挡层共形沉积在沉积室中，其中在沉积阻挡层之前在所述室中去除抗反射涂层。然后在绝缘层中蚀刻的互连图案中形成铜互连。

3. 发明授权

US06878621B2 Method of fabricating barrierless and embedded copper damascene interconnects 失效
标题翻译：制造无障碍和嵌入铜大马士革互连的方法
公开(公告)号：US06878621B2
公开(公告)日：2005-04-12
申请号：US10346382
申请日：2003-01-17
申请人： Zhen-Cheng Wu , Lain-Jong Li , Yung-Chen Lu , Syun-Ming Jang
发明人： Zhen-Cheng Wu , Lain-Jong Li , Yung-Chen Lu , Syun-Ming Jang
IPC分类号： H01L21/768 , H01L21/44 , H01L21/4763
CPC分类号： H01L21/76834 , H01L21/76832 , H01L21/76835 , H01L21/76885
摘要： A method for forming at least one barrierless, embedded metal structure comprising the following steps. A structure having a patterned dielectric layer formed thereover with at least one opening exposing at least one respective portion of the structure. Respective metal structures are formed within each respective opening. The first dielectric layer is removed to expose the top and at least a portion of the side walls of the respective at least one metal structure. A dielectric barrier layer is formed over the structure and the exposed top of the respective metal structure. A second, conformal dielectric layer is formed over the dielectric barrier layer to complete the respective barrierless at least one metal structure embedded within the second, conformal dielectric layer. The dielectric barrier layer preventing diffusion of the metal comprising the respective at least one metal structure into the second, conformal dielectric layer.
摘要翻译：一种形成至少一个无障碍嵌入金属结构的方法，包括以下步骤。具有形成在其上的图案化电介质层的结构，其中至少一个开口暴露出结构的至少一个相应部分。在每个相应的开口内形成相应的金属结构。去除第一电介质层以暴露相应的至少一个金属结构的顶部和至少一部分侧壁。介电阻挡层形成在相应的金属结构的结构和暴露的顶部上。在电介质阻挡层上方形成第二个保形介电层，以完成嵌入在第二保形电介质层内的相应无障碍的至少一个金属结构。电介质阻挡层防止包含相应的至少一种金属结构的金属扩散到第二保形电介质层中。

4. 发明授权

US07135408B2 Metal barrier integrity via use of a novel two step PVD-ALD deposition procedure 有权
标题翻译：通过使用新型两步PVD-ALD沉积程序，金属屏障完整性
公开(公告)号：US07135408B2
公开(公告)日：2006-11-14
申请号：US10283862
申请日：2002-10-30
申请人： Zhen-Cheng Wu , Syun-Ming Jang
发明人： Zhen-Cheng Wu , Syun-Ming Jang
IPC分类号： H01L21/44
CPC分类号： H01L21/76843
摘要： A method of forming a barrier layer on the surface of an opening defined in a porous, low dielectric constant (low k), layer, has been developed. The method features the use of a two step deposition procedure using a physical vapor deposition (PVD), procedure to initially deposit a thin underlying, first component of the barrier layer, while an atomic layer deposition (ALD), procedure is then employed for deposition of an overlying second barrier layer component. The underlying, thin barrier layer component obtained via PVD procedures is comprised with the desired properties needed to interface the porous, low k layer, while the overlying barrier layer component obtained via ALD procedures exhibits excellent thickness uniformity.
摘要翻译：已经开发了在多孔低介电常数（低k）层限定的开口的表面上形成阻挡层的方法。该方法的特征在于使用物理气相沉积（PVD）的两步沉积程序，以便首先沉积阻挡层的薄的底层第一部分，同时使用原子层沉积（ALD）方法进行沉积的上覆第二阻挡层组分。通过PVD方法获得的底层薄阻挡层组分包含与多孔低k层接合所需的所需性质，而通过ALD方法获得的上覆阻挡层组分表现出优异的厚度均匀性。

5. 发明申请

US20060024954A1 Copper damascene barrier and capping layer 审中-公开
标题翻译：铜镶嵌屏障和封盖层
公开(公告)号：US20060024954A1
公开(公告)日：2006-02-02
申请号：US10910007
申请日：2004-08-02
申请人： Zhen-Cheng Wu , Lain-Jong Li , Yung-Chen Lu , Syun-Ming Jang
发明人： Zhen-Cheng Wu , Lain-Jong Li , Yung-Chen Lu , Syun-Ming Jang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76829 , H01L21/76831 , H01L21/7684 , H01L21/76846
摘要： A method for forming a damascene with improved electrical properties and resulting structure thereof including providing at least one dielectric insulating layer overlying a first etch stop layer; forming an anti-reflectance coating (ARC) layer prior to a photolithographic patterning process; forming at least one opening extending through a thickness portion of the at least one dielectric insulating layer and first etch stop layer according to said photolithographic patterning and an etching process; blanket depositing a barrier layer including material selected from the group consisting of silicon carbide and silicon oxycarbide to line the at least one opening; blanket depositing a refractory metal liner over the barrier layer; blanket depositing at least one metal layer to fill the at least one opening; and, removing at least the at least one metal layer overlying the at least one opening level according to a chemical mechanical polish (CMP) process.
摘要翻译：一种用于形成具有改善的电性能及其结构的镶嵌体的方法，包括提供覆盖在第一蚀刻停止层上的至少一个介电绝缘层; 在光刻图案化工艺之前形成抗反射涂层（ARC）层; 根据所述光刻图案和蚀刻工艺形成至少一个延伸穿过所述至少一个介电绝缘层的厚度部分的开口和第一蚀刻停止层; 覆盖沉积包括选自碳化硅和碳氧化硅的材料的阻挡层，以使所述至少一个开口线对准; 在阻挡层上铺设难熔金属衬垫; 毯子沉积至少一个金属层以填充所述至少一个开口; 以及根据化学机械抛光（CMP）工艺，至少去除覆盖所述至少一个开口水平面的所述至少一个金属层。

6. 发明申请

US20050245100A1 Reliability improvement of SiOC etch with trimethylsilane gas passivation in Cu damascene interconnects 有权
标题翻译：在Cu大马士革互连中三甲基硅烷气体钝化的SiOC蚀刻的可靠性提高
公开(公告)号：US20050245100A1
公开(公告)日：2005-11-03
申请号：US10835788
申请日：2004-04-30
申请人： Zhen-Cheng Wu , Bi-Troug Chen , Weng Chang , Syun-Ming Jang , Su-Horng Lin
发明人： Zhen-Cheng Wu , Bi-Troug Chen , Weng Chang , Syun-Ming Jang , Su-Horng Lin
IPC分类号： H01L21/306 , H01L21/314 , H01L21/316 , H01L21/4763 , H01L21/768
CPC分类号： H01L21/31633 , H01L21/02046 , H01L21/02126 , H01L21/02211 , H01L21/02274 , H01L21/02304 , H01L21/02315 , H01L21/3144 , H01L21/3145 , H01L21/3148 , H01L21/76807 , H01L21/76829 , H01L21/76832
摘要： A method of forming a SiCOH etch stop layer in a copper damascene process is described. A substrate with an exposed metal layer is treated with H2 or NH3 plasma to remove metal oxides. Trimethylsilane is flowed into a chamber with no RF power at about 350° C. to form at least a monolayer on the exposed metal layer. The SiCOH layer is formed by a PECVD process including trimethylsilane and CO2 source gases. Optionally, a composite SiCOH layer comprised of a low compressive stress layer on a high compressive stress layer is formed on the substrate. A conventional damascene sequence is then used to form a second metal layer on the exposed metal layer. Via Rc stability is improved and a lower leakage current is achieved with the trimethylsilane passivation layer. A composite SiCOH etch stop layer provides improved stress migration resistance compared to a single low stress SiCOH layer.
摘要翻译：描述了在铜镶嵌工艺中形成SiCOH蚀刻停止层的方法。具有暴露的金属层的衬底用H 2 N 3或NH 3 3等离子体处理以除去金属氧化物。三甲基硅烷在约350℃下流入没有RF功率的室，以在暴露的金属层上形成至少单层。 SiCOH层通过包括三甲基硅烷和CO 2原子气体的PECVD工艺形成。任选地，在基底上形成由高压缩应力层上的低压应力层构成的复合SiCOH层。然后使用常规的镶嵌序列在暴露的金属层上形成第二金属层。通过Rc稳定性提高，并且用三甲基硅烷钝化层实现较低的漏电流。与单个低应力SiCOH层相比，复合SiCOH蚀刻停止层提供改进的应力迁移阻力。

7. 发明申请

US20050212135A1 Interconnect structure with dielectric barrier and fabrication method thereof 有权
标题翻译：具有电介质阻挡层的互连结构及其制造方法
公开(公告)号：US20050212135A1
公开(公告)日：2005-09-29
申请号：US10811186
申请日：2004-03-26
申请人： Zhen-Cheng Wu , Ying-Tsung Chen , Yun-Cheng Lu , Syun-Ming Jang
发明人： Zhen-Cheng Wu , Ying-Tsung Chen , Yun-Cheng Lu , Syun-Ming Jang
IPC分类号： H01L21/4763 , H01L21/768 , H01L23/52 , H01L23/532
CPC分类号： H01L21/7682 , H01L21/76885 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure with dielectric barrier and fabrication thereof. The interconnect structure includes a semiconductor substrate and a plurality of stacked structures formed thereon, each stacked structure including a conductive line and a conductive plug thereon. A conformal dielectric barrier is formed over the surfaces of the stacked structures and a blanket second dielectric layer is formed over the dielectric barrier to form an inter-metal layer.
摘要翻译：具有介电阻挡层及其制造的互连结构。互连结构包括半导体衬底和形成在其上的多个堆叠结构，每个堆叠结构包括导电线和导电插头。在层叠结构的表面上形成保形电介质阻挡层，并且在电介质阻挡层之上形成覆盖的第二介电层以形成金属间层。

8. 发明授权

US07193325B2 Reliability improvement of SiOC etch with trimethylsilane gas passivation in Cu damascene interconnects 有权
标题翻译：在Cu大马士革互连中三甲基硅烷气体钝化的SiOC蚀刻的可靠性提高
公开(公告)号：US07193325B2
公开(公告)日：2007-03-20
申请号：US10835788
申请日：2004-04-30
申请人： Zhen-Cheng Wu , Bi-Troug Chen , Weng Chang , Syun-Ming Jang , Su-Horng Lin
发明人： Zhen-Cheng Wu , Bi-Troug Chen , Weng Chang , Syun-Ming Jang , Su-Horng Lin
IPC分类号： H01L23/48
CPC分类号： H01L21/31633 , H01L21/02046 , H01L21/02126 , H01L21/02211 , H01L21/02274 , H01L21/02304 , H01L21/02315 , H01L21/3144 , H01L21/3145 , H01L21/3148 , H01L21/76807 , H01L21/76829 , H01L21/76832
摘要： A method of forming a SiCOH etch stop layer in a copper damascene process is described. A substrate with an exposed metal layer is treated with H2 or NH3 plasma to remove metal oxides. Trimethylsilane is flowed into a chamber with no RF power at about 350° C. to form at least a monolayer on the exposed metal layer. The SiCOH layer is formed by a PECVD process including trimethylsilane and CO2 source gases. Optionally, a composite SiCOH layer comprised of a low compressive stress layer on a high compressive stress layer is formed on the substrate. A conventional damascene sequence is then used to form a second metal layer on the exposed metal layer. Via Rc stability is improved and a lower leakage current is achieved with the trimethylsilane passivation layer. A composite SiCOH etch stop layer provides improved stress migration resistance compared to a single low stress SiCOH layer.
摘要翻译：描述了在铜镶嵌工艺中形成SiCOH蚀刻停止层的方法。具有暴露的金属层的衬底用H 2 N 3或NH 3 3等离子体处理以除去金属氧化物。三甲基硅烷在约350℃下流入没有RF功率的室，以在暴露的金属层上形成至少单层。 SiCOH层通过包括三甲基硅烷和CO 2原子气体的PECVD工艺形成。任选地，在基底上形成由高压缩应力层上的低压应力层构成的复合SiCOH层。然后使用常规的镶嵌序列在暴露的金属层上形成第二金属层。通过Rc稳定性提高，并且用三甲基硅烷钝化层实现较低的漏电流。与单个低应力SiCOH层相比，复合SiCOH蚀刻停止层提供改进的应力迁移阻力。

9. 发明授权

US06753607B1 Structure for improving interlevel conductor connections 失效
标题翻译：改善层间导体连接的结构
公开(公告)号：US06753607B1
公开(公告)日：2004-06-22
申请号：US10441511
申请日：2003-05-19
申请人： Zhen-Cheng Wu , Yung-Cheng Lu , Syun-Ming Jang
发明人： Zhen-Cheng Wu , Yung-Cheng Lu , Syun-Ming Jang
IPC分类号： H01L2348
CPC分类号： H01L21/02126 , H01L21/02312 , H01L21/31051 , H01L21/31633 , H01L21/76829
摘要： The present invention relates to an improved integrated circuit structure including adjacent conductive and dielectric layers having a continuous, planar top surface, produced by a process which includes treating the surface with a silane compound, followed by depositing an etch stop layer over the surface, wherein a glue layer is not applied to the surface.
摘要翻译：本发明涉及一种改进的集成电路结构，其包括具有连续的平坦顶表面的相邻的导电和电介质层，其通过包括用硅烷化合物处理表面的方法产生，然后在表面上沉积蚀刻停止层，其中胶层不施加到表面。

10. 发明授权

US07196423B2 Interconnect structure with dielectric barrier and fabrication method thereof 有权
标题翻译：具有电介质阻挡层的互连结构及其制造方法
公开(公告)号：US07196423B2
公开(公告)日：2007-03-27
申请号：US10811186
申请日：2004-03-26
申请人： Zhen-Cheng Wu , Ying-Tsung Chen , Yun-Cheng Lu , Syun-Ming Jang
发明人： Zhen-Cheng Wu , Ying-Tsung Chen , Yun-Cheng Lu , Syun-Ming Jang
IPC分类号： H01L23/48
CPC分类号： H01L21/7682 , H01L21/76885 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure with dielectric barrier and fabrication thereof. The interconnect structure includes a semiconductor substrate and a plurality of stacked structures formed thereon, each stacked structure including a conductive line and a conductive plug thereon. A conformal dielectric barrier is formed over the surfaces of the stacked structures and a blanket second dielectric layer is formed over the dielectric barrier to form an inter-metal layer.
摘要翻译：具有介电阻挡层及其制造的互连结构。互连结构包括半导体衬底和形成在其上的多个堆叠结构，每个堆叠结构包括导电线和导电插头。在层叠结构的表面上形成保形电介质阻挡层，并且在电介质阻挡层之上形成覆盖的第二介电层以形成金属间层。

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