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1. 发明申请

US20090327665A1 Efficient parallel floating point exception handling in a processor 有权
标题翻译：处理器中的高效并行浮点异常处理
公开(公告)号：US20090327665A1
公开(公告)日：2009-12-31
申请号：US12217084
申请日：2008-06-30
申请人： Zeev Sperber , Shachar Finkelstein , Gregory Pribush , Amit Gradstein , Guy Bale , Thierry Pons
发明人： Zeev Sperber , Shachar Finkelstein , Gregory Pribush , Amit Gradstein , Guy Bale , Thierry Pons
IPC分类号： G06F9/302
CPC分类号： G06F9/3861 , G06F9/30014 , G06F9/30036
摘要： Methods and apparatus are disclosed for handling floating point exceptions in a processor that executes single-instruction multiple-data (SIMD) instructions. In one embodiment a numerical exception is identified for a SIMD floating point operation and SIMD micro-operations are initiated to generate two packed partial results of a packed result for the SIMD floating point operation. A SIMD denormalization micro-operation is initiated to combine the two packed partial results and to denormalize one or more elements of the combined packed partial results to generate a packed result for the SIMD floating point operation having one or more denormal elements. Flags are set and stored with packed partial results to identify denormal elements. In one embodiment a SIMD normalization micro-operation is initiated to generate a normalized pseudo internal floating point representation prior to the SIMD floating point operation when it uses multiplication.
摘要翻译：公开了用于处理执行单指令多数据（SIMD）指令的处理器中的浮点异常的方法和装置。在一个实施例中，识别用于SIMD浮点运算的数字异常，并启动SIMD微操作以产生用于SIMD浮点运算的打包结果的两个打包部分结果。启动SIMD非规范化微操作以组合两个打包的部分结果并且对组合的打包部分结果的一个或多个元素进行非规范化，以生成具有一个或多个异常元素的SIMD浮点运算的打包结果。标志被设置和存储与打包部分结果以识别异常元素。在一个实施例中，当SIMD标准化微操作在使用乘法时在SIMD浮点运算之前产生归一化的伪内部浮点表示。

2. 发明授权

US09092226B2 Efficient parallel floating point exception handling in a processor 有权
标题翻译：处理器中的高效并行浮点异常处理
公开(公告)号：US09092226B2
公开(公告)日：2015-07-28
申请号：US13325559
申请日：2011-12-14
申请人： Zeev Sperber , Shachar Finkelstein , Gregory Pribush , Amit Gradstein , Guy Bale , Thierry Pons
发明人： Zeev Sperber , Shachar Finkelstein , Gregory Pribush , Amit Gradstein , Guy Bale , Thierry Pons
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3861 , G06F9/30014 , G06F9/30036
摘要： Methods and apparatus are provided for handling floating point exceptions in a processor that executes single-instruction multiple-data (SIMD) instructions. In one example a numerical exception is identified for a SIMD floating point operation and SIMD micro-operations are initiated to generate two packed partial results of a packed result for the SIMD floating point operation. A SIMD denormalization micro-operation is initiated to combine the two packed partial results and to denormalize one or more elements of the combined packed partial results to generate a packed result for the SIMD floating point operation having one or more denormal elements. Flags are set and stored with packed partial results to identify denormal elements. In one example a SIMD normalization micro-operation is initiated to generate a normalized pseudo internal floating point representation prior to the SIMD floating point operation when it uses multiplication.
摘要翻译：提供了用于处理执行单指令多数据（SIMD）指令的处理器中的浮点异常的方法和装置。在一个示例中，识别用于SIMD浮点运算的数字异常，并且启动SIMD微操作以生成用于SIMD浮点运算的打包结果的两个打包部分结果。启动SIMD非规范化微操作以组合两个打包的部分结果并且对组合的打包部分结果的一个或多个元素进行非规范化，以生成具有一个或多个异常元素的SIMD浮点运算的打包结果。标志被设置和存储与打包部分结果以识别异常元素。在一个示例中，当SIMD归一化微操作在使用乘法时在SIMD浮点运算之前产生归一化的伪内部浮点表示。

3. 发明授权

US08103858B2 Efficient parallel floating point exception handling in a processor 有权
标题翻译：处理器中的高效并行浮点异常处理
公开(公告)号：US08103858B2
公开(公告)日：2012-01-24
申请号：US12217084
申请日：2008-06-30
申请人： Zeev Sperber , Shachar Finkelstein , Gregory Pribush , Arnit Gradstein , Guy Bale , Thierry Pons
发明人： Zeev Sperber , Shachar Finkelstein , Gregory Pribush , Arnit Gradstein , Guy Bale , Thierry Pons
IPC分类号： G06F9/00
CPC分类号： G06F9/3861 , G06F9/30014 , G06F9/30036
摘要： Methods and apparatus are disclosed for handling floating point exceptions in a processor that executes single-instruction multiple-data (SIMD) instructions. In one embodiment a numerical exception is identified for a SIMD floating point operation and SIMD micro-operations are initiated to generate two packed partial results of a packed result for the SIMD floating point operation. A SIMD denormalization micro-operation is initiated to combine the two packed partial results and to denormalize one or more elements of the combined packed partial results to generate a packed result for the SIMD floating point operation having one or more denormal elements. Flags are set and stored with packed partial results to identify denormal elements. In one embodiment a SIMD normalization micro-operation is initiated to generate a normalized pseudo internal floating point representation prior to the SIMD floating point operation when it uses multiplication.
摘要翻译：公开了用于处理执行单指令多数据（SIMD）指令的处理器中的浮点异常的方法和装置。在一个实施例中，识别用于SIMD浮点运算的数字异常，并启动SIMD微操作以产生用于SIMD浮点运算的打包结果的两个打包部分结果。启动SIMD非规范化微操作以组合两个打包的部分结果并且对组合的打包部分结果的一个或多个元素进行非规范化，以生成具有一个或多个异常元素的SIMD浮点运算的打包结果。标志被设置和存储与打包部分结果以识别异常元素。在一个实施例中，当SIMD标准化微操作在使用乘法时在SIMD浮点运算之前产生归一化的伪内部浮点表示。

4. 发明申请

US20120084533A1 Efficient Parallel Floating Point Exception Handling In A Processor 审中-公开
标题翻译：处理器中有效的并行浮点异常处理
公开(公告)号：US20120084533A1
公开(公告)日：2012-04-05
申请号：US13325559
申请日：2011-12-14
申请人： Zeev Sperber , Shachar Finkelstein , Gregory Pribush , Arnit Gradstein , Guy Bale , Thierry Pons
发明人： Zeev Sperber , Shachar Finkelstein , Gregory Pribush , Arnit Gradstein , Guy Bale , Thierry Pons
IPC分类号： G06F9/30 , G06F9/38 , G06F9/302
CPC分类号： G06F9/3861 , G06F9/30014 , G06F9/30036
摘要： Methods and apparatus are disclosed for handling floating point exceptions in a processor that executes single-instruction multiple-data (SIMD) instructions. In one embodiment a numerical exception is identified for a SIMD floating point operation and SIMD micro-operations are initiated to generate two packed partial results of a packed result for the SIMD floating point operation. A SIMD denormalization micro-operation is initiated to combine the two packed partial results and to denormalize one or more elements of the combined packed partial results to generate a packed result for the SIMD floating point operation having one or more denormal elements. Flags are set and stored with packed partial results to identify denormal elements. In one embodiment a SIMD normalization micro-operation is initiated to generate a normalized pseudo internal floating point representation prior to the SIMD floating point operation when it uses multiplication.
摘要翻译：公开了用于处理执行单指令多数据（SIMD）指令的处理器中的浮点异常的方法和装置。在一个实施例中，识别用于SIMD浮点运算的数字异常，并启动SIMD微操作以产生用于SIMD浮点运算的打包结果的两个打包部分结果。启动SIMD非规范化微操作以组合两个打包的部分结果并且对组合的打包部分结果的一个或多个元素进行非规范化，以生成具有一个或多个异常元素的SIMD浮点运算的打包结果。标志被设置和存储与打包部分结果以识别异常元素。在一个实施例中，当SIMD标准化微操作在使用乘法时在SIMD浮点运算之前产生归一化的伪内部浮点表示。

5. 发明申请

US20140188967A1 Leading Change Anticipator Logic 有权
标题翻译：领先的变革预期逻辑
公开(公告)号：US20140188967A1
公开(公告)日：2014-07-03
申请号：US13729421
申请日：2012-12-28
申请人： Simon Rubanovich , Thierry Pons , Amit Gradstein , Zeev Sperber
发明人： Simon Rubanovich , Thierry Pons , Amit Gradstein , Zeev Sperber
IPC分类号： G06F17/10
CPC分类号： G06F7/74 , G06F5/012 , G06F7/485
摘要： In one embodiment, a processor includes at least one floating point unit. The at least one floating point unit may include an adder, leading change anticipator (LCA) logic, and a shifter. The adder may be to add a first operand X and a second operand Y to obtain an output operand having a bit length n. The LCA logic may be to: for each bit position i from n−1 to 1, obtain a set of propagation values and a set of bit values based on the first operand X and the second operand Y; and generate a LCA mask based on the set of propagation values and the set of bit values. The shifter may be to normalize the output operand based on the LCA mask. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括至少一个浮点单元。所述至少一个浮点单元可以包括加法器，引导改变预测器（LCA）逻辑和移位器。加法器可以添加第一操作数X和第二操作数Y以获得具有位长度n的输出操作数。 LCA逻辑可以是：对于从n-1到1的每个比特位置i，基于第一操作数X和第二操作数Y获得一组传播值和一组比特值; 并且基于传播值集合和位值集合来生成LCA掩码。移位器可以是基于LCA掩码来规范化输出操作数。描述和要求保护其他实施例。

6. 发明申请

US20140379773A1 FUSED MULTIPLY ADD OPERATIONS USING BIT MASKS 有权
标题翻译：使用位掩码的多功能加密操作
公开(公告)号：US20140379773A1
公开(公告)日：2014-12-25
申请号：US13926175
申请日：2013-06-25
申请人： Simon Rubanovich , Thierry Pons , Amit Gradstein , Zeev Sperber
发明人： Simon Rubanovich , Thierry Pons , Amit Gradstein , Zeev Sperber
IPC分类号： G06F7/483 , G06F7/485 , G06F7/487
CPC分类号： G06F7/483 , G06F7/5443 , G06F7/764
摘要： Systems and methods of performing a fused multiply add (FMA) operations are provided. In one embodiment, the length of the adder used by the FMA operation is less than 3*N, where N is the number of bits in the mantissa term of a floating point number. A mask may be used to perform the addition portion of the FMA operation using the adder. A second mask may be used to denormalize the result of the addition portion of the FMA operation if an underflow occurs.
摘要翻译：提供了执行融合乘法（FMA）操作的系统和方法。在一个实施例中，由FMA操作使用的加法器的长度小于3 * N，其中N是浮点数的尾数项中的位数。可以使用掩码来使用加法器来执行FMA操作的相加部分。如果发生下溢，则可以使用第二掩模来对FMA操作的添加部分的结果进行非规范化。

7. 发明授权

US09542154B2 Fused multiply add operations using bit masks 有权
标题翻译：融合乘法使用位掩码添加操作
公开(公告)号：US09542154B2
公开(公告)日：2017-01-10
申请号：US13926175
申请日：2013-06-25
申请人： Simon Rubanovich , Thierry Pons , Amit Gradstein , Zeev Sperber
发明人： Simon Rubanovich , Thierry Pons , Amit Gradstein , Zeev Sperber
IPC分类号： G06F7/483 , G06F7/544 , G06F7/76
CPC分类号： G06F7/483 , G06F7/5443 , G06F7/764
摘要： Systems and methods of performing a fused multiply add (FMA) operations are provided. In one embodiment, the length of the adder used by the FMA operation is less than 3*N, where N is the number of bits in the mantissa term of a floating point number. A mask may be used to perform the addition portion of the FMA operation using the adder. A second mask may be used to denormalize the result of the addition portion of the FMA operation if an underflow occurs.
摘要翻译：提供了执行融合乘法（FMA）操作的系统和方法。在一个实施例中，由FMA操作使用的加法器的长度小于3 * N，其中N是浮点数的尾数项中的位数。可以使用掩码来使用加法器来执行FMA操作的相加部分。如果发生下溢，则可以使用第二掩模来对FMA操作的添加部分的结果进行非规范化。

8. 发明授权

US09619226B2 Systems, apparatuses, and methods for performing a horizontal add or subtract in response to a single instruction 有权
公开(公告)号：US09619226B2
公开(公告)日：2017-04-11
申请号：US13992230
申请日：2011-12-23
申请人： Mostafa Hagog , Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Amit Gradstein , Simon Rubanovich , Zeev Sperber
发明人： Mostafa Hagog , Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Amit Gradstein , Simon Rubanovich , Zeev Sperber
IPC分类号： G06F9/302 , G06F9/305 , G06F15/76 , G06F9/30 , G06F15/80
CPC分类号： G06F9/30036 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30029 , G06F9/30167 , G06F9/30185 , G06F15/8053 , G06F2207/5442
摘要： Embodiments of systems, apparatuses, and methods for performing in a computer processor vector packed horizontal add or subtract of packed data elements in response to a single vector packed horizontal add or subtract instruction that includes a destination vector register operand, a source vector register operand, and an opcode are describes.

9. 发明授权

US09513918B2 Apparatus and method for performing permute operations 有权
标题翻译：用于执行置换操作的装置和方法
公开(公告)号：US09513918B2
公开(公告)日：2016-12-06
申请号：US13995974
申请日：2011-12-22
申请人： Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Mostafa Hagog , Jesus Corbal , Bret L Toll , Mark J Charney , Tal Uliel , Zeev Sperber , Amit Gradstein
发明人： Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Mostafa Hagog , Jesus Corbal , Bret L Toll , Mark J Charney , Tal Uliel , Zeev Sperber , Amit Gradstein
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30196 , G06F9/30032 , G06F9/30036 , G06F9/30145 , G06F9/3867
摘要： An apparatus and method are described for permuting data elements with masking. For example, a method according to one embodiment includes the following operations: reading values from a mask data structure to determine whether masking is implemented for each data element of a destination operand; if masking not implemented for a particular data element, then selecting data elements from a first source operand and a second source operand based on index values stored in destination operand to be copied to data element positions within the destination operand, wherein any one of the data elements from either the first source operand and the second source operand may be copied to any one of the data element positions within the destination operand; and if masking is implemented for a particular data element of the destination operand, then performing a designated masking operation with respect to that particular data element.
摘要翻译：描述了用掩模来置换数据元素的装置和方法。例如，根据一个实施例的方法包括以下操作：从掩模数据结构读取值以确定是否对目的地操作数的每个数据元素实施掩蔽; 如果对于特定数据元素没有被实现掩蔽，则基于存储在目的地操作数中的索引值从第一源操作数和第二源操作数中选择数据元素以被复制到目的地操作数中的数据元素位置，其中数据中的任何一个可以将来自第一源操作数和第二源操作数的元素复制到目的地操作数中的任何一个数据元素位置; 并且如果针对目的地操作数的特定数据元素实现掩蔽，则对该特定数据元素执行指定的掩蔽操作。

10. 发明申请

US20150026439A1 APPARATUS AND METHOD FOR PERFORMING PERMUTE OPERATIONS 有权
标题翻译：用于执行操作的装置和方法
公开(公告)号：US20150026439A1
公开(公告)日：2015-01-22
申请号：US13995974
申请日：2011-12-22
申请人： Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Mostafa Hagog , Jesus Corbal , Bret L. Toll , Mark J. Charney , Tal Uliel , Zeev Sperber , Amit Gradstein
发明人： Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Mostafa Hagog , Jesus Corbal , Bret L. Toll , Mark J. Charney , Tal Uliel , Zeev Sperber , Amit Gradstein
IPC分类号： G06F9/30
CPC分类号： G06F9/30196 , G06F9/30032 , G06F9/30036 , G06F9/30145 , G06F9/3867
摘要： An apparatus and method are described for permuting data elements with masking. For example, a method according to one embodiment includes the following operations: reading values from a mask data structure to determine whether masking is implemented for each data element of a destination operand; if masking not implemented for a particular data element, then selecting data elements from a first source operand and a second source operand based on index values stored in destination operand to be copied to data element positions within the destination operand, wherein any one of the data elements from either the first source operand and the second source operand may be copied to any one of the data element positions within the destination operand; and if masking is implemented for a particular data element of the destination operand, then performing a designated masking operation with respect to that particular data element.
摘要翻译：描述了用掩模来置换数据元素的装置和方法。例如，根据一个实施例的方法包括以下操作：从掩模数据结构读取值以确定是否对目的地操作数的每个数据元素实施掩蔽; 如果对于特定数据元素没有被实现掩蔽，则基于存储在目的地操作数中的索引值从第一源操作数和第二源操作数中选择数据元素以被复制到目的地操作数中的数据元素位置，其中数据中的任何一个可以将来自第一源操作数和第二源操作数的元素复制到目的地操作数中的任何一个数据元素位置; 并且如果针对目的地操作数的特定数据元素实现掩蔽，则对该特定数据元素执行指定的掩蔽操作。

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