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1. 发明申请

US20050188289A1 METHOD FOR SYSTEM PERFORMANCE TESTING AND SELF CORRECTING ACTION 有权
标题翻译：用于系统性能测试和自校正操作的方法
公开(公告)号：US20050188289A1
公开(公告)日：2005-08-25
申请号：US10708316
申请日：2004-02-24
申请人： Zachary Berndlmaier , Stephen Geissler , William Tonti
发明人： Zachary Berndlmaier , Stephen Geissler , William Tonti
IPC分类号： G01R31/28 , G01R31/317
CPC分类号： G01R31/31718 , G01R31/31707
摘要： Disclosed is a method and apparatus for autonomously self-monitoring and self-adjusting the operation of an integrated circuit device throughout the integrated circuit device's useful life. The invention periodically performs performance self-testing on the integrated circuit device throughout the integrated circuit devices useful life. The invention also evaluates whether results from the self-testing are within acceptable limits and self-adjusts parameters of the integrated circuit device until the results from the self-testing are within the acceptable limits.
摘要翻译：公开了一种在整个集成电路器件的使用寿命内自主地自我监测和自调整集成电路器件的操作的方法和装置。本发明在整个集成电路器件的使用寿命中定期对集成电路器件进行性能自检。本发明还评估自测试的结果是否在可接受的限度内，并且自调整集成电路器件的参数，直到自测试的结果在可接受的限度内。

2. 发明申请

US20050180228A1 METHOD AND CIRCUIT FOR DYNAMIC READ MARGIN CONTROL OF A MEMORY ARRAY 失效
标题翻译：用于动态读取记忆阵列控制的方法和电路
公开(公告)号：US20050180228A1
公开(公告)日：2005-08-18
申请号：US10708236
申请日：2004-02-18
申请人： Miles Canada , Stephen Geissler , Robert Houle , Dongho Lee , Vinod Ramadurai , Mathew Ringler , Gerard Salem , Timothy Vonreyn
发明人： Miles Canada , Stephen Geissler , Robert Houle , Dongho Lee , Vinod Ramadurai , Mathew Ringler , Gerard Salem , Timothy Vonreyn
IPC分类号： G11C7/00 , G11C7/08 , G11C7/10
CPC分类号： G11C7/08 , G11C7/1045 , G11C2207/065 , G11C2207/2254
摘要： A method and circuit for adjusting the read margin of a self-timed memory array. The electronic circuit, including: a memory cell array including a sense amplifier self-timed decode circuit adapted to set a base read time delay of the memory cell array; and a read delay adjustment circuit coupled to the memory cell array, the read delay adjustment circuit adapted to adjust the base read time delay of the memory array based on an operating frequency of the memory cell array.
摘要翻译：一种用于调整自定时存储器阵列的读取余量的方法和电路。该电子电路包括：存储单元阵列，包括适于设置存储单元阵列的基本读时间延迟的读出放大器自定时解码电路; 以及耦合到所述存储单元阵列的读延迟调整电路，所述读延迟调整电路适于基于所述存储单元阵列的工作频率来调整所述存储器阵列的基本读时间延迟。

3. 发明申请

US20050046469A1 LOW VOLTAGE CURRENT REFERENCE CIRCUITS 失效
标题翻译：低电压电流参考电路
公开(公告)号：US20050046469A1
公开(公告)日：2005-03-03
申请号：US10604910
申请日：2003-08-26
申请人： Stephen Geissler
发明人： Stephen Geissler
IPC分类号： H03F3/345 , H03K3/01
CPC分类号： H03F3/345
摘要： In a first aspect, a first current reference circuit is provided that includes (1) a first n-channel field effect transistor (NFET) having a gate and a drain that are coupled together; and (2) a second NFET having a floating body. In a second aspect, a second current reference circuit is provided that includes (1) a first n-channel field effect transistor (NFET) having a gate and a drain that are coupled together; and (2) a second NFET having a floating body. In the second current reference circuit, the first and second NFETs are configured so as to generate a reference current at a supply voltage of not more than about 0.5 volts. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了第一电流参考电路，其包括（1）具有耦合在一起的栅极和漏极的第一n沟道场效应晶体管（NFET）和（2）具有浮体的第二NFET。在第二方面中，提供了第二电流参考电路，其包括：（1）具有耦合在一起的栅极和漏极的第一n沟道场效应晶体管（NFET）和（2）具有浮体的第二NFET。在第二电流参考电路中，第一和第二NFET被配置为在不大于约0.5伏特的电源电压下产生参考电流。提供了许多其他方面。

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