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1. 发明授权

US06400231B1 Numerically controlled variable oscillator 有权
标题翻译：数控可变振荡器
公开(公告)号：US06400231B1
公开(公告)日：2002-06-04
申请号：US09642481
申请日：2000-08-18
申请人： Yves Leduc , Pascal Guignon , Pierre Carbou
发明人： Yves Leduc , Pascal Guignon , Pierre Carbou
IPC分类号： H03B500
CPC分类号： H03K3/0307 , H03B5/366 , H03J2200/10
摘要： An oscillator includes a resonator, such as a crystal (12) coupled to first and second capacitor banks (14). The first and second capacitor banks (14) each comprise a plurality of capacitors (16) coupled to the resonator (12) through respective switching devices (18) that may be selectively enabled. The switches (18) are selectively enabled to couple a desired set of said capacitors (16) to said resonator (12). At least one of the switches (18sd) is controlled with a clock signal having a programmable duty cycle from a sigma-delta modulator (20) to enable at least one of said capacitors (16sd) during a first phase of the clock signal and disable that capacitor (16sd) during a second phase of the clock signal.
摘要翻译：振荡器包括谐振器，例如耦合到第一和第二电容器组（14）的晶体（12）。第一和第二电容器组（14）各自包括通过可以选择性地使能的各个开关装置（18）耦合到谐振器（12）的多个电容器（16）。选择性地使开关（18）能够将期望的所述电容器组（16）耦合到所述谐振器（12）。至少一个开关（18sd）由具有来自Σ-Δ调制器（20）的可编程占空比的时钟信号控制，以在时钟信号的第一阶段期间使能至少一个所述电容器（16sd），并且使能该电容器（16sd）在时钟信号的第二阶段期间。

2. 发明授权

US6160507A Current bit cell and switched current network formed of such cells 有权
标题翻译：当前位单元和交换电流网络由这样的单元组成
公开(公告)号：US6160507A
公开(公告)日：2000-12-12
申请号：US189073
申请日：1998-11-09
申请人： Pierre Carbou , Pascal Guignon
发明人： Pierre Carbou , Pascal Guignon
IPC分类号： H03K17/041 , H03M1/68 , H03M1/74 , H03M1/66
CPC分类号： H03K17/04106 , H03M1/685 , H03M1/747
摘要： Current bit cell having a current source (P1), a transistor (P6) for detecting the presence of a digital signal bit (Bit) and a plurality of transistors (P2, P5, P7) for detecting at least one command signal (L, Lc) so as to command, on a first output (S1) of the cell, the appearance of a current delivered by the current source (P1) as a function of the digital signal (Bit) applied to the cell and of the at least one command signal (L, Lc), a transistor (P9) for detecting the presence of a bit (Bitz) complementary to the bit of the digital signal (Bit) and a plurality of transistors (P3, P4, P8) for detecting the complement (Lz, Lcz) of the at least one command signal (L, Lc), so as to command on a second output (S2) of the cell the appearance of a current delivered by the current source (P1) which is the complement of the current delivered on the first output (S1), the transistors for detecting the presence of bits and of the at least one command signal, the transistors for detecting the presence of complementary bits and of complementary command signals and the current source being embodied with the aid of field-effect transistors of the same type.
摘要翻译：具有电流源（P1）的当前位单元，用于检测数字信号位（Bit）的存在的晶体管（P6）和用于检测至少一个指令信号（L，...）的多个晶体管（P2，P5，P7） Lc），以便在单元的第一输出（S1）上命令由电流源（P1）传送的电流的外观作为应用于单元的数字信号（Bit）和至少一个指令信号（L，Lc），用于检测与数字信号（Bit）的位互补的位（Bitz）的存在的晶体管（P9）和用于检测数字信号的位的多个晶体管（P3，P4，P8）所述至少一个命令信号（L，Lc）的补码（Lz，Lcz），以便在所述单元的第二输出（S2）上命令出现由当前源（P1）作为补码在第一输出（S1）上传送的电流，用于检测位的存在和至少一个命令信号的晶体管，用于检测的晶体管存在互补位和互补指令信号，并且电流源借助于相同类型的场效应晶体管而被实现。

3. 发明授权

US5610546A Controlled delay circuit 失效
标题翻译：受控延时电路
公开(公告)号：US5610546A
公开(公告)日：1997-03-11
申请号：US164606
申请日：1993-12-09
申请人： Pierre Carbou , Pascal Guignon , Philippe Perney
发明人： Pierre Carbou , Pascal Guignon , Philippe Perney
IPC分类号： H03K3/017 , H03K3/353 , H03K5/04 , H03K5/13 , H03K5/151 , H03K17/687 , H03H11/26
CPC分类号： H03K5/133 , H03K5/04 , H03K5/1515
摘要： Delay circuit comprising a delay cell formed by a current source (I) connected between drain and source of two field-effect transistors (PO, NO) whose gates are connected to each other in order to constitute the input of the cell, and an inverter (INV) linked to one or other of the terminals of the current source (I) according to whether the delay is to affect the leading edge or the trailing edge of the signal to be delayed, a capacitor (C) for defining a delay time (Te) proportional to the power supply voltage and inversely proportional to the current (I) delivered by the current source, being connected between the input of the inverter (INV) and earth, characterized in that it furthermore comprises a circuit (Ci, Cu, S1, S3, AMPLO, P1) for regulating the current delivered by the current source in order to make it proportional to the power supply voltage of the circuit.
摘要翻译：延迟电路包括由连接在两个场效应晶体管（PO，NO）的漏极和源极之间的电流源（I）形成的延迟单元，其栅极彼此连接以构成单元的输入，以及反相器（INV）根据延迟是否影响待延迟的信号的前沿或后沿，连接到电流源（I）的一个或另一个终端;电容器（C），用于定义延迟时间（Te）与电源电压成比例并且与由电流源传递的电流（I）成反比，其连接在逆变器（INV）的输入端和地之间，其特征在于，它还包括电路（Ci，Cu ，S1，S3，AMPLO，P1），用于调节由电流源传递的电流，以使其与电路的电源电压成比例。

4. 发明授权

US5438291A Controlled delay digital clock signal generator 失效
标题翻译：受控延时数字时钟信号发生器
公开(公告)号：US5438291A
公开(公告)日：1995-08-01
申请号：US168707
申请日：1993-12-16
申请人： Pierre Carbou , Pascal Guignon
发明人： Pierre Carbou , Pascal Guignon
IPC分类号： H03K5/08 , H03K5/12
CPC分类号： H03K5/082
摘要： Controlled delay digital clock signal generator, characterised in that it comprises means (I5, I6, I7, I8, I9, I10, IT7, IT8, IT9, IT10, C4) to generate from a clock signal (CK) and its complementary signal (CKB) a ramp signal comprising at least two segments of positive slope and at least two segments of negative slope, means (I1, I2, IT1, IT2, IT3, C2, CET1T2, AMPLI, I3, I4, IT4, IT5, IT6, C3, CET3T4, AMPL2) for separate control of the slopes of the said segments, means with trigger circuits (AMPLO) for converting the ramp signal (RAMP) into a square signal (CKQ) means (NO0, A0, A1, NO1) for achieving the logic combinations of the delayed square clock signal (CKQ) resulting from the conversion with the clock signal (CK) and the clock complementary clock signal (CKB) of the said clock signal to obtain as many delayed digital clock signals as the ramp signal has segments of different slopes.
摘要翻译：受控延迟数字时钟信号发生器，其特征在于它包括从时钟信号（CK）及其互补信号（CK）产生的装置（I5，I6，I7，I8，I9，I10，IT7，IT8，IT9，IT10，C4） CKB）包括至少两个正斜率段和至少两个负斜率段的斜坡信号，所述装置（I1，I2，IT1，IT2，IT3，C2，CET1T2，AMPLI，I3，I4，IT4，IT5，IT6， C3，CET3T4，AMPL2），用于单独控制所述段的斜率的装置，具有用于将斜坡信号（RAMP）转换成方波信号（CKQ）装置（NO0，A0，A1，NO1）的触发电路（AMPLO）实现由时钟信号（CK）的转换和所述时钟信号的时钟互补时钟信号（CKB）产生的延迟平方时信号（CKQ）的逻辑组合，以获得与斜坡信号相同的延迟的数字时钟信号有不同坡度的段。

5. 发明授权

US07633339B2 Differential amplifier 有权
标题翻译：差分放大器
公开(公告)号：US07633339B2
公开(公告)日：2009-12-15
申请号：US11947065
申请日：2007-11-29
申请人： Christian V. Sorace , Xavier Albinet , Pierre Carbou
发明人： Christian V. Sorace , Xavier Albinet , Pierre Carbou
IPC分类号： H03F3/217
CPC分类号： H03F3/217
摘要： An amplifier comprising an analog amplifier which outputs a first current and a second current. The amplifier also comprises a first digital amplifier coupled to the analog amplifier, the first digital amplifier amplifies a modified version of the first current to produce a third current. The amplifier also comprises a second digital amplifier coupled to the analog amplifier, the second digital amplifier amplifies a modified version of the second current to produce a fourth current. The amplifier also includes connections configured to provide the first, second, third and fourth currents through a load.
摘要翻译：一种放大器，包括输出第一电流和第二电流的模拟放大器。放大器还包括耦合到模拟放大器的第一数字放大器，第一数字放大器放大第一电流的修改版本以产生第三电流。放大器还包括耦合到模拟放大器的第二数字放大器，第二数字放大器放大第二电流的修改版本以产生第四电流。放大器还包括被配置成通过负载提供第一，第二，第三和第四电流的连接。

6. 发明申请

US20050062457A1 Battery charger interface architecture suitable for digital process 审中-公开
标题翻译：电池充电器接口架构适合数字化处理
公开(公告)号：US20050062457A1
公开(公告)日：2005-03-24
申请号：US10665928
申请日：2003-09-18
申请人： Fabrice Galant , Pierre Carbou , Philipe Perney
发明人： Fabrice Galant , Pierre Carbou , Philipe Perney
IPC分类号： H02J7/00
CPC分类号： H02J7/0072 , H02J7/0093
摘要： The present application describes a battery charger interface architecture suitable for digital applications. According to some embodiment, the parameters of a battery are measured and converted into a digital data stream using various analog-to-digital conversion techniques. The digital data stream is compared with a predetermined digital reference to control a duty cycle of a PWM sequence according to a functional mode of the battery charger interface. If the battery charger provides a controlled current output, then the battery charger interface architecture operates in a pulse mode controlling the duty cycle of the battery charger current. If the battery charger does not provide a controlled current output, then the battery charger interface architecture operates in a linear mode controlling the charging current of the battery charger.
摘要翻译：本申请描述了适用于数字应用的电池充电器接口架构。根据一些实施例，使用各种模数转换技术来测量电池的参数并将其转换成数字数据流。将数字数据流与预定的数字参考值进行比较，以根据电池充电器接口的功能模式来控制PWM序列的占空比。如果电池充电器提供受控的电流输出，则电池充电器接口架构以脉冲模式操作，控制电池充电器电流的占空比。如果电池充电器不提供受控的电流输出，则电池充电器接口架构以线性模式操作来控制电池充电器的充电电流。

7. 发明申请

US20070229042A1 SYSTEMS AND METHODS FOR DRIVING LIGHT EMITTING DIODES 有权
标题翻译：用于驱动发光二极管的系统和方法
公开(公告)号：US20070229042A1
公开(公告)日：2007-10-04
申请号：US11560906
申请日：2006-11-17
申请人： Paolo Cusinato , Pierre Carbou , Philippe Perney
发明人： Paolo Cusinato , Pierre Carbou , Philippe Perney
IPC分类号： G05F1/577
CPC分类号： H05B33/0845 , H05B33/0815 , H05B33/0818 , H05B33/0827 , Y02B20/347
摘要： The present disclosure describes systems and methods for driving light emitting diodes (LEDs). At least some embodiments include an LED driver system that includes a power supply, a plurality of current sources (each current source coupled between a common return resistor and one of a plurality of branches of series coupled LEDs, and each branch coupled between a corresponding current source and the power supply), and control logic coupled to the current sources (the control logic capable of controlling the current flow through each current source). Each of the current sources allows current to flow during one of a plurality of substantially non-overlapping time periods within a repeating time interval, each current source allowing current to flow during a different time period. The magnitude of the current flowing through each current source is substantially the same and is regulated based upon a feedback voltage across the common return resistor.
摘要翻译：本公开描述了用于驱动发光二极管（LED）的系统和方法。至少一些实施例包括LED驱动器系统，其包括电源，多个电流源（每个电流源耦合在公共返回电阻器和串联耦合的LED的多个分支中的一个之间，并且每个分支耦合在相应的电流源和电源）以及耦合到电流源（控制逻辑能够控制通过每个电流源的电流）的控制逻辑。每个电流源允许电流在重复时间间隔内的多个基本上不重叠的时间段中的一个期间流动，每个电流源允许电流在不同时间段期间流动。流过每个电流源的电流的大小基本相同，并且基于公共返回电阻器上的反馈电压来调节。

8. 发明授权

US5216380A Performance operational amplifier and method of amplification 失效
标题翻译：性能运算放大器和放大方法
公开(公告)号：US5216380A
公开(公告)日：1993-06-01
申请号：US769906
申请日：1991-10-01
申请人： Pierre Carbou
发明人： Pierre Carbou
IPC分类号： H03F3/30 , H03F3/45
CPC分类号： H03F3/3062 , H03F3/3023 , H03F3/45192 , H03F3/45475 , H03F3/45659 , H03F3/45946 , H03F2200/153 , H03F2203/45471
摘要： An operational amplifier (10) is provided which includes a differential input stage (18) for receiving differential signals. A differential loop (30, 64), (86) amplifies said differential signals. The amplified differential signals are output on a pair differential output terminals (80, 84). A common mode loop (54), (30, 64) maintains the mean voltage of the amplified differential signals at a preselected value.

9. 发明授权

US07840239B2 Distributed power management 有权
标题翻译：分布式电源管理
公开(公告)号：US07840239B2
公开(公告)日：2010-11-23
申请号：US11744188
申请日：2007-05-03
申请人： Lorenzo Indiani , Jean-Christophe Jiguet , Pierre Carbou , Philippe Perney
发明人： Lorenzo Indiani , Jean-Christophe Jiguet , Pierre Carbou , Philippe Perney
IPC分类号： H04B1/38 , H04B1/16 , H04B1/06
CPC分类号： G06F1/3203 , G06F1/3287 , Y02D10/171 , Y02D50/20
摘要： A power management bus for controlling power over multiple device subsystems includes a master power bus controller which transmits power management information to control one or more power resources through a transmit interface. The transmitted information is received at one or more receive interfaces. A broadcast message can be transmitted to control multiple power resources by subsystem, resource group and resource type. A single address message can be transmitted to control a single power resource. A power down can be initiated at any of the receive interfaces.
摘要翻译：用于控制多个设备子系统的电力的电源管理总线包括主电源总线控制器，其通过发送接口传输电力管理信息以控制一个或多个电力资源。所发送的信息在一个或多个接收接口处被接收。可以传输广播消息，以通过子系统，资源组和资源类型来控制多个电力资源。可以传输单个地址消息来控制单个电源。可以在任何接收接口上启动掉电。

10. 发明申请

US20080276110A1 DISTRIBUTED POWER MANAGEMENT 有权
标题翻译：分布式电源管理
公开(公告)号：US20080276110A1
公开(公告)日：2008-11-06
申请号：US11744188
申请日：2007-05-03
申请人： Lorenzo Indiani , Jean-Christophe Jiguet , Pierre Carbou , Philippe Perney
发明人： Lorenzo Indiani , Jean-Christophe Jiguet , Pierre Carbou , Philippe Perney
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F1/3287 , Y02D10/171 , Y02D50/20
摘要： A power management bus for controlling power over multiple device subsystems includes a master power bus controller which transmits power management information to control one or more power resources through a transmit interface. The transmitted information is received at one or more receive interfaces. A broadcast message can be transmitted to control multiple power resources by subsystem, resource group and resource type. A single address message can be transmitted to control a single power resource. A power down can be initiated at any of the receive interfaces.
摘要翻译：用于控制多个设备子系统的电力的电源管理总线包括主电源总线控制器，其通过发送接口传输电力管理信息以控制一个或多个电力资源。所发送的信息在一个或多个接收接口处被接收。可以传输广播消息，以通过子系统，资源组和资源类型来控制多个电力资源。可以传输单个地址消息来控制单个电源。可以在任何接收接口上启动掉电。

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