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1. 发明授权

US07983858B2 Fault test apparatus and method for testing semiconductor device under test using fault excitation function 有权
标题翻译：使用故障激励功能测试半导体器件的故障测试装置和方法
公开(公告)号：US07983858B2
公开(公告)日：2011-07-19
申请号：US12222992
申请日：2008-08-21
申请人： Yuzo Takamatsu , Hiroshi Takahashi , Yoshinobu Higami , Michinobu Nakao , Takashi Aikyo , Michiaki Emori , Hideo Ohmae
发明人： Yuzo Takamatsu , Hiroshi Takahashi , Yoshinobu Higami , Michinobu Nakao , Takashi Aikyo , Michiaki Emori , Hideo Ohmae
IPC分类号： G06F19/00
CPC分类号： G01R31/3193
摘要： A fault test apparatus for testing a fault on each signal line in a circuit under test including signal lines includes a controller, which calculates a value of a fault excitation function for a fault signal line, using the fault excitation function representing a fitness result of a predetermined fault excitation condition between the fault signal line having a fault among the signal lines under test in the circuit under test and at least one of adjacent signal lines adjacent to the fault signal line and falling within a predetermined range from the fault signal line, based on layout information between the fault signal line and at least one adjacent signal line adjacent to the fault signal line, manufacturing parameter information, and timing information, and then, determines whether or not a dynamic fault is excited on the fault signal line based on the value of the fault excitation function.
摘要翻译：用于测试包括信号线在内的被测电路中的每个信号线上的故障的故障测试装置包括一个控制器，该控制器使用表示一个适应度结果的故障激励函数来计算故障信号线的故障激励函数的值基于被测电路的被测试信号线之间的故障的故障信号线与与故障信号线相邻的相邻信号线中的至少一个与故障信号线相关的预定范围内的预定故障激励条件在故障信号线与与故障信号线相邻的至少一个相邻信号线之间的布局信息，制造参数信息和定时信息上，然后基于该故障信号线确定动态故障是否在故障信号线上被激励故障励磁功能的值。

2. 发明申请

US20090063062A1 Fault test apparatus and method for testing semiconductor device under test using fault excitation function 有权
标题翻译：使用故障激励功能测试半导体器件的故障测试装置和方法
公开(公告)号：US20090063062A1
公开(公告)日：2009-03-05
申请号：US12222992
申请日：2008-08-21
申请人： Yuzo Takamatsu , Hiroshi Takahashi , Yoshinobu Higami , Michinobu Nakao , Takashi Aikyo , Michiaki Emori , Hideo Ohmae
发明人： Yuzo Takamatsu , Hiroshi Takahashi , Yoshinobu Higami , Michinobu Nakao , Takashi Aikyo , Michiaki Emori , Hideo Ohmae
IPC分类号： G01R31/28
CPC分类号： G01R31/3193
摘要： A fault test apparatus for testing a fault on each signal line in a circuit under test including signal lines includes a controller, which calculates a value of a fault excitation function for a fault signal line, using the fault excitation function representing a fitness result of a predetermined fault excitation condition between the fault signal line having a fault among the signal lines under test in the circuit under test and at least one of adjacent signal lines adjacent to the fault signal line and falling within a predetermined range from the fault signal line, based on layout information between the fault signal line and at least one adjacent signal line adjacent to the fault signal line, manufacturing parameter information, and timing information, and then, determines whether or not a dynamic fault is excited on the fault signal line based on the value of the fault excitation function.
摘要翻译：用于测试包括信号线在内的被测电路中的每个信号线上的故障的故障测试装置包括一个控制器，该控制器使用表示一个适应度结果的故障激励函数来计算故障信号线的故障激励函数的值基于被测电路的被测试信号线之间的故障的故障信号线与与故障信号线相邻的相邻信号线中的至少一个与故障信号线相关的预定范围内的预定故障激励条件在故障信号线与与故障信号线相邻的至少一个相邻信号线之间的布局信息，制造参数信息和定时信息上，然后基于该故障信号线确定动态故障是否在故障信号线上被激励故障励磁功能的值。

3. 发明授权

US5414866A One-chip microcomputer with parallel operating load and unload data buses 失效
标题翻译：具有并行运行负载和卸载数据总线的单片机
公开(公告)号：US5414866A
公开(公告)日：1995-05-09
申请号：US783906
申请日：1991-10-29
申请人： Hideo Ohmae
发明人： Hideo Ohmae
IPC分类号： G06F13/42 , G06F15/78 , G06F13/40
CPC分类号： G06F13/4213 , G06F15/7814
摘要： A one-chip microcomputer is equipped with a two-data-bus system, a first and a second data bus, so that data is transferred from an internal register to one bus and different data from RAM or an I/O buffer to the other. The internal register and RAM or the I/O buffer are induced to transfer different data simultaneously to different buses in the same machine cycle at the same timing, respectively. As data exist on different buses, the data on the respective buses can be loaded simultaneously by the internal register and RAM or the I/O buffer at the same timing. As a result, transfer of data to the buses from the internal register and RAM or the I/O buffer can be implemented simultaneously at a given timing within one machine cycle. At the same time, data can be loaded simultaneously from the buses to the internal register and RAM or the I/O buffer at a given different timing.
摘要翻译：单片机配备有双数据总线系统，第一和第二数据总线，使得数据从内部寄存器传输到一个总线，并将不同数据从RAM或I / O缓冲器传输到另一个总线。引导内部寄存器和RAM或I / O缓冲器分别在相同的时间在相同的机器周期中将不同的数据同时传输到不同的总线。由于数据存在于不同的总线上，各个总线上的数据可以通过内部寄存器和RAM或I / O缓冲器同时加载。因此，可以在一个机器周期内的给定时刻同时实现从内部寄存器和RAM或I / O缓冲器向总线传送数据。同时，数据可以在给定的不同时间从总线同时加载到内部寄存器和RAM或I / O缓冲器。

4. 发明授权

US5237698A Microcomputer 失效
标题翻译：微电脑
公开(公告)号：US5237698A
公开(公告)日：1993-08-17
申请号：US802041
申请日：1991-12-03
申请人： Hideo Ohmae
发明人： Hideo Ohmae
IPC分类号： G06F1/24 , G06F1/32
CPC分类号： G06F1/32 , G06F1/24
摘要： A microcomputer that comprises a standby signal generating circuit for supplying a standby signal to a processor and an initial reset circuit for supplying an initial reset signal to the processor when supply voltage becomes lower than a predetermined value, wherein the standby signal is produced in either case where a standby condition is sustained or imposed to switch the processor from an operation mode to a standby mode so that the supply voltage may be lowered during the standby mode, is characterized by the provision of a blocking circuit for blocking the entrance of the initial reset signal into the processor according to the standby signal thus produced.
摘要翻译：一种微型计算机，包括用于向处理器提供备用信号的待机信号发生电路和用于在电源电压变得低于预定值时向处理器提供初始复位信号的初始复位电路，其中在任一情况下产生待机信号其中持续或施加待机状态以将处理器从操作模式切换到待机模式，使得在待机模式期间电源电压可能降低，其特征在于提供阻塞电路以阻止初始复位的进入根据如此产生的待机信号将信号传送到处理器中。

5. 发明授权

US09314496B2 Insoluble dietary fiber-containing product derived from grain seeds 有权
标题翻译：不溶性膳食纤维来源于粮食种子的产品
公开(公告)号：US09314496B2
公开(公告)日：2016-04-19
申请号：US12809191
申请日：2008-12-19
申请人： Hideo Ohmae , Hiroshi Murayama , Naohiro Takimoto , Yuji Sakamoto , Osamu Kanauchi , Mikio Katayama , Hiroyuki Watanabe , Yuta Komano
发明人： Hideo Ohmae , Hiroshi Murayama , Naohiro Takimoto , Yuji Sakamoto , Osamu Kanauchi , Mikio Katayama , Hiroyuki Watanabe , Yuta Komano
IPC分类号： A61K35/00 , A61K36/899 , A23L1/10 , A23L1/105 , A23L1/308 , C12P19/04 , C12P19/14
CPC分类号： A61K36/899 , A23L7/107 , A23L7/115 , A23L33/22 , C12P19/04 , C12P19/14
摘要： This invention provides a product safe for treating, improving or preventing an inflammatory bowel disease such as ulcerative colitis, and provides a product comprising an insoluble dietary fiber obtained by enzymatic treatment of seeds of a grain plant(s) or germinated young seeds thereof, as well as a food or drink or medicament comprising the product.
摘要翻译：本发明提供一种治疗，改善或预防溃疡性结肠炎等炎症性肠病的产品安全性，并且提供包含通过酶处理种子植物或其发芽的幼苗的种子获得的不溶性膳食纤维的产品，作为以及包含该产品的食品或饮料或药物。

6. 发明授权

US06798245B2 Current mirror circuit 失效
公开(公告)号：US06798245B2
公开(公告)日：2004-09-28
申请号：US10681891
申请日：2003-10-09
申请人： Hideo Ohmae
发明人： Hideo Ohmae
IPC分类号： G05F324
CPC分类号： G05F3/262
摘要： A first input transistor of a current mirror, in which one end is connected to a first constant current source and another end is connected to a reference potential (for example, the ground), serves as a current mirror input. A second input transistor, in which one end is connected to a second constant current source, is disposed with being separated from the first input transistor by a predetermined distance. A plurality of output transistors is distributed between the first and second input transistors. The gate-source voltages of the output transistors are substantially equal to those of the first and second input transistors. Therefore, it is possible to provide to a current mirror circuit which has a large number of output transistors, an influence due to the wiring resistance of a feeder line are remarkably reduced without increasing the wiring area for forming the feeder line.

7. 发明申请

US20120141455A1 INSOLUBLE DIETARY FIBER-CONTAINING MATERIALS DERIVED FROM CEREAL SEEDS 有权
标题翻译：来自谷物种子的不含食物纤维的材料
公开(公告)号：US20120141455A1
公开(公告)日：2012-06-07
申请号：US12809191
申请日：2008-12-19
申请人： Hideo Ohmae , Hiroshi Murayama , Naohiro Takimoto , Yuji Sakamoto , Osamu Kanauchi , Mikio Katayama , Hiroyuki Watanabe , Yuta Komano
发明人： Hideo Ohmae , Hiroshi Murayama , Naohiro Takimoto , Yuji Sakamoto , Osamu Kanauchi , Mikio Katayama , Hiroyuki Watanabe , Yuta Komano
IPC分类号： A23L1/308 , A23L1/105 , A61P29/00 , A61K36/899 , A61P1/00
CPC分类号： A61K36/899 , A23L7/107 , A23L7/115 , A23L33/22 , C12P19/04 , C12P19/14
摘要： This invention provides a product safe for treating, improving or preventing an inflammatory bowel disease such as ulcerative colitis, and provides a product comprising an insoluble dietary fiber obtained by enzymatic treatment of seeds of a grain plant(s) or germinated young seeds thereof, as well as a food or drink or medicament comprising the product.
摘要翻译：本发明提供一种治疗，改善或预防溃疡性结肠炎等炎症性肠病的产品安全性，并且提供包含通过酶处理种子植物或其发芽的幼苗的种子获得的不溶性膳食纤维的产品，作为以及包含该产品的食品或饮料或药物。

8. 发明授权

US5644127A Rotary encoder and input device using the same 失效
标题翻译：旋转编码器和输入装置使用相同
公开(公告)号：US5644127A
公开(公告)日：1997-07-01
申请号：US361379
申请日：1994-12-22
申请人： Hideo Ohmae
发明人： Hideo Ohmae
IPC分类号： G01D5/245 , G01D5/244 , G01D5/36 , G06F3/033 , G06F3/038 , H03M1/24 , G01D5/34
CPC分类号： G06F3/03543 , G01D5/24476 , G01D5/2448 , G01D5/3473 , G01D5/36 , G06F3/0312
摘要： The present invention includes a light receiving unit having a first and second light receiving element which receive light emitted from a light emitting element via slits formed at a rotary disk and respectively generate detection signals whose phases differ from each other substantially by 90.degree.. A first waveform shaping circuit compares the detection signal from the first light receiving element with a reference value and generates a first detection output of a rectangular waveform. A second waveform shaping circuit compares the detection signal from the second light receiving element with the reference value and generates a second detection output of a rectangular waveform. A peak hold circuit receives the detection signal from the first light receiving element and holds the peak value thereof. A reference value generating circuit generates the reference value depending on the peak value held at the peak hold circuit.
摘要翻译：本发明包括具有第一和第二光接收元件的光接收单元，该第一和第二光接收元件通过形成在旋转盘上的狭缝接收从发光元件发射的光，并且分别产生相位彼此相差90度的检测信号。第一波形整形电路将来自第一光接收元件的检测信号与参考值进行比较，并产生矩形波形的第一检测输出。第二波形整形电路将来自第二光接收元件的检测信号与参考值进行比较，并产生矩形波形的第二检测输出。峰值保持电路从第一光接收元件接收检测信号并保持其峰值。参考值产生电路根据峰值保持电路保持的峰值产生参考值。

9. 发明授权

US5355458A Microcomputer with table address forcing for different size memories 失效
标题翻译：具有桌面地址的微型计算机强制用于不同大小的存储器
公开(公告)号：US5355458A
公开(公告)日：1994-10-11
申请号：US774312
申请日：1991-10-10
申请人： Hideo Ohmae
发明人： Hideo Ohmae
IPC分类号： G06F9/26 , G06F9/32 , G06F12/06 , G06F13/40 , G06F12/02 , G06F13/00
CPC分类号： G06F9/32 , G06F12/0653 , G06F12/0684 , G06F13/4018 , G06F9/261
摘要： A microcomputer features the provision of wiring connected to a program counter, the wiring being used for setting a bit at a particular digit position of the program counter to a logical value "0" in proportion to the storage capacity of a memory actually packaged, and when an instruction for gaining access to the rearmost storage area of the largest memory that can be packaged is executed, an address space to be accessed then is forced to be converted to the rearmost address space on the memory thus packaged on the program counter by means of the wiring, whereby data in the rearmost storage area of the memory actually packaged may be accessed with the same program. A process of producing the microcomputer comprises at least the step of setting data in a memory simultaneously with the provision of the wiring for the program counter.
摘要翻译：微型计算机具有连接到程序计数器的布线，布线用于将程序计数器的特定数位位置的位设置为与实际封装的存储器的存储容量成比例的逻辑值“0”，以及当执行用于访问最大存储器的最后存储区域的指令时，将要被访问的地址空间被强制转换到存储在程序计数器上的存储器上的最后地址空间的布线，由此可以使用相同的程序访问实际封装的存储器的最后存储区域中的数据。微型计算机的制造方法至少包括在提供程序计数器的配线的同时在存储器中设定数据的步骤。

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