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1. 发明申请

US20110180775A1 PROGRAMMABLE METALLIZATION CELL WITH ION BUFFER LAYER 有权
标题翻译：具有离子缓冲层的可编程金属化电池
公开(公告)号：US20110180775A1
公开(公告)日：2011-07-28
申请号：US12692861
申请日：2010-01-25
申请人： Yuyu LIN , Feng-Ming Lee , Yi-Chou Chen
发明人： Yuyu LIN , Feng-Ming Lee , Yi-Chou Chen
IPC分类号： H01L45/00 , H01L29/18 , H01L21/06
CPC分类号： H01L45/085 , H01L45/122 , H01L45/1233 , H01L45/1266 , H01L45/145
摘要： A programmable metallization device, comprises a first electrode; a memory layer electrically coupled to the first electrode and adapted for electrolytic formation and destruction of a conducting bridge therethrough; an ion-supplying layer containing a source of ions of a first metal element capable of diffusion into and out of the memory layer; a conductive ion buffer layer between the ion-supplying layer and the memory layer, and which allows diffusion therethrough of said ions; and a second electrode electrically coupled to the ion-supplying layer. Circuitry is coupled to the device to apply bias voltages to the first and second electrodes to induce creation and destruction of conducting bridges including the first metal element in the memory layer. The ion buffer layer can improve retention of the conducting bridge by reducing the likelihood that the first metallic element will be absorbed into the ion supplying layer.
摘要翻译：可编程金属化器件，包括第一电极; 存储层，其电耦合到所述第一电极并适于通过其导电桥的电解形成和破坏; 离子供给层，其含有能够扩散到所述存储层中的第一金属元素的离子源; 在离子供给层和存储层之间的导电离子缓冲层，并且允许所述离子的扩散; 以及电耦合到所述离子供应层的第二电极。电路耦合到器件以向第一和第二电极施加偏置电压，以引起包括存储器层中的第一金属元件的导电桥的产生和破坏。离子缓冲层可以通过降低第一金属元素被吸收到离子供给层中的可能性来改善导电桥的保留。

2. 发明授权

US08077505B2 Bipolar switching of phase change device 有权
标题翻译：相变装置的双极开关
公开(公告)号：US08077505B2
公开(公告)日：2011-12-13
申请号：US12432055
申请日：2009-04-29
申请人： Yi-Chou Chen , Yuyu Lin
发明人： Yi-Chou Chen , Yuyu Lin
IPC分类号： G11C11/00
CPC分类号： G11C13/0064 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/0073 , G11C2013/0078 , G11C2013/0092
摘要： Memory devices and methods for operating such devices are described herein. A method as described herein includes applying a reset bias arrangement to a memory cell to change the resistance state from the lower resistance state to the higher resistance state. The reset bias arrangement comprises a first voltage pulse. The method further includes applying a set bias arrangement to the memory cell to change the resistance state from the higher resistance state to the lower resistance state. The set bias arrangement comprises a second voltage pulse, the second voltage pulse having a voltage polarity different from that of the first voltage pulse.
摘要翻译：这里描述了用于操作这样的设备的存储器件和方法。本文所述的方法包括将复位偏置布置应用于存储单元，以将电阻状态从较低电阻状态改变到较高电阻状态。复位偏置装置包括第一电压脉冲。该方法还包括将设置偏置装置应用于存储单元，以将电阻状态从较高电阻状态改变到较低电阻状态。所述设定偏置装置包括第二电压脉冲，所述第二电压脉冲的电压极性与所述第一电压脉冲的极性不同。

3. 发明申请

US20090323409A1 METHODS FOR HIGH SPEED READING OPERATION OF PHASE CHANGE MEMORY AND DEVICE EMPLOYING SAME 有权
标题翻译：高速读取操作相位变化记忆的方法及其使用的装置
公开(公告)号：US20090323409A1
公开(公告)日：2009-12-31
申请号：US12466650
申请日：2009-05-15
申请人： Yuyu Lin , Yi-Chou Chen
发明人： Yuyu Lin , Yi-Chou Chen
IPC分类号： G11C11/00 , G11C11/416 , H01L47/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2013/0073 , G11C2013/0092
摘要： Phase change based memory devices and methods for operating described herein overcome the performance limitations of slow set speeds and long recovery times commonly associated with phase change memory devices, enabling high speed operation and extending their usefulness into high speed applications typically filled by DRAM and SRAM memory.
摘要翻译：基于相变的存储器件和本文描述的操作方法克服了慢设定速度和通常与相变存储器件相关联的长恢复时间的性能限制，使得能够进行高速操作并将其有用性扩展到通常由DRAM和SRAM存储器填充的高速应用。

4. 发明申请

US20090279350A1 BIPOLAR SWITCHING OF PHASE CHANGE DEVICE 有权
标题翻译：相变设备的双极开关
公开(公告)号：US20090279350A1
公开(公告)日：2009-11-12
申请号：US12432055
申请日：2009-04-29
申请人： Yi-Chou Chen , Yuyu Lin
发明人： Yi-Chou Chen , Yuyu Lin
IPC分类号： G11C11/00 , H01L47/00
CPC分类号： G11C13/0064 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/0073 , G11C2013/0078 , G11C2013/0092
摘要： Memory devices and methods for operating such devices are described herein. A method as described herein includes applying a reset bias arrangement to a memory cell to change the resistance state from the lower resistance state to the higher resistance state. The reset bias arrangement comprises a first voltage pulse. The method further includes applying a set bias arrangement to the memory cell to change the resistance state from the higher resistance state to the lower resistance state. The set bias arrangement comprises a second voltage pulse, the second voltage pulse having a voltage polarity different from that of the first voltage pulse.
摘要翻译：这里描述了用于操作这样的设备的存储器件和方法。本文所述的方法包括将复位偏置布置应用于存储单元，以将电阻状态从较低电阻状态改变到较高电阻状态。复位偏置装置包括第一电压脉冲。该方法还包括将设置偏置装置应用于存储单元，以将电阻状态从较高电阻状态改变到较低电阻状态。所述设定偏置装置包括第二电压脉冲，所述第二电压脉冲的电压极性与所述第一电压脉冲的极性不同。

5. 发明授权

US08134857B2 Methods for high speed reading operation of phase change memory and device employing same 有权
标题翻译：相变存储器的高速读取操作的方法及其使用的装置
公开(公告)号：US08134857B2
公开(公告)日：2012-03-13
申请号：US12466650
申请日：2009-05-15
申请人： Yuyu Lin , Yi-Chou Chen
发明人： Yuyu Lin , Yi-Chou Chen
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2013/0073 , G11C2013/0092
摘要： Phase change based memory devices and methods for operating described herein overcome the performance limitations of slow set speeds and long recovery times commonly associated with phase change memory devices, enabling high speed operation and extending their usefulness into high speed applications typically filled by DRAM and SRAM memory.
摘要翻译：基于相变的存储器件和本文描述的操作方法克服了慢设定速度和通常与相变存储器件相关联的长恢复时间的性能限制，使得能够进行高速操作并将其有用性扩展到通常由DRAM和SRAM存储器填充的高速应用。

6. 发明授权

US08331127B2 Nonvolatile memory device having a transistor connected in parallel with a resistance switching device 有权
标题翻译：具有与电阻切换装置并联连接的晶体管的非易失性存储装置
公开(公告)号：US08331127B2
公开(公告)日：2012-12-11
申请号：US12785978
申请日：2010-05-24
申请人： Yi-Chou Chen , Wei-Chih Chien , Feng-Ming Lee
发明人： Yi-Chou Chen , Wei-Chih Chien , Feng-Ming Lee
IPC分类号： G11C13/00
CPC分类号： G11C13/003 , G11C8/14 , G11C11/56 , G11C11/5678 , G11C11/5685 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0009 , G11C13/004 , G11C13/0069 , G11C2013/0076 , G11C2213/75 , G11C2213/79
摘要： A memory device comprises an array of memory cells each capable of storing multiple bits of data. The memory cells are arranged in memory strings that are connected to a common source line. Each memory cell includes a programmable transistor connected in parallel with a resistance switching device. The transistor is switchable between a plurality of different threshold voltages associated with respective memory states. The resistance switching device is configured to be switchable between a plurality of different resistances associated with respective memory states.
摘要翻译：存储器件包括每个能够存储多个数据位的存储器单元的阵列。存储单元被布置在连接到公共源极线的存储器串中。每个存储单元包括与电阻切换装置并联连接的可编程晶体管。晶体管可在与各个存储器状态相关联的多个不同阈值电压之间切换。电阻切换装置被配置为可在与各个存储器状态相关联的多个不同电阻之间切换。

7. 发明申请

US20110242874A1 RESISTIVE MEMORY AND METHOD FOR CONTROLLING OPERATIONS OF THE SAME 有权
标题翻译：电阻记忆及其控制方法
公开(公告)号：US20110242874A1
公开(公告)日：2011-10-06
申请号：US12753316
申请日：2010-04-02
申请人： Wei-Chih Chien , Yi-Chou Chen , Feng-Ming Lee
发明人： Wei-Chih Chien , Yi-Chou Chen , Feng-Ming Lee
IPC分类号： G11C11/00 , H01L45/00
CPC分类号： G11C13/004 , G11C11/5614 , G11C11/5685 , G11C13/0007 , G11C13/0011 , G11C13/0069 , G11C2213/51 , G11C2213/71 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/146
摘要： A resistive memory and a method for controlling operations of the resistive memory are provided. The resistive memory has a first memory layer, a second memory layer and a medium layer. Each of the first memory layer and the second memory layer is used to store data. The medium layer is formed between the first memory layer and the second memory layer. The method comprises at least a step of measuring a resistance between the first memory layer and the second memory layer, and determining which one of a first state, a second state and a third state is a state of the resistive memory according to the measured resistance.
摘要翻译：提供了一种用于控制电阻性存储器的操作的电阻性存储器和方法。电阻性存储器具有第一存储器层，第二存储器层和介质层。第一存储器层和第二存储器层中的每一个用于存储数据。介质层形成在第一存储层和第二存储层之间。该方法至少包括测量第一存储层和第二存储层之间的电阻的步骤，以及根据测得的电阻确定第一状态，第二状态和第三状态中的哪一种是电阻性存储器的状态。

8. 发明授权

US08295075B2 Resistive memory and method for controlling operations of the same 有权
标题翻译：电阻记忆及其控制方法
公开(公告)号：US08295075B2
公开(公告)日：2012-10-23
申请号：US12753316
申请日：2010-04-02
申请人： Wei-Chih Chien , Yi-Chou Chen , Feng-Ming Lee
发明人： Wei-Chih Chien , Yi-Chou Chen , Feng-Ming Lee
IPC分类号： G11C11/00
CPC分类号： G11C13/004 , G11C11/5614 , G11C11/5685 , G11C13/0007 , G11C13/0011 , G11C13/0069 , G11C2213/51 , G11C2213/71 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/146
摘要： A resistive memory and a method for controlling operations of the resistive memory are provided. The resistive memory has a first memory layer, a second memory layer and a medium layer. Each of the first memory layer and the second memory layer is used to store data. The medium layer is formed between the first memory layer and the second memory layer. The method comprises at least a step of measuring a resistance between the first memory layer and the second memory layer, and determining which one of a first state, a second state and a third state is a state of the resistive memory according to the measured resistance.
摘要翻译：提供了一种用于控制电阻性存储器的操作的电阻性存储器和方法。电阻性存储器具有第一存储器层，第二存储器层和介质层。第一存储器层和第二存储器层中的每一个用于存储数据。介质层形成在第一存储层和第二存储层之间。该方法至少包括测量第一存储层和第二存储层之间的电阻的步骤，以及根据测得的电阻确定第一状态，第二状态和第三状态中的哪一种是电阻性存储器的状态。

9. 发明授权

US08149610B2 Nonvolatile memory device 有权
标题翻译：非易失性存储器件
公开(公告)号：US08149610B2
公开(公告)日：2012-04-03
申请号：US12778533
申请日：2010-05-12
申请人： Yi-Chou Chen , Wei-Chih Chien , Feng-Ming Lee
发明人： Yi-Chou Chen , Wei-Chih Chien , Feng-Ming Lee
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C11/5685 , G11C13/0011 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C2013/0071 , G11C2013/0076 , G11C2213/76 , G11C2213/79
摘要： A memory device comprises an array of memory cells each capable of storing multiple bits of data. Each memory cell includes a programmable transistor in series with a resistance switching device. The transistor is switchable between a plurality of different threshold voltages associated with respective memory states. The resistance switching device is configured to be switchable between a plurality of different resistances associated with respective memory states.
摘要翻译：存储器件包括每个能够存储多个数据位的存储器单元的阵列。每个存储单元包括与电阻切换装置串联的可编程晶体管。晶体管可在与各个存储器状态相关联的多个不同阈值电压之间切换。电阻切换装置被配置为可在与各个存储器状态相关联的多个不同电阻之间切换。

10. 发明申请

US20110280058A1 NONVOLATILE MEMORY DEVICE 有权
标题翻译：非易失性存储器件
公开(公告)号：US20110280058A1
公开(公告)日：2011-11-17
申请号：US12778533
申请日：2010-05-12
申请人： Yi-Chou Chen , Wei-Chih Chien , Feng-Ming Lee
发明人： Yi-Chou Chen , Wei-Chih Chien , Feng-Ming Lee
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/0007 , G11C11/5685 , G11C13/0011 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C2013/0071 , G11C2013/0076 , G11C2213/76 , G11C2213/79
摘要： A memory device comprises an array of memory cells each capable of storing multiple bits of data. Each memory cell includes a programmable transistor in series with a resistance switching device. The transistor is switchable between a plurality of different threshold voltages associated with respective memory states. The resistance switching device is configured to be switchable between a plurality of different resistances associated with respective memory states.
摘要翻译：存储器件包括每个能够存储多个数据位的存储器单元的阵列。每个存储单元包括与电阻切换装置串联的可编程晶体管。晶体管可在与各个存储器状态相关联的多个不同阈值电压之间切换。电阻切换装置被配置为可在与各个存储器状态相关联的多个不同电阻之间切换。

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