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1. 发明授权

US07319267B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07319267B2
公开(公告)日：2008-01-15
申请号：US11712440
申请日：2007-03-01
申请人： Yutaka Uematsu , Hideki Osaka , Yoji Nishio , Yukitoshi Hirose
发明人： Yutaka Uematsu , Hideki Osaka , Yoji Nishio , Yukitoshi Hirose
IPC分类号： H01L23/02 , H01L23/34
CPC分类号： H01L23/642 , H01L23/5223 , H01L23/5228 , H01L23/5286 , H01L23/647 , H01L25/105 , H01L2224/73204 , H01L2924/19105 , H01L2924/3011
摘要： In a prior art, there has been a method in which a power supply line of an output buffer and that of a control circuit are independently provided so that the power supply noise occurring in the control circuit will not affect the output buffer. However, this method has had the problems that it increases both the number of power supply/grounding pins and power feed line inductance.The present invention provides a technique which, without causing the above two problems, i.e., (1) increased number of power supply/grounding pins and (2) increased power feed line inductance, prevents the noise causing a problem in a control circuit, from becoming routed around and induced into an output buffer. More specifically, the above can be realized by using either of two methods: (A) providing an on-chip bypass capacitor for the control circuit and isolating a power feed route of the control circuit from that of the output buffer in an AC-like manner, or (B) designing electrical parameters (inserting resistors) such that the oscillation mode of any electrical parameter noise induced into the power feed routes will change to overdamping.
摘要翻译：在现有技术中，存在一种方法，其中独立地提供输出缓冲器的电源线和控制电路的电源线，使得控制电路中出现的电源噪声不会影响输出缓冲器。然而，该方法存在增加电源/接地引脚数和馈电线电感的问题。本发明提供一种技术，其不会引起上述两个问题，即（1）增加电源/接地引脚数量和（2）增加的馈电线电感，防止在控制电路中引起问题的噪声变成路由并感应到输出缓冲区。更具体地，可以通过以下两种方法之一来实现上述：（A）为控制电路提供片上旁路电容器，并将控制电路的馈电路径与AC类似的输出缓冲器的馈电路径隔离方式或（B）设计电参数（插入电阻），使得引入馈电路径的任何电参数噪声的振荡模式将变为过阻尼。

2. 发明申请

US20060017144A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20060017144A1
公开(公告)日：2006-01-26
申请号：US10981676
申请日：2004-11-05
申请人： Yutaka Uematsu , Hideki Osaka , Yoji Nishio , Yukitoshi Hirose
发明人： Yutaka Uematsu , Hideki Osaka , Yoji Nishio , Yukitoshi Hirose
IPC分类号： H01L23/02
CPC分类号： H01L23/642 , H01L23/5223 , H01L23/5228 , H01L23/5286 , H01L23/647 , H01L25/105 , H01L2224/73204 , H01L2924/19105 , H01L2924/3011
摘要： The present invention provides a technique which, without causing two problems, i.e., (1) increased number of power supply/grounding pins and (2) increased power feed line inductance, prevents the noise causing a problem in a control circuit, from becoming routed around and induced into an output buffer. More specifically, the above can be realized by using either of two methods: (A) providing an on-chip bypass capacitor for the control circuit and isolating a power feed route of the control circuit from that of the output buffer in an AC-like manner, or (B) designing electrical parameters (inserting resistors) such that the oscillation mode of any electrical parameter noise induced into the power feed routes will change to overdamping.
摘要翻译：本发明提供一种技术，其不会引起两个问题，即（1）增加电源/接地引脚的数量和（2）增加的馈电线电感，防止在控制电路中引起问题的噪声变为布线并引入输出缓冲区。更具体地，可以通过以下两种方法之一来实现上述：（A）为控制电路提供片上旁路电容器，并将控制电路的馈电路径与AC类似的输出缓冲器的馈电路径隔离方式或（B）设计电参数（插入电阻），使得引入馈电路径的任何电参数噪声的振荡模式将变为过阻尼。

3. 发明申请

US20070145559A1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US20070145559A1
公开(公告)日：2007-06-28
申请号：US11712440
申请日：2007-03-01
申请人： Yutaka Uematsu , Hideki Osaka , Yoji Nishio , Yukitoshi Hirose
发明人： Yutaka Uematsu , Hideki Osaka , Yoji Nishio , Yukitoshi Hirose
IPC分类号： H01L23/02
CPC分类号： H01L23/642 , H01L23/5223 , H01L23/5228 , H01L23/5286 , H01L23/647 , H01L25/105 , H01L2224/73204 , H01L2924/19105 , H01L2924/3011
摘要： In a prior art, there has been a method in which a power supply line of an output buffer and that of a control circuit are independently provided so that the power supply noise occurring in the control circuit will not affect the output buffer. However, this method has had the problems that it increases both the number of power supply/grounding pins and power feed line inductance. The present invention provides a technique which, without causing the above two problems, i.e., (1) increased number of power supply/grounding pins and (2) increased power feed line inductance, prevents the noise causing a problem in a control circuit, from becoming routed around and induced into an output buffer. More specifically, the above can be realized by using either of two methods: (A) providing an on-chip bypass capacitor for the control circuit and isolating a power feed route of the control circuit from that of the output buffer in an AC-like manner, or (B) designing electrical parameters (inserting resistors) such that the oscillation mode of any electrical parameter noise induced into the power feed routes will change to overdamping.
摘要翻译：在现有技术中，存在一种方法，其中独立地提供输出缓冲器的电源线和控制电路的电源线，使得控制电路中出现的电源噪声不会影响输出缓冲器。然而，该方法存在增加电源/接地引脚数和馈电线电感的问题。本发明提供一种技术，其不会引起上述两个问题，即（1）增加电源/接地引脚数量和（2）增加的馈电线电感，防止在控制电路中引起问题的噪声变成路由并感应到输出缓冲区。更具体地，可以通过以下两种方法之一来实现上述：（A）为控制电路提供片上旁路电容器，并将控制电路的馈电路径与AC类似的输出缓冲器的馈电路径隔离方式或（B）设计电参数（插入电阻），使得引入馈电路径的任何电参数噪声的振荡模式将变为过阻尼。

4. 发明授权

US07187069B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07187069B2
公开(公告)日：2007-03-06
申请号：US10981676
申请日：2004-11-05
申请人： Yutaka Uematsu , Hideki Osaka , Yoji Nishio , Yukitoshi Hirose
发明人： Yutaka Uematsu , Hideki Osaka , Yoji Nishio , Yukitoshi Hirose
IPC分类号： H01L23/02 , H01L23/34
CPC分类号： H01L23/642 , H01L23/5223 , H01L23/5228 , H01L23/5286 , H01L23/647 , H01L25/105 , H01L2224/73204 , H01L2924/19105 , H01L2924/3011
摘要： The present invention provides a technique which, without causing two problems, i.e., (1) increased number of power supply/grounding pins and (2) increased power feed line inductance, prevents the noise causing a problem in a control circuit, from becoming routed around and induced into an output buffer. More specifically, the above can be realized by using either of two methods: (A) providing an on-chip bypass capacitor for the control circuit and isolating a power feed route of the control circuit from that of the output buffer in an AC-like manner, or (B) designing electrical parameters (inserting resistors) such that the oscillation mode of any electrical parameter noise induced into the power feed routes will change to overdamping.
摘要翻译：本发明提供一种技术，其不会引起两个问题，即（1）增加电源/接地引脚的数量和（2）增加的馈电线电感，防止在控制电路中引起问题的噪声变为布线并引入输出缓冲区。更具体地，可以通过以下两种方法之一来实现上述：（A）为控制电路提供片上旁路电容器，并将控制电路的馈电路径与AC类似的输出缓冲器的馈电路径隔离方式或（B）设计电参数（插入电阻），使得引入馈电路径的任何电参数噪声的振荡模式将变为过阻尼。

5. 发明授权

US07965572B2 Semiconductor device and information processing system 有权
标题翻译：半导体器件和信息处理系统
公开(公告)号：US07965572B2
公开(公告)日：2011-06-21
申请号：US12504319
申请日：2009-07-16
申请人： Yutaka Uematsu , Tatsuya Saito , Yoji Nishio , Yukitoshi Hirose
发明人： Yutaka Uematsu , Tatsuya Saito , Yoji Nishio , Yukitoshi Hirose
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/40618 , G11C11/4074 , G11C2211/4067
摘要： A semiconductor device or an information processing system comprises a plurality of circuit units, and a control unit for controlling a start timing of large-current operations executed by the respective circuit units within a predetermined period, where the large-current operation involves a relatively large current which flows in a power supply system, as compared with other operations. The control unit controls the start timing of the large-current operation from one circuit unit to another such that the waveform of a current flowing from the power supply system is shaped into the waveform of a half cycle of a sinusoidal wave when the circuit units execute large-current operations within the predetermined period.
摘要翻译：半导体器件或信息处理系统包括多个电路单元，以及控制单元，用于在预定时间段内控制由各个电路单元执行的大电流操作的开始定时，其中大电流操作涉及相对大的与其他操作相比，在电源系统中流动的电流。控制单元控制从一个电路单元到另一个电路单元的大电流操作的开始定时，使得当电路单元执行时，从电源系统流过的电流的波形被成形为正弦波的半周期的波形在预定时段内的大电流操作。

6. 发明申请

US20100013528A1 SEMICONDUCTOR DEVICE AND INFORMATION PROCESSING SYSTEM 有权
标题翻译：半导体器件和信息处理系统
公开(公告)号：US20100013528A1
公开(公告)日：2010-01-21
申请号：US12504319
申请日：2009-07-16
申请人： Yutaka Uematsu , Tatsuya Saito , Yoji Nishio , Yukitoshi Hirose
发明人： Yutaka Uematsu , Tatsuya Saito , Yoji Nishio , Yukitoshi Hirose
IPC分类号： H03L5/00
CPC分类号： G11C11/406 , G11C11/40618 , G11C11/4074 , G11C2211/4067
摘要： A semiconductor device or an information processing system comprises a plurality of circuit units, and a control unit for controlling a start timing of large-current operations executed by the respective circuit units within a predetermined period, where the large-current operation involves a relatively large current which flows in a power supply system, as compared with other operations. The control unit controls the start timing of the large-current operation from one circuit unit to another such that the waveform of a current flowing from the power supply system is shaped into the waveform of a half cycle of a sinusoidal wave when the circuit units execute large-current operations within the predetermined period.
摘要翻译：半导体器件或信息处理系统包括多个电路单元，以及控制单元，用于在预定时间段内控制由各个电路单元执行的大电流操作的开始定时，其中大电流操作涉及相对大的与其他操作相比，在电源系统中流动的电流。控制单元控制从一个电路单元到另一个电路单元的大电流操作的开始定时，使得当电路单元执行时，从电源系统流过的电流的波形被成形为正弦波的半周期的波形在预定时段内的大电流操作。

7. 发明授权

US07986037B2 Low noise semiconductor device 有权
标题翻译：低噪声半导体器件
公开(公告)号：US07986037B2
公开(公告)日：2011-07-26
申请号：US12068606
申请日：2008-02-08
申请人： Yutaka Uematsu , Tatsuya Saito , Hideki Osaka , Yoji Nishio , Shunichi Saito
发明人： Yutaka Uematsu , Tatsuya Saito , Hideki Osaka , Yoji Nishio , Shunichi Saito
IPC分类号： H01L23/52
CPC分类号： H05K1/0231 , H01L23/50 , H01L23/5385 , H01L23/66 , H01L2224/16225 , H01L2924/12044 , H01L2924/3011 , H05K1/09 , H05K1/111 , H05K1/167 , H05K2201/0352 , H05K2201/0391 , H05K2201/09236 , H05K2201/09309 , H05K2201/09481 , H05K2201/09781 , H05K2201/10636 , H05K2201/10674 , Y02P70/611 , H01L2924/00
摘要： As a power feed route in a semiconductor chip, a power feed route which reduces antiresonance impedance in the frequency range of tens of MHz is to be realized thereby to suppress power noise in a semiconductor device. By inserting structures which raise the resistance in the medium frequency band into parts where the resistance is intrinsically high, such as power wiring in a semiconductor package and capacitor interconnecting electrode parts, the antiresonance impedance in the medium frequency band can be effectively reduced while keeping the impedance low at the low frequency.
摘要翻译：作为半导体芯片中的馈电路径，可以实现降低数十MHz频率范围内的反谐振阻抗的馈电路径，从而抑制半导体器件的功率噪声。通过插入将中频带中的电阻提升到电阻本身较高的部分的结构，例如半导体封装中的功率布线和电容器互连电极部件，可以有效地减少中频带中的反谐振阻抗，同时保持阻抗低在低频。

8. 发明授权

US07760531B2 Semiconductor module 失效
标题翻译：半导体模块
公开(公告)号：US07760531B2
公开(公告)日：2010-07-20
申请号：US11511262
申请日：2006-08-29
申请人： Yoji Nishio , Seiji Funaba , Yutaka Uematsu , Hideki Osaka
发明人： Yoji Nishio , Seiji Funaba , Yutaka Uematsu , Hideki Osaka
IPC分类号： G11C5/02
CPC分类号： G11C5/147 , G11C5/02 , G11C7/02 , H01L24/48 , H01L2224/05554 , H01L2224/4809 , H01L2224/48091 , H01L2224/48227 , H01L2224/4847 , H01L2924/00014 , H01L2924/10161 , H01L2924/15183 , H01L2924/15311 , H01L2924/181 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： A semiconductor module includes a first semiconductor device, a second semiconductor device and a reference voltage supplying circuit. The first semiconductor device includes a first electrode. The second semiconductor device includes a second electrode. The reference voltage supplying circuit is for supplying a reference potential to the first electrode and the second electrode and for suppressing a noise to be transferred between the first electrode and the second electrode.
摘要翻译：半导体模块包括第一半导体器件，第二半导体器件和参考电压提供电路。第一半导体器件包括第一电极。第二半导体器件包括第二电极。参考电压提供电路用于向第一电极和第二电极提供参考电位，并用于抑制在第一电极和第二电极之间传递的噪声。

9. 发明授权

US08878351B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08878351B2
公开(公告)日：2014-11-04
申请号：US12318700
申请日：2009-01-06
申请人： Eiichi Suzuki , Hideki Osaka , Yutaka Uematsu , Yoji Nishio
发明人： Eiichi Suzuki , Hideki Osaka , Yutaka Uematsu , Yoji Nishio
IPC分类号： H01L23/02 , H01L23/50 , H01L23/498 , H01L25/065 , H01L25/18
CPC分类号： H01L25/0657 , H01L23/49827 , H01L23/49838 , H01L23/50 , H01L25/18 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2924/00014 , H01L2924/01055 , H01L2924/15311 , H01L2224/05599
摘要： A semiconductor device having a chip-on-chip structure is constituted of a first semiconductor chip and even-numbered pairs of second semiconductor chips, all of which are laminated together on the surface of an interposer. The first semiconductor chip controls each pair of the second semiconductor chips so as to activate one second semiconductor chip while inactivating another second semiconductor chip. The second semiconductor chips are paired together in such a way that through-vias and electrodes thereof are positioned opposite to each other via bumps. Since drive voltage electrodes supplied with a drive voltage (VDD) and reference potential electrodes supplied with a reference potential (VSS) are mutually connected together between the paired second semiconductor chips, it is possible to increase the overall electrostatic capacitance of each second semiconductor chip so as to substantially reduce feed noise without increasing the overall layout area of the semiconductor device.
摘要翻译：具有片上芯片结构的半导体器件由第一半导体芯片和偶数对的第二半导体芯片组成，所有第二半导体芯片在中介层的表面上层压在一起。第一半导体芯片控制每对第二半导体芯片，以激活一个第二半导体芯片，同时使另一个第二半导体芯片失效。第二半导体芯片以通孔和电极通过凸块彼此相对定位的方式配对在一起。由于提供有驱动电压（VDD）的驱动电压电极和提供参考电位（VSS）的参考电位电极在成对的第二半导体芯片之间相互连接在一起，因此可以增加每个第二半导体芯片的总静电电容以便在不增加半导体器件的整体布局面积的情况下显着降低馈送噪声。

10. 发明授权

US07990228B2 Semiconductor device and wiring part thereof 有权
标题翻译：半导体器件及其布线部分
公开(公告)号：US07990228B2
公开(公告)日：2011-08-02
申请号：US12060941
申请日：2008-04-02
申请人： Yutaka Uematsu , Hideki Osaka , Yoji Nishio , Eiichi Suzuki
发明人： Yutaka Uematsu , Hideki Osaka , Yoji Nishio , Eiichi Suzuki
IPC分类号： H04B3/28
CPC分类号： H05K1/162 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/50 , H01L2924/0002 , H01L2924/3011 , H05K1/0231 , H05K1/111 , H05K2201/0175 , H05K2201/0179 , H05K2201/09763 , H05K2201/10515 , H05K2201/10522 , H05K2201/10734 , H01L2924/00
摘要： A technique capable of achieving both improvement of mounting density and noise reduction for a semiconductor device is provided. An LSI mounted on a printed wiring board comprises a grounding BGA ball and a power BGA ball to get power supply from the printed wiring board, and the grounding BGA ball and the power BGA ball are arranged closely to each other. A decoupling capacitor is mounted on the printed wiring board and has a first terminal and a second terminal. The grounding BGA ball and the first terminal are connected by a first metal electrode plate, and the power BGA ball and the second terminal are connected by a second metal electrode plate. The first metal electrode plate and the second metal electrode plate interpose a dielectric film having a thickness equal to or smaller than 1 μm therebetween.
摘要翻译：提供了能够实现半导体器件的安装密度和噪声降低的改进的技术。安装在印刷电路板上的LSI包括接地BGA球和电源BGA球，以从印刷线路板获得电源，并且接地BGA球和电源BGA球彼此靠近地布置。去耦电容器安装在印刷电路板上，并具有第一端子和第二端子。接地BGA球和第一端子通过第一金属电极板连接，电力BGA球和第二端子通过第二金属电极板连接。第一金属电极板和第二金属电极板之间插入厚度等于或小于1μm的电介质膜。

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