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    • 7. 发明申请
    • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    • 半导体器件及其制造方法
    • US20130037816A1
    • 2013-02-14
    • US13520271
    • 2010-12-02
    • Kazuhide TomiyasuYutaka TakafujiYasumori FukushimaKenshi TadaShin Matsumoto
    • Kazuhide TomiyasuYutaka TakafujiYasumori FukushimaKenshi TadaShin Matsumoto
    • H01L29/786H01L21/50
    • H01L27/1266H01L21/76898H01L21/8221H01L27/0688H01L27/1251H01L29/7833H01L2224/08225H01L2224/80896
    • A semiconductor device (130) includes: a bonding substrate (100); a thin film element (80) formed on the bonding substrate (100); and a semiconductor element (90) bonded to the bonding substrate (100), the semiconductor element (90) including semiconductor element main body (50) and a plurality of underlying layers (51-54) stacked on a side of the semiconductor element main body (50) facing the bonding substrate (100), and each of the underlying layers (51-54) including an insulating layer and a circuit pattern in the insulating layer, wherein an end of the semiconductor element (90) facing the thin film element (80) is provided in a stepped form so that the closer to the bonding substrate the underlying layers arc, the farther ends of the underlying layers facing the thin film element protrude, the end of the semiconductor element (90) is covered with a resin layer (120), and the thin film element (80) is connected to the semiconductor element main body (50) via a connection line (121a) provided on the resin layer (120).
    • 半导体器件(130)包括:接合衬底(100); 形成在所述接合基板(100)上的薄膜元件(80)。 以及与所述接合基板(100)接合的半导体元件(90),所述半导体元件(90)包括半导体元件主体(50)和层叠在所述半导体元件主体(50)侧的多个下层(51-54) 主体(50),以及在绝缘层中包括绝缘层和电路图案的每个下层(51-54),其中半导体元件(90)的面向薄膜的端部 元件(80)以阶梯形式设置,使得更靠近接合基底的下面的层弧形,面向薄膜元件的下面的层的更远的端部突出,半导体元件(90)的端部覆盖有 树脂层(120),并且薄膜元件(80)经由设置在树脂层(120)上的连接线(121a)连接到半导体元件主体(50)。
    • 10. 发明申请
    • SEMICONDUCTOR DEVICE AND DISPLAY DEVICE
    • 半导体器件和显示器件
    • US20100252885A1
    • 2010-10-07
    • US12742463
    • 2008-09-19
    • Yasumori FukushimaYutaka TakafujiKenshi Tada
    • Yasumori FukushimaYutaka TakafujiKenshi Tada
    • H01L27/12
    • H01L21/84H01L21/76254H01L27/12H01L29/78603H01L29/78621
    • A semiconductor device (10) is formed by bonding a semiconductor substrate (1) including a CMOS transistor (3) to a glass substrate (2). The semiconductor substrate (1) is formed by partial separation at a separation layer. A P-type high concentration impurity region (39n) is formed in electric connection with a channel region (35n) of an NMOS transistor (3n) so that an electric potential of the channel region (35n) is fixed. The P-type high concentration impurity region (39n) has the same P conductive type as that of the channel region (35n) and also has a concentration higher than that of the channel region (35n). An N-type high concentration impurity region (39p) is formed in electric connection with a channel region (35p) of a PMOS transistor (3p) so that an electric potential of the channel region (35p) is fixed. The N-type high concentration impurity region (39p) has the same N conductive type as that of the channel region (35p) and also has a concentration higher than that of the channel region (35p). This makes it possible to provide a semiconductor device whose performance can be enhanced by restraint on variation in a characteristic of a thin film transistor and a display device including the semiconductor device.
    • 半导体器件(10)通过将包括CMOS晶体管(3)的半导体衬底(1)结合到玻璃衬底(2)而形成。 半导体衬底(1)通过在分离层处的部分分离而形成。 形成与NMOS晶体管(3n)的沟道区(35n)电连接的P型高浓度杂质区(39n),使得沟道区(35n)的电位固定。 P型高浓度杂质区域(39n)具有与沟道区域(35n)相同的P导电型,并且其浓度高于沟道区域(35n)的浓度。 形成与PMOS晶体管(3p)的沟道区(35p)电连接的N型高浓度杂质区(39p),使得沟道区(35p)的电位固定。 N型高浓度杂质区(39p)具有与沟道区(35p)相同的N导电型,其浓度高于沟道区(35p)。 这使得可以提供一种通过限制薄膜晶体管的特性变化和包括半导体器件的显示装置来提高其性能的半导体器件。