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1. 发明授权

US4984052A Bonded substrate of semiconductor elements having a high withstand voltage 失效
标题翻译：具有高耐压的半导体元件的粘结基板
公开(公告)号：US4984052A
公开(公告)日：1991-01-08
申请号：US418587
申请日：1989-10-10
申请人： Yutaka Koshino , Yoshiro Baba , Akihiko Osawa , Satoshi Yanagiya
发明人： Yutaka Koshino , Yoshiro Baba , Akihiko Osawa , Satoshi Yanagiya
IPC分类号： H01L21/02 , H01L21/762 , H01L21/763 , H01L27/12
CPC分类号： H01L21/763 , H01L21/76264 , H01L21/76275 , H01L21/76281 , H01L21/76286 , Y10S257/914
摘要： A bonded substrate comprises a first semiconductor substrate in which a plurality of semiconductor elements are formed, a second semiconductor substrate adhered to the first semiconductor substrate so as to support it by means of an insulating layer interposed therebetween, a first semi-insulating polysilicon layer interposed between the first semiconductor substrate and the insulating layer, and a second semi-insulating polysilicon layer interposed between the insulating layer and the second semiconductor substrate. The semi-insulating polysilicon layers serve to reduce the voltage applied to the insulating layer and to prevent the insulating layer from being etched.
摘要翻译：键合衬底包括其中形成有多个半导体元件的第一半导体衬底，第二半导体衬底，其粘附到第一半导体衬底，以便通过插入其间的绝缘层来支撑它;第一半绝缘多晶硅层，在第一半导体衬底和绝缘层之间，以及插入在绝缘层和第二半导体衬底之间的第二半绝缘多晶硅层。半绝缘多晶硅层用于降低施加到绝缘层的电压并防止绝缘层被蚀刻。

2. 发明授权

US5084408A Method of making complete dielectric isolation structure in semiconductor integrated circuit 失效
标题翻译：在半导体集成电路中制作完整的电介质隔离结构的方法
公开(公告)号：US5084408A
公开(公告)日：1992-01-28
申请号：US596294
申请日：1990-10-15
申请人： Yoshiro Baba , Yutaka Koshino , Akihiko Osawa , Satoshi Yanagiya
发明人： Yoshiro Baba , Yutaka Koshino , Akihiko Osawa , Satoshi Yanagiya
IPC分类号： H01L21/76 , H01L21/762 , H01L21/763
CPC分类号： H01L21/76202 , H01L21/76264 , H01L21/763 , H01L21/76283 , H01L21/76286 , Y10S438/978
摘要： For controlling unwanted production of crystal defects from corners of isolated regions in a complete dielectric isolation structure, after at least one trench or groove is provided through a mask of an insulating film in a semiconductor substrate adhered to an insulating film of a base substrate, the mask is side-etched and the insulating film of the base substrate is selectively etched at the same time to expose corners of the semiconductor substrate. The exposed corners of the semiconductor substrate is then subjected to isotropic etching to remove a pointed portion therefrom. Thereafter, side surfaces of the semiconductor substrate exposed within the trench is oxidized to provide an insulating film for dielectric isolation which has rounded corners.

3. 发明授权

US5578508A Vertical power MOSFET and process of fabricating the same 失效
标题翻译：垂直功率MOSFET及其制造工艺
公开(公告)号：US5578508A
公开(公告)日：1996-11-26
申请号：US426233
申请日：1995-04-21
申请人： Yoshiro Baba , Satoshi Yanagiya , Noboru Matsuda , Akihiko Osawa , Masanobu Tsuchitani
发明人： Yoshiro Baba , Satoshi Yanagiya , Noboru Matsuda , Akihiko Osawa , Masanobu Tsuchitani
IPC分类号： H01L21/302 , H01L21/265 , H01L21/266 , H01L21/306 , H01L21/336 , H01L29/78 , H01L21/304 , H01L21/76
CPC分类号： H01L29/7813 , H01L29/66734 , H01L21/26586 , H01L21/266 , H01L29/7838
摘要： A channel region and a source region are formed on a surface of a substrate by double diffusion. A trench is formed so as to penetrate a part of the channel region and a part of the source region and reach the substrate. After an insulating film is formed on an inner wall of the trench, a polysilicon layer is buried up to an intermediate portion of the trench. In this state, channel ions are implanted in a side surface region of the trench, thereby depleting a channel region. Thereafter, a polysilicon layer for leading out a gate is buried in the trench.
摘要翻译：通过双扩散在衬底的表面上形成沟道区域和源极区域。形成沟槽，以便穿透沟道区域的一部分和源区域的一部分并到达衬底。在沟槽的内壁上形成绝缘膜之后，将多晶硅层埋入沟槽的中间部分。在这种状态下，沟道离子注入沟槽的侧表面区域，从而耗尽沟道区域。此后，用于引出栅极的多晶硅层被埋在沟槽中。

4. 发明授权

US5242845A Method of production of vertical MOS transistor 失效
标题翻译：垂直MOS晶体管的制造方法
公开(公告)号：US5242845A
公开(公告)日：1993-09-07
申请号：US866418
申请日：1992-04-10
申请人： Yoshiro Baba , Shunichi Hiraki , Akihiko Osawa , Satoshi Yanagiya
发明人： Yoshiro Baba , Shunichi Hiraki , Akihiko Osawa , Satoshi Yanagiya
IPC分类号： H01L29/06 , H01L29/40 , H01L29/423 , H01L29/78
CPC分类号： H01L29/402 , H01L29/407 , H01L29/42368 , H01L29/7813 , H01L29/4232 , H01L29/4238 , H01L29/7831
摘要： A vertical MOS transistor comprises a semiconductor substrate, a first impurity region defined on the surface of the semiconductor substrate, a second impurity region defined under the first impurity region, the conduction type of the second impurity region being opposite to that of the first impurity region, a trench engraved on the surface of the semiconductor substrate to cut through the first and second impurity regions deeper than at least the bottom of the second impurity region, and a gate electrode disposed in the trench with a gate insulation film interposing between the wall of the trench and the gate electrode. The gate insulation film is thicker on the bottom of the trench and on part of the side walls of the trench continuous to the bottom than on the other parts.
摘要翻译：垂直MOS晶体管包括半导体衬底，限定在半导体衬底的表面上的第一杂质区域，限定在第一杂质区域下方的第二杂质区域，第二杂质区域的导电类型与第一杂质区域的导电类型相反刻蚀在所述半导体衬底的表面上的沟槽，以切割穿过所述第一和第二杂质区域至少比所述第二杂质区域的底部更深;以及栅电极，设置在所述沟槽中，栅极绝缘膜插入在所述第二杂质区域的壁之间沟槽和栅电极。栅极绝缘膜在沟槽的底部和沟槽的侧壁的一部分比底部更厚，而不是其它部分。

5. 发明授权

US5126807A Vertical MOS transistor and its production method 失效
标题翻译：垂直MOS晶体管及其制作方法
公开(公告)号：US5126807A
公开(公告)日：1992-06-30
申请号：US713505
申请日：1991-06-12
申请人： Yoshiro Baba , Shunichi Hiraki , Akihiko Osawa , Satoshi Yanagiya
发明人： Yoshiro Baba , Shunichi Hiraki , Akihiko Osawa , Satoshi Yanagiya
IPC分类号： H01L29/06 , H01L29/40 , H01L29/423 , H01L29/78
CPC分类号： H01L29/402 , H01L29/407 , H01L29/42368 , H01L29/42376 , H01L29/7813
摘要： A vertical MOS transistor comprises a semiconductor substrate, a first impurity region defined on the surface of the semiconductor substrate, a second impurity region defined under the first impurity region, the conduction type of the second impurity region being opposite to that of the first impurity region, a trench engraved on the surface of the semiconductor substrate to cut through the first and second impurity regions deeper than at least the bottom of the second impurity region, and a gate electrode disposed in the trench with a gate insulation film interposing between the wall of the trench and the gate electrode. THE gate insulation film is thicker on the bottom of the trench and on part of the side walls of the trench continuous to the bottom than on the other parts.
摘要翻译：垂直MOS晶体管包括半导体衬底，限定在半导体衬底的表面上的第一杂质区域，限定在第一杂质区域下方的第二杂质区域，第二杂质区域的导电类型与第一杂质区域的导电类型相反刻蚀在所述半导体衬底的表面上的沟槽，以切割穿过所述第一和第二杂质区域至少比所述第二杂质区域的底部更深;以及栅电极，设置在所述沟槽中，栅极绝缘膜插入在所述第二杂质区域的壁之间沟槽和栅电极。栅极绝缘膜在沟槽的底部和沟槽的侧壁的一部分比底部的部分更厚，而不是其他部分。

6. 发明授权

US5126817A Dielectrically isolated structure for use in soi-type semiconductor device 失效
标题翻译：用于单相半导体器件的绝缘隔离结构
公开(公告)号：US5126817A
公开(公告)日：1992-06-30
申请号：US596286
申请日：1990-10-12
申请人： Yoshiro Baba , Yutaka Koshino , Akihiko Osawa , Kenji Yamawaki
发明人： Yoshiro Baba , Yutaka Koshino , Akihiko Osawa , Kenji Yamawaki
IPC分类号： H01L21/76 , H01L21/762 , H01L21/763
CPC分类号： H01L21/763 , H01L21/76264 , H01L21/76275 , H01L21/76286
摘要： A dielectrically isolated structure for use in an SOI-type semiconductor device according to the present invention comprises a substrate having an element-forming region formed therein on a first insulating film, the region being made of a first material, at least one trench formed in the element-forming region and extending to the first insulating film, second insulating films formed on side walls of the trench, and a film made of a second material, and embedded in only an upper portion of the trench such that a bottom portion of the trench is hollow.
摘要翻译：根据本发明的用于SOI型半导体器件的介电隔离结构包括在第一绝缘膜上形成有元件形成区域的衬底，该区域由第一材料制成，至少一个沟槽形成在元件形成区域并延伸到第一绝缘膜，形成在沟槽的侧壁上的第二绝缘膜和由第二材料制成的膜，并且仅嵌入在沟槽的上部中，使得底部部分沟是空心的

7. 发明授权

US5029324A Semiconductor device having a semiconductive protection layer 失效
标题翻译：具有半导体保护层的半导体器件
公开(公告)号：US5029324A
公开(公告)日：1991-07-02
申请号：US512013
申请日：1990-04-16
申请人： Akihiko Osawa , Yutaka Koshino , Yoshiro Baba
发明人： Akihiko Osawa , Yutaka Koshino , Yoshiro Baba
IPC分类号： H01L21/60 , H01L21/314 , H01L21/768 , H01L23/29 , H01L23/522 , H01L23/532 , H01L29/06 , H01L29/40
CPC分类号： H01L29/408 , H01L23/29 , H01L23/53271 , H01L24/05 , H01L24/48 , H01L2224/04042 , H01L2224/05556 , H01L2224/05624 , H01L2224/05686 , H01L2224/451 , H01L2224/48463 , H01L24/45 , H01L2924/00014 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01023 , H01L2924/01033 , H01L2924/01074 , H01L2924/13091 , H01L2924/3025
摘要： A semiconductor device has a semiconductor region, an electrode layer formed over the semiconductor region, and a protection layer formed to cover the semiconductor region and the electrode layer. In the semiconductor device, the protection layer is a semiconductor protection layer. Part of the semiconductive protection layer is formed thin so as to have a low resistance, permitting a corresponding portion of the electrode layer to be connected to an external bonding wire.

8. 发明授权

US5610422A Semiconductor device having a buried insulated gate 失效
标题翻译：具有掩埋绝缘栅极的半导体器件
公开(公告)号：US5610422A
公开(公告)日：1997-03-11
申请号：US510654
申请日：1995-08-03
申请人： Satoshi Yanagiya , Noboru Matsuda , Yoshiro Baba
发明人： Satoshi Yanagiya , Noboru Matsuda , Yoshiro Baba
IPC分类号： H01L21/336 , H01L29/423 , H01L29/78 , H01L29/76 , H01L31/062
CPC分类号： H01L29/7827 , H01L29/42368 , H01L29/4238
摘要： In a vertical power MOSFET having a U-shaped trench gate and a method of manufacturing the same, a P-type base layer and an N.sup.+ -type emitter layer are formed on the surface of an N-type semiconductor substrate. A plurality of trenches are formed to such a depth as to reach the semiconductor substrate. After that, an oxide film and a nitride film are formed in this order on the surface of the resultant element and on the inner surfaces of the trenches. In this case, the oxide film and nitride film are each formed to have a thickness corresponding to the operating characteristics of the element at the stage of design. The nitride film of a gate wiring region is selectively removed to form an oxide film on the surface of the element. Consequently, a thick gate insulation film of the oxide films can be formed between the corner portions of the N.sup.+ -type emitter layer and a gate electrode wiring layer of the gate wiring region which is to be formed afterward, and the gate-to-source breakdown voltage can be enhanced.
摘要翻译：在具有U形沟槽栅极的垂直功率MOSFET及其制造方法中，在N型半导体衬底的表面上形成P型基极层和N +型发射极层。多个沟槽形成为达到半导体衬底的深度。此后，在所得元件的表面和沟槽的内表面上依次形成氧化物膜和氮化物膜。在这种情况下，氧化膜和氮化物膜各自形成为具有与设计阶段的元件的工作特性对应的厚度。选择性地去除栅极布线区域的氮化物膜以在元件的表面上形成氧化物膜。因此，可以在N +型发射极层的角部与之后形成的栅极配线区域的栅电极配线层之间形成氧化物膜的厚栅极绝缘膜，栅极至源极可以提高击穿电压。

9. 发明授权

US5726088A Method of manufacturing a semiconductor device having a buried insulated gate 失效
标题翻译：制造具有埋入绝缘栅的半导体器件的方法
公开(公告)号：US5726088A
公开(公告)日：1998-03-10
申请号：US746846
申请日：1996-11-15
申请人： Satoshi Yanagiya , Noboru Matsuda , Yoshiro Baba
发明人： Satoshi Yanagiya , Noboru Matsuda , Yoshiro Baba
IPC分类号： H01L21/336 , H01L29/423 , H01L29/78
CPC分类号： H01L29/7827 , H01L29/42368 , H01L29/4238
摘要： In a vertical power MOSFET having a U-shaped trench gate and a method of manufacturing the same, a P-type base layer and an N.sup.+ -type emitter layer are formed on the surface of an N-type semiconductor substrate. A plurality of trenches are formed to such a depth as to reach the semiconductor substrate. After that, an oxide film and a nitride film are formed in this order on the surface of the resultant element and on the inner surfaces of the trenches. In this case, the oxide film and nitride film are each formed to have a thickness corresponding to the operating characteristics of the element at the stage of design. The nitride film of a gate wiring region is selectively removed to form an oxide film on the surface of the element. Consequently, a thick gate insulation film of the oxide films can be formed between the corner portions of the N.sup.+ -type emitter layer and a gate electrode wiring layer of the gate wiring region which is to be formed afterward, and the gate-to-source breakdown voltage can be enhanced.
摘要翻译：在具有U形沟槽栅极的垂直功率MOSFET及其制造方法中，在N型半导体衬底的表面上形成P型基极层和N +型发射极层。多个沟槽形成为达到半导体衬底的深度。此后，在所得元件的表面和沟槽的内表面上依次形成氧化物膜和氮化物膜。在这种情况下，氧化膜和氮化物膜各自形成为具有与设计阶段的元件的工作特性对应的厚度。选择性地去除栅极布线区域的氮化物膜以在元件的表面上形成氧化物膜。因此，可以在N +型发射极层的角部与之后形成的栅极配线区域的栅电极配线层之间形成氧化物膜的厚栅极绝缘膜，栅极至源极可以提高击穿电压。

10. 发明授权

US5770514A Method for manufacturing a vertical transistor having a trench gate 失效
标题翻译：制造具有沟槽栅极的垂直晶体管的方法
公开(公告)号：US5770514A
公开(公告)日：1998-06-23
申请号：US787573
申请日：1997-01-22
申请人： Noboru Matsuda , Yoshiro Baba , Satoshi Yanagiya , Masanobu Tsuchitani
发明人： Noboru Matsuda , Yoshiro Baba , Satoshi Yanagiya , Masanobu Tsuchitani
IPC分类号： H01L29/78 , H01L21/336 , H01L29/423 , H01L29/739 , H01L29/772 , H01L21/3205 , H01L21/4763
CPC分类号： H01L29/7397 , H01L29/7813 , H01L29/4232 , H01L29/4238
摘要： In a vertical field effect transistor having a trench gate and a method of manufacturing the same according to the present invention, p-type base and n.sup.+ -type source diffusion layers are formed in this order in a surface region of an n.sup.31 -type epitaxial layer on an n.sup.+ -type semiconductor substrate. A trench is then provided to such a depth as to penetrate the diffusion layers. A dope polysilicon layer is deposited and buried into the trench with a gate insulation film interposed between them. The polysilicon layer is etched to have the same level as that of the entrance of the trench, and a dope polysilicon layer 18 is selectively grown thereon, thereby forming a trench gate in which an upper corner portion of the trench is not covered with a gate electrode. Consequently, the concentration of electric fields at the corner portion can be mitigated thereby to increase an absolute withstand voltage of the gate and the variations in threshold voltage can be suppressed in a BT test.
摘要翻译：在根据本发明的具有沟槽栅的垂直场效应晶体管及其制造方法中，在n31型外延层的表面区域中依次形成p型基极和n +型源极扩散层在n +型半导体衬底上。然后将沟槽提供到穿透扩散层的深度。将掺杂多晶硅层沉积并埋入沟槽中，并在其间插入栅极绝缘膜。蚀刻多晶硅层以与沟槽的入口具有相同的电平，并且在其上选择性地生长掺杂多晶硅层18，从而形成沟槽栅极，其中沟槽的上角部分未被栅极覆盖电极。因此，可以减轻角部处的电场的集中，从而提高栅极的绝对耐受电压，并且可以在BT测试中抑制阈值电压的变化。

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