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1. 发明授权

US08808562B2 Dry metal etching method 有权
标题翻译：干金属蚀刻方法
公开(公告)号：US08808562B2
公开(公告)日：2014-08-19
申请号：US13230721
申请日：2011-09-12
申请人： Yusuke Ohsawa , Hiroto Ohtake , Eiji Suzuki , Kaushik Arun Kumar , Andrew W. Metz
发明人： Yusuke Ohsawa , Hiroto Ohtake , Eiji Suzuki , Kaushik Arun Kumar , Andrew W. Metz
IPC分类号： B44C1/22 , H01J37/32 , H01L21/3213
CPC分类号： H01L21/32136 , H01J37/3222 , H01J37/32238 , H01J37/32247
摘要： A method of etching an aluminum-containing layer on a substrate is described. The method includes forming plasma from a process composition containing a halogen element, and exposing the substrate to the plasma to etch the aluminum-containing layer. The method may additionally include exposing the substrate to an oxygen-containing environment to oxidize a surface of the aluminum-containing layer and control an etch rate of the aluminum-containing layer. The method may further include forming first plasma from a process composition containing HBr and an additive gas having the chemical formula CxHyRz (wherein R is a halogen element, x and y are equal to unity or greater, and z is equal to zero or greater), forming second plasma from a process composition containing HBr, and exposing the substrate to the first plasma and the second plasma to etch the aluminum-containing layer.
摘要翻译：描述了蚀刻基板上的含铝层的方法。该方法包括从含有卤素元素的工艺组合物形成等离子体，并将该衬底暴露于等离子体以蚀刻含铝层。该方法可以另外包括将基底暴露于含氧环境以氧化含铝层的表面并控制含铝层的蚀刻速率。该方法可以进一步包括从含有HBr的工艺组合物和具有化学式C x H y R z（其中R是卤素元素，x和y等于或大于1，并且z等于或大于0）的添加剂气体形成第一等离子体，从含有HBr的工艺组合物形成第二等离子体，并将衬底暴露于第一等离子体和第二等离子体以蚀刻含铝层。

2. 发明授权

US08809194B2 Formation of SiOCl-containing layer on spacer sidewalls to prevent CD loss during spacer etch 有权
标题翻译：在隔离物侧壁上形成含SiOCl的层，以防止间隔物蚀刻期间的CD损失
公开(公告)号：US08809194B2
公开(公告)日：2014-08-19
申请号：US13413915
申请日：2012-03-07
申请人： Alok Ranjan , Kaushik Arun Kumar
发明人： Alok Ranjan , Kaushik Arun Kumar
IPC分类号： H01L21/302 , H01L21/033 , H01L21/3065 , H01L21/308
CPC分类号： H01L21/0337 , H01J37/32082 , H01J2237/334 , H01L21/0206 , H01L21/02126 , H01L21/02271 , H01L21/02274 , H01L21/3065 , H01L21/3086 , H01L21/31116 , H01L29/6653 , H01L29/6656 , Y10S438/947 , Y10S438/976
摘要： A method for performing a spacer etch process is described. The method includes conformally applying a spacer material over a gate structure on a substrate, and performing a spacer etch process sequence to partially remove the spacer material from the gate structure and the substrate, while retaining a sidewall spacer positioned along a sidewall of the gate structure. The spacer etch process sequence may include depositing a SiOCl-containing layer on an exposed surface of the spacer material to form a spacer protection layer.
摘要翻译：描述了用于执行间隔物蚀刻工艺的方法。该方法包括在衬底上的栅极结构上保形地施加间隔物材料，并且执行间隔物蚀刻工艺顺序以从栅极结构和衬底部分去除间隔物材料，同时保持沿栅极结构的侧壁定位的侧壁间隔物。间隔物蚀刻工艺序列可以包括在间隔物材料的暴露表面上沉积含SiOCl的层以形成间隔物保护层。

3. 发明授权

US08058176B2 Methods of patterning insulating layers using etching techniques that compensate for etch rate variations 有权
标题翻译：使用补偿蚀刻速率变化的蚀刻技术对绝缘层进行图案化的方法
公开(公告)号：US08058176B2
公开(公告)日：2011-11-15
申请号：US11861478
申请日：2007-09-26
申请人： Wan-jae Park , Kaushik Arun Kumar , Joseph Edward Linville , Anthony David Lisi , Ravi Prakash Srivastava , Hermann Willhelm Wendt
发明人： Wan-jae Park , Kaushik Arun Kumar , Joseph Edward Linville , Anthony David Lisi , Ravi Prakash Srivastava , Hermann Willhelm Wendt
IPC分类号： H01L21/311
CPC分类号： H01L21/31116
摘要： Methods of forming integrated circuit devices include forming an integrated circuit substrate having an electrically insulating layer thereon and forming a mask layer pattern having at least first and second openings of different size therein, on the electrically insulating layer. First and second portions of the electrically insulating layer extending opposite the first and second openings, respectively, are simultaneously etched at first and second different etch rates. This etching yields a first trench extending adjacent the first opening that is deeper than a second trench extending adjacent the second opening. Then, the bottoms of the first and second trenches are simultaneously etched to substantially the same depths using an etching process that compensates for the first and second different etch rates.
摘要翻译：形成集成电路器件的方法包括在其上形成具有电绝缘层的集成电路衬底，并在电绝缘层上形成至少具有不同大小的第一和第二开口的掩模层图案。分别与第一和第二开口相对延伸的电绝缘层的第一和第二部分以第一和第二不同的蚀刻速率被同时蚀刻。该蚀刻产生相邻于第一开口延伸的第一沟槽，其比邻近第二开口延伸的第二沟槽更深。然后，使用补偿第一和第二不同蚀刻速率的蚀刻工艺，将第一和第二沟槽的底部同时蚀刻到基本上相同的深度。

4. 发明授权

US08592327B2 Formation of SiOCl-containing layer on exposed low-k surfaces to reduce low-k damage 有权
标题翻译：在暴露的低k表面上形成含SiOCl的层以降低低k损伤
公开(公告)号：US08592327B2
公开(公告)日：2013-11-26
申请号：US13413878
申请日：2012-03-07
申请人： Alok Ranjan , Kaushik Arun Kumar
发明人： Alok Ranjan , Kaushik Arun Kumar
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/02063 , H01L21/02126 , H01L21/02271 , H01L21/02274 , H01L21/31116 , H01L21/31138 , H01L21/76802 , H01L21/76814 , H01L2221/1063
摘要： A method for protecting an exposed low-k surface is described. The method includes receiving a substrate having a mask layer and a low-k layer formed thereon, wherein a pattern formed in the mask layer using a lithographic process has been transferred to the low-k layer using an etching process to form a structural feature therein. Additionally, the method includes forming a SiOCl-containing layer on exposed surfaces of the mask layer and the low-k layer, and anisotropically removing the SiOCl-containing layer from a top surface of the mask layer and a bottom surface of the structural feature in the low-k layer, while retaining a remaining portion of the SiOCl-containing layer on sidewall surfaces of the structural feature. The method further includes performing an ashing process to remove the mask layer, and thereafter, selectively removing the remaining portion of the SiOCl-containing layer from the sidewall surfaces of the structural feature.
摘要翻译：描述了一种用于保护暴露的低k表面的方法。该方法包括接收具有掩模层和形成在其上的低k层的衬底，其中使用光刻工艺在掩模层中形成的图案已经使用蚀刻工艺转移到低k层，以在其中形成结构特征。此外，该方法包括在掩模层和低k层的暴露表面上形成含SiOCl的层，并且从掩模层的顶表面和结构特征的底表面各向异性除去含SiOCl层同时在结构特征的侧壁表面上保留含SiOCl层的剩余部分。该方法还包括进行灰化处理以除去掩模层，然后从结构特征的侧壁表面选择性地除去含SiOCl层的剩余部分。

5. 发明申请

US20090081873A1 Methods of Patterning Insulating Layers Using Etching Techniques that Compensate for Etch Rate Variations 有权
标题翻译：使用补偿蚀刻速率变化的蚀刻技术对绝缘层进行图案化的方法
公开(公告)号：US20090081873A1
公开(公告)日：2009-03-26
申请号：US11861478
申请日：2007-09-26
申请人： Wan-jae Park , Kaushik Arun Kumar , Joseph Edward Linville , Anthony David Lisi , Ravi Prakash Srivastava , Hermann Willhelm Wendt
发明人： Wan-jae Park , Kaushik Arun Kumar , Joseph Edward Linville , Anthony David Lisi , Ravi Prakash Srivastava , Hermann Willhelm Wendt
IPC分类号： H01L21/311
CPC分类号： H01L21/31116
摘要： Methods of forming integrated circuit devices include forming an integrated circuit substrate having an electrically insulating layer thereon and forming a mask layer pattern having at least first and second openings of different size therein, on the electrically insulating layer. First and second portions of the electrically insulating layer extending opposite the first and second openings, respectively, are simultaneously etched at first and second different etch rates. This etching yields a first trench extending adjacent the first opening that is deeper than a second trench extending adjacent the second opening. Then, the bottoms of the first and second trenches are simultaneously etched to substantially the same depths using an etching process that compensates for the first and second different etch rates.
摘要翻译：形成集成电路器件的方法包括在其上形成具有电绝缘层的集成电路衬底，并在电绝缘层上形成至少具有不同大小的第一和第二开口的掩模层图案。分别与第一和第二开口相对延伸的电绝缘层的第一和第二部分以第一和第二不同的蚀刻速率被同时蚀刻。该蚀刻产生相邻于第一开口延伸的第一沟槽，其比邻近第二开口延伸的第二沟槽更深。然后，使用补偿第一和第二不同蚀刻速率的蚀刻工艺，将第一和第二沟槽的底部同时蚀刻到基本上相同的深度。

6. 发明授权

US07358182B2 Method of forming an interconnect structure 失效
标题翻译：形成互连结构的方法
公开(公告)号：US07358182B2
公开(公告)日：2008-04-15
申请号：US11315923
申请日：2005-12-22
申请人： Heidi Lee Baks , Shyng-Tsong Chen , Timothy Joseph Dalton , Nicholas Colvin Masi Fuller , Kaushik Arun Kumar
发明人： Heidi Lee Baks , Shyng-Tsong Chen , Timothy Joseph Dalton , Nicholas Colvin Masi Fuller , Kaushik Arun Kumar
IPC分类号： H01L21/4763
CPC分类号： H01L21/76802 , H01L21/31116 , H01L21/31138 , H01L21/31144 , H01L21/76811
摘要： A method of forming damascene interconnect structure in an organo-silicate glass layer without causing damage to the organo-silicate glass material. The method includes forming a stack of hardmask layers over the organo-silicate glass layer, defining openings in the hardmask and organo-silicate glass layers using a combination of plasma etch and plasma photoresist removal processes and performing one or more additional plasma etch processes that do not include oxygen containing species to etch the openings to depths required for forming the damascene interconnect structures and to remove any organo-silicate material damaged by the combination of plasma etch and plasma photoresist removal processes.
摘要翻译：在有机硅酸盐玻璃层中形成镶嵌互连结构而不会损坏有机硅酸盐玻璃材料的方法。该方法包括在有机硅酸盐玻璃层上形成硬掩模层堆叠，使用等离子体蚀刻和等离子体光致抗蚀剂去除方法的组合在硬掩模和有机硅酸盐玻璃层中限定开口，并执行一个或多个额外的等离子体蚀刻工艺不包括含氧物质，以将开口蚀刻到形成镶嵌互连结构所需的深度，并除去由等离子体蚀刻和等离子体光致抗蚀剂去除工艺的组合损坏的任何有机硅酸盐材料。

7. 发明授权

US08551877B2 Sidewall and chamfer protection during hard mask removal for interconnect patterning 有权
标题翻译：用于互连图案化的硬掩模去除期间的侧壁和倒角保护
公开(公告)号：US08551877B2
公开(公告)日：2013-10-08
申请号：US13414015
申请日：2012-03-07
申请人： Alok Ranjan , Kaushik Arun Kumar
发明人： Alok Ranjan , Kaushik Arun Kumar
IPC分类号： H01L21/4763 , H01L23/532
CPC分类号： H01L21/76811 , H01L21/02063 , H01L21/02126 , H01L21/02271 , H01L21/02274 , H01L21/31116 , H01L21/31144 , H01L21/76808 , H01L21/76814 , H01L2221/1063
摘要： A method for method for removing a hard mask is described. The method includes forming at least a portion of a trench-via structure in a low-k insulation layer on a substrate using one or more etching processes and a hard mask layer overlying the low-k insulation layer. Thereafter, the method includes depositing a SiOCl-containing layer on exposed surfaces of the trench-via structure to form an insulation protection layer, performing one or more etching processes to anisotropically remove at least a portion of the SiOCl-containing layer from at least one surface on the trench-via structure, and removing the hard mask layer using a mask removal etching process.
摘要翻译：描述了用于去除硬掩模的方法的方法。该方法包括使用一个或多个蚀刻工艺和覆盖低k绝缘层的硬掩模层，在衬底上的低k绝缘层中形成沟槽通孔结构的至少一部分。此后，该方法包括在沟槽通孔结构的暴露表面上沉积含SiOCl的层以形成绝缘保护层，执行一个或多个蚀刻工艺以使至少一部分含SiOCl层从至少一个沟槽通孔结构的表面，并且使用掩模去除蚀刻工艺去除硬掩模层。

8. 发明授权

US07253098B2 Maintaining uniform CMP hard mask thickness 有权
标题翻译：保持均匀的CMP硬掩模厚度
公开(公告)号：US07253098B2
公开(公告)日：2007-08-07
申请号：US10711145
申请日：2004-08-27
申请人： Shyng-Tsong T. Chen , Kaushik Arun Kumar , Stephen Edward Greco , Shom Ponoth , Terry Allen Spooner , David L. Rath , Wei-Tsu Tseng
发明人： Shyng-Tsong T. Chen , Kaushik Arun Kumar , Stephen Edward Greco , Shom Ponoth , Terry Allen Spooner , David L. Rath , Wei-Tsu Tseng
IPC分类号： H01L21/4763
CPC分类号： H01L21/7684 , H01L21/3212 , H01L21/76832 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A chemical mechanical polishing (CMP) step is used to remove excess conductive material (e.g., Cu) overlying a low-k or ultralow-k interlevel dielectric layer (ILD) layer having trenches filled with conductive material, for a damascene interconnect structure. A reactive ion etch (RIE) or a Gas Cluster Ion Beam (GCIB) process is used to remove a portion of a liner which is atop a hard mask. A wet etch step is used to remove an oxide portion of the hard mask overlying the ILD, followed by a final touch-up Cu CMP (CMP) step which chops the protruding Cu patterns off and lands on the SiCOH hard mask. In this manner, processes used to remove excess conductive material substantially do not affect the portion of the hard mask overlying the interlevel dielectric layer.
摘要翻译：化学机械抛光（CMP）步骤用于去除覆盖在具有填充有导电材料的沟槽的低k或超低k层间介质层（ILD）层上的过剩导电材料（例如Cu），用于镶嵌互连结构。使用反应离子蚀刻（RIE）或气体簇离子束（GCIB）方法去除位于硬掩模顶部的衬垫的一部分。使用湿蚀刻步骤去除覆盖在ILD上的硬掩模的氧化物部分，随后是最后的上覆Cu CMP（CMP）步骤，其将突出的Cu图案切掉并落在SiCOH硬掩模上。以这种方式，用于去除过量的导电材料的工艺基本上不影响覆盖层间电介质层的硬掩模的部分。

9. 发明授权

US07084479B2 Line level air gaps 失效
公开(公告)号：US07084479B2
公开(公告)日：2006-08-01
申请号：US10731377
申请日：2003-12-08
申请人： Shyng-Tsong Chen , Stefanie Ruth Chiras , Matthew Earl Colburn , Timothy Joseph Dalton , Jeffrey Curtis Hedrick , Elbert Emin Huang , Kaushik Arun Kumar , Michael Wayne Lane , Kelly Malone , Chandrasekhar Narayan , Satyanarayana Venkata Nitta , Sampath Purushothaman , Robert Rosenburg , Christy Sensenich Tyberg , Roy RongQing Yu
发明人： Shyng-Tsong Chen , Stefanie Ruth Chiras , Matthew Earl Colburn , Timothy Joseph Dalton , Jeffrey Curtis Hedrick , Elbert Emin Huang , Kaushik Arun Kumar , Michael Wayne Lane , Kelly Malone , Chandrasekhar Narayan , Satyanarayana Venkata Nitta , Sampath Purushothaman , Robert Rosenburg , Christy Sensenich Tyberg , Roy RongQing Yu
IPC分类号： H01L29/00 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/7682 , H01L21/76829 , H01L23/5222 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： In a multilevel microelectronic integrated circuit, air comprises permanent line level dielectric and ultra low-K materials are via level dielectric. The air is supplied to line level subsequent to removal of sacrificial material by clean thermal decomposition and assisted diffusion of byproducts through porosities in the IC structure. Optionally, air is also included within porosities in the via level dielectric. By incorporating air to the extent produced in the invention, intralevel and interlevel dielectric values are minimized.

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