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1. 发明申请

US20060291110A1 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US20060291110A1
公开(公告)日：2006-12-28
申请号：US11447168
申请日：2006-06-06
申请人： Yusuke Kanno , Hiroyuki Mizuno , Yoshihiko Yasu , Kenji Hirose , Takahiro Irita
发明人： Yusuke Kanno , Hiroyuki Mizuno , Yoshihiko Yasu , Kenji Hirose , Takahiro Irita
IPC分类号： H02H7/00
CPC分类号： H01L27/11898 , G06F17/5068 , G06F17/5072 , G11C11/419 , H01L23/48 , H01L23/50 , H01L23/528 , H01L27/00 , H01L27/02 , H01L27/0203 , H01L27/0207 , H01L27/11807 , H01L29/7835 , H01L2027/11881 , H01L2924/0002 , H03K3/0315 , H03K3/0375 , H03K17/16 , H01L2924/00
摘要： A semiconductor integrated circuit device is provided, the circuit being capable of arranging a control signal system, avoiding a danger of failure to check an indefinite signal propagation prevention circuit or the like, further facilitating a check oriented to mounting on an automated tool, and facilitating power shutdown control inside of a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains Area A to Area I. A rule is provided, the rule defining that, in the case where a circuit having a high priority is turned ON, a power domain having its lower priority cannot be turned OFF, thereby facilitating a designing method. In addition, areas capable of applying still another power supply are provided in the independent power areas Area A to Area I. In that area, a relay buffer (repeater) and a clock buffer or an information retaining latch for saving information are integrated. A layout may be provided in a direction vertical to a direction in which cells are arranged in a row direction for the purpose of dispersing a current of a light supply line.
摘要翻译：提供了一种半导体集成电路器件，该电路能够布置控制信号系统，避免不能检查不确定的信号传播防止电路等的危险，进一步便于针对安装在自动化工具上的检查，并且促进功率关断控制芯片内部。在半导体集成电路装置中，功率关闭优先级由独立的电源区域A至区域I提供。规定了在具有高优先级的电路被接通的情况下，规定了具有其较低优先级不能关闭，从而有助于设计方法。此外，在独立电源区域A至区域I中提供能够应用另一电源的区域。在该区域中，集成了用于保存信息的中继缓冲器（中继器）和时钟缓冲器或信息保持锁存器。为了分散供电线的电流，布置可以沿垂直于单元布置在行方向上的方向设置。

2. 发明授权

US07610572B2 Semiconductor integrated circuit device with independent power domains 有权
标题翻译：具有独立电源域的半导体集成电路器件
公开(公告)号：US07610572B2
公开(公告)日：2009-10-27
申请号：US11447168
申请日：2006-06-06
申请人： Yusuke Kanno , Hiroyuki Mizuno , Yoshihiko Yasu , Kenji Hirose , Takahiro Irita
发明人： Yusuke Kanno , Hiroyuki Mizuno , Yoshihiko Yasu , Kenji Hirose , Takahiro Irita
IPC分类号： G06F17/50 , H01L25/00
CPC分类号： H01L27/11898 , G06F17/5068 , G06F17/5072 , G11C11/419 , H01L23/48 , H01L23/50 , H01L23/528 , H01L27/00 , H01L27/02 , H01L27/0203 , H01L27/0207 , H01L27/11807 , H01L29/7835 , H01L2027/11881 , H01L2924/0002 , H03K3/0315 , H03K3/0375 , H03K17/16 , H01L2924/00
摘要： A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.
摘要翻译：一种具有控制信号系统的半导体集成电路装置，用于避免无法检查不确定信号传播防止电路的故障，以便于包括在自动化工具中的检查，以及便于芯片内的电源关闭控制。在半导体集成电路器件中，功率关断优先级由独立电源域（A区至I区）提供。还提供了当具有高优先级的电路被接通时，防止具有较低优先级的功率域被关断的方法。

3. 发明申请

US20100017775A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：半导体集成电路设备
公开(公告)号：US20100017775A1
公开(公告)日：2010-01-21
申请号：US12566323
申请日：2009-09-24
申请人： Yusuke KANNO , Hiroyuki Mizuno , Yoshihiko Yasu , Kenji Hirose , Takahiro Irita
发明人： Yusuke KANNO , Hiroyuki Mizuno , Yoshihiko Yasu , Kenji Hirose , Takahiro Irita
IPC分类号： G06F17/50 , H02H9/00 , H01L25/00
CPC分类号： H01L27/11898 , G06F17/5068 , G06F17/5072 , G11C11/419 , H01L23/48 , H01L23/50 , H01L23/528 , H01L27/00 , H01L27/02 , H01L27/0203 , H01L27/0207 , H01L27/11807 , H01L29/7835 , H01L2027/11881 , H01L2924/0002 , H03K3/0315 , H03K3/0375 , H03K17/16 , H01L2924/00
摘要： A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.
摘要翻译：一种具有控制信号系统的半导体集成电路装置，用于避免无法检查不确定信号传播防止电路的故障，以便于包括在自动化工具中的检查，以及便于芯片内的电源关闭控制。在半导体集成电路器件中，功率关断优先级由独立电源域（A区至I区）提供。还提供了当具有高优先级的电路被接通时，防止具有较低优先级的功率域被关断的方法。

4. 发明授权

US08441095B2 Semiconductor device having a ring oscillator and MISFET for converting voltage fluctuation to frequency fluctuation 有权
标题翻译：具有用于将电压波动转换为频率波动的环形振荡器和MISFET的半导体器件
公开(公告)号：US08441095B2
公开(公告)日：2013-05-14
申请号：US13438347
申请日：2012-04-03
申请人： Yusuke Kanno , Hiroyuki Mizuno , Yoshihiko Yasu , Kenji Hirose , Takahiro Irita
发明人： Yusuke Kanno , Hiroyuki Mizuno , Yoshihiko Yasu , Kenji Hirose , Takahiro Irita
IPC分类号： H01L29/66 , H01L21/70 , H01L25/00
CPC分类号： H01L27/11898 , G06F17/5068 , G06F17/5072 , G11C11/419 , H01L23/48 , H01L23/50 , H01L23/528 , H01L27/00 , H01L27/02 , H01L27/0203 , H01L27/0207 , H01L27/11807 , H01L29/7835 , H01L2027/11881 , H01L2924/0002 , H03K3/0315 , H03K3/0375 , H03K17/16 , H01L2924/00
摘要： A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.
摘要翻译：一种具有控制信号系统的半导体集成电路装置，用于避免无法检查不确定信号传播防止电路的故障，以便于包括在自动化工具中的检查，以及便于芯片内的电源关闭控制。在半导体集成电路器件中，功率关断优先级由独立电源域（A区至I区）提供。还提供了当具有高优先级的电路被接通时，防止具有较低优先级的功率域被关断的方法。

5. 发明申请

US20120187981A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：半导体集成电路设备
公开(公告)号：US20120187981A1
公开(公告)日：2012-07-26
申请号：US13438347
申请日：2012-04-03
申请人： Yusuke Kanno , Hiroyuki Mizuno , Yoshihiko Yasu , Kenji Hirose , Takahiro Irita
发明人： Yusuke Kanno , Hiroyuki Mizuno , Yoshihiko Yasu , Kenji Hirose , Takahiro Irita
IPC分类号： H02M1/00
CPC分类号： H01L27/11898 , G06F17/5068 , G06F17/5072 , G11C11/419 , H01L23/48 , H01L23/50 , H01L23/528 , H01L27/00 , H01L27/02 , H01L27/0203 , H01L27/0207 , H01L27/11807 , H01L29/7835 , H01L2027/11881 , H01L2924/0002 , H03K3/0315 , H03K3/0375 , H03K17/16 , H01L2924/00
摘要： A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.
摘要翻译：一种具有控制信号系统的半导体集成电路装置，用于避免无法检查不确定信号传播防止电路的故障，以便于包括在自动化工具中的检查，以及便于芯片内的电源关闭控制。在半导体集成电路器件中，功率关断优先级由独立电源域（A区至I区）提供。还提供了当具有高优先级的电路被接通时，防止具有较低优先级的功率域被关断的方法。

6. 发明授权

US08169036B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US08169036B2
公开(公告)日：2012-05-01
申请号：US13225401
申请日：2011-09-02
申请人： Yusuke Kanno , Hiroyuki Mizuno , Yoshihiko Yasu , Kenji Hirose , Takahiro Irita
发明人： Yusuke Kanno , Hiroyuki Mizuno , Yoshihiko Yasu , Kenji Hirose , Takahiro Irita
IPC分类号： H01L27/088
CPC分类号： H01L27/11898 , G06F17/5068 , G06F17/5072 , G11C11/419 , H01L23/48 , H01L23/50 , H01L23/528 , H01L27/00 , H01L27/02 , H01L27/0203 , H01L27/0207 , H01L27/11807 , H01L29/7835 , H01L2027/11881 , H01L2924/0002 , H03K3/0315 , H03K3/0375 , H03K17/16 , H01L2924/00
摘要： A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.
摘要翻译：一种具有控制信号系统的半导体集成电路装置，用于避免无法检查不确定信号传播防止电路的故障，以便于包括在自动化工具中的检查，以及便于芯片内的电源关闭控制。在半导体集成电路器件中，功率关断优先级由独立电源域（A区至I区）提供。还提供了当具有高优先级的电路被接通时，防止具有较低优先级的功率域被关断的方法。

7. 发明授权

US08026570B2 Semiconductor integrated circuit device having power switch controller with gate insulator thickness for controlling multiple power switches 有权
标题翻译：具有用于控制多个电源开关的具有栅绝缘体厚度的电源开关控制器的半导体集成电路器件
公开(公告)号：US08026570B2
公开(公告)日：2011-09-27
申请号：US12566323
申请日：2009-09-24
申请人： Yusuke Kanno , Hiroyuki Mizuno , Yoshihiko Yasu , Kenji Hirose , Takahiro Irita
发明人： Yusuke Kanno , Hiroyuki Mizuno , Yoshihiko Yasu , Kenji Hirose , Takahiro Irita
IPC分类号： H01L21/70 , H01L29/76 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11898 , G06F17/5068 , G06F17/5072 , G11C11/419 , H01L23/48 , H01L23/50 , H01L23/528 , H01L27/00 , H01L27/02 , H01L27/0203 , H01L27/0207 , H01L27/11807 , H01L29/7835 , H01L2027/11881 , H01L2924/0002 , H03K3/0315 , H03K3/0375 , H03K17/16 , H01L2924/00
摘要： A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.
摘要翻译：一种具有控制信号系统的半导体集成电路装置，用于避免无法检查不确定信号传播防止电路的故障，以便于包括在自动化工具中的检查，以及便于芯片内的电源关闭控制。在半导体集成电路器件中，功率关断优先级由独立电源域（A区至I区）提供。还提供了当具有高优先级的电路被接通时，防止具有较低优先级的功率域被关断的方法。

8. 发明申请

US20070210404A1 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US20070210404A1
公开(公告)日：2007-09-13
申请号：US11652013
申请日：2007-01-11
申请人： Satoshi Umekita , Tomomi Ajioka , Kenji Hirose , Yoshihiko Yasu , Yujiro Miyairi
发明人： Satoshi Umekita , Tomomi Ajioka , Kenji Hirose , Yoshihiko Yasu , Yujiro Miyairi
IPC分类号： H01L29/00
CPC分类号： H01L27/0203
摘要： Repeaters are arranged at arbitrary positions to substantially improve transmission speed of a signal. In the semiconductor integrated circuit device 1, repeater regions 10 where repeaters are provided as relay points for wiring are provided in the central parts of the core power source regions 2, 3 and 5, on the left side of the core power source regions 4 to 8 and at the upper and lower parts of the semiconductor integrated circuit device 1. A power switch region for repeater 11 is formed so as to surround the core power source regions 2 to 8 and the repeater regions 10. The power source lines of the reference potential connected to the repeater regions 10 are laid out at equally spaced intervals throughout the core power source regions 2 to 8, which enables the repeater regions 10 to be flexibly laid out. This permits the repeaters to be more effectively arranged, which improves the performances of semiconductor integrated circuit device 1.
摘要翻译：中继器被布置在任意位置以显着提高信号的传输速度。在半导体集成电路装置1中，在核心电源区域2,3和5的核心电源区域4的左侧设置有作为布线用继电器点的中继器的中继器区域10，半导体集成电路装置1的上部和下部。中继器11的电源开关区域形成为围绕核心电源区域2至8和中继器区域10.参考电源线连接到中继器区域10的电位在整个核心电源区域2至8中以均匀间隔布置，这使得中继器区域10能够被灵活布置。这允许更有效地布置中继器，这改善了半导体集成电路装置1的性能。

9. 发明申请

US20080224177A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：半导体集成电路设备
公开(公告)号：US20080224177A1
公开(公告)日：2008-09-18
申请号：US12126019
申请日：2008-05-23
申请人： Satoshi Umekita , Tomomi Ajioka , Kenji Hirose , Yoshihiko Yasu , Yujiro Miyairi
发明人： Satoshi Umekita , Tomomi Ajioka , Kenji Hirose , Yoshihiko Yasu , Yujiro Miyairi
IPC分类号： H01L27/10
CPC分类号： H01L27/0203
摘要： Repeaters are arranged at arbitrary positions to substantially improve transmission speed of a signal. In the semiconductor integrated circuit device 1, repeater regions 10 where repeaters are provided as relay points for wiring are provided in the central parts of the core power source regions 2, 3 and 5, on the left side of the core power source regions 4 to 8 and at the upper and lower parts of the semiconductor integrated circuit device 1. A power switch region for repeater 11 is formed so as to surround the core power source regions 2 to 8 and the repeater regions 10. The power source lines of the reference potential connected to the repeater regions 10 are laid out at equally spaced intervals throughout the core power source regions 2 to 8, which enables the repeater regions 10 to be flexibly laid out. This permits the repeaters to be more effectively arranged, which improves the performances of semiconductor integrated circuit device 1.
摘要翻译：中继器被布置在任意位置以显着提高信号的传输速度。在半导体集成电路装置1中，在核心电源区域2,3和5的核心电源区域4的左侧设置有作为布线用继电器点的中继器的中继器区域10，并且在半导体集成电路装置1的上部和下部。中继器11的电源开关区域形成为围绕核心电源区域2至8和中继器区域10。连接到中继器区域10的参考电位的电源线在整个核心电源区域2至8中以均匀间隔布置，这使得中继器区域10能够被灵活布置。这允许更有效地布置中继器，这改善了半导体集成电路装置1的性能。

10. 发明授权

US07394143B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US07394143B2
公开(公告)日：2008-07-01
申请号：US11652013
申请日：2007-01-11
申请人： Satoshi Umekita , Tomomi Ajioka , Kenji Hirose , Yoshihiko Yasu , Yujiro Miyairi
发明人： Satoshi Umekita , Tomomi Ajioka , Kenji Hirose , Yoshihiko Yasu , Yujiro Miyairi
IPC分类号： H01L29/00
CPC分类号： H01L27/0203
摘要： Repeaters are arranged at arbitrary positions to substantially improve transmission speed of a signal. In the semiconductor integrated circuit device 1, repeater regions 10 where repeaters are provided as relay points for wiring are provided in the central parts of the core power source regions 2, 3 and 5, on the left side of the core power source regions 4 to 8 and at the upper and lower parts of the semiconductor integrated circuit device 1. A power switch region for repeater 11 is formed so as to surround the core power source regions 2 to 8 and the repeater regions 10. The power source lines of the reference potential connected to the repeater regions 10 are laid out at equally spaced intervals throughout the core power source regions 2 to 8, which enables the repeater regions 10 to be flexibly laid out. This permits the repeaters to be more effectively arranged, which improves the performances of semiconductor integrated circuit device 1.
摘要翻译：中继器被布置在任意位置以显着提高信号的传输速度。在半导体集成电路装置1中，在核心电源区域2,3和5的核心电源区域4的左侧设置有作为布线用继电器点的中继器的中继器区域10，并且在半导体集成电路装置1的上部和下部。中继器11的电源开关区域形成为围绕核心电源区域2至8和中继器区域10。连接到中继器区域10的参考电位的电源线在整个核心电源区域2至8中以均匀间隔布置，这使得中继器区域10能够被灵活布置。这允许更有效地布置中继器，这改善了半导体集成电路装置1的性能。

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