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1. 发明授权

US08850437B2 Two-pass linear complexity task scheduler 有权
标题翻译：双通线性复杂度任务调度器
公开(公告)号：US08850437B2
公开(公告)日：2014-09-30
申请号：US13290299
申请日：2011-11-07
申请人： Yurii S. Shutkin , Pavel A. Aliseychik , Elyar E. Gasanov , Ilya V. Neznanov , Andrey P. Sokolov , Pavel A. Panteleev
发明人： Yurii S. Shutkin , Pavel A. Aliseychik , Elyar E. Gasanov , Ilya V. Neznanov , Andrey P. Sokolov , Pavel A. Panteleev
IPC分类号： G06F9/46 , G06F9/50
CPC分类号： G06F9/5066
摘要： A method for two-pass scheduling of a plurality of tasks generally including steps (A) to (C). Step (A) may assign each of the tasks to a corresponding one or more of a plurality of processors in a first pass through the tasks. The first pass may be non-iterative. Step (B) may reassign the tasks among the processors to shorten a respective load on one or more of the processors in a second pass through the tasks. The second pass may be non-iterative and may begin after the first pass has completed. Step (C) may generate a schedule in response to the assigning and the reassigning. The schedule generally maps the tasks to the processors.
摘要翻译：一种通常包括步骤（A）至（C）的多个任务的二次调度的方法。在第一次通过任务时，步骤（A）可以将每个任务分配给多个处理器中相应的一个或多个处理器。第一遍可能是非迭代的。步骤（B）可以在处理器之间重新分配任务，以在通过任务的第二次通过中缩短一个或多个处理器上的相应负载。第二遍可能是非迭代的，并且可以在第一遍完成之后开始。步骤（C）可以产生响应于分配和重新分配的时间表。计划通常将任务映射到处理器。

2. 发明申请

US20120284731A1 TWO-PASS LINEAR COMPLEXITY TASK SCHEDULER 有权
标题翻译：双通道线性复杂度任务调度器
公开(公告)号：US20120284731A1
公开(公告)日：2012-11-08
申请号：US13290299
申请日：2011-11-07
申请人： Yurii S. Shutkin , Pavel A. Aliseychik , Elyar E. Gasanov , Ilya V. Neznanov , Andrey P. Sokolov , Pavel A. Panteleev
发明人： Yurii S. Shutkin , Pavel A. Aliseychik , Elyar E. Gasanov , Ilya V. Neznanov , Andrey P. Sokolov , Pavel A. Panteleev
IPC分类号： G06F9/50
CPC分类号： G06F9/5066
摘要： A method for two-pass scheduling of a plurality of tasks generally including steps (A) to (C). Step (A) may assign each of the tasks to a corresponding one or more of a plurality of processors in a first pass through the tasks. The first pass may be non-iterative. Step (B) may reassign the tasks among the processors to shorten a respective load on one or more of the processors in a second pass through the tasks. The second pass may be non-iterative and may begin after the first pass has completed. Step (C) may generate a schedule in response to the assigning and the reassigning. The schedule generally maps the tasks to the processors.
摘要翻译：一种通常包括步骤（A）至（C）的多个任务的二次调度的方法。在第一次通过任务时，步骤（A）可以将每个任务分配给多个处理器中相应的一个或多个处理器。第一遍可能是非迭代的。步骤（B）可以在处理器之间重新分配任务，以在通过任务的第二次通过中缩短一个或多个处理器上的相应负载。第二遍可能是非迭代的，并且可以在第一遍完成之后开始。步骤（C）可以产生响应于分配和重新分配的时间表。计划通常将任务映射到处理器。

3. 发明授权

US08868890B2 No-delay microsequencer 有权
标题翻译：无延迟微定序器
公开(公告)号：US08868890B2
公开(公告)日：2014-10-21
申请号：US13106119
申请日：2011-05-12
申请人： Yurii S. Shutkin , Elyar E. Gasanov , Ilya V. Neznanov , Andrey P. Sokolov , Pavel A. Panteleev
发明人： Yurii S. Shutkin , Elyar E. Gasanov , Ilya V. Neznanov , Andrey P. Sokolov , Pavel A. Panteleev
IPC分类号： G06F9/30 , G06F9/32
CPC分类号： G06F9/322 , G06F9/30054 , G06F9/30065
摘要： An apparatus generally including a memory and a circuit is disclosed. The memory may be configured to store a plurality of instructions. Each of the instructions generally includes a corresponding command and a corresponding command repeat count. At least one of the instructions may include a subprocedure call. The circuit may be configured to (i) decode the instructions one at a time and (ii) present a sequence of the commands at an interface. The sequence (i) may be based on the decoding and (ii) may have no delays between consecutive the commands at the interface.
摘要翻译：通常包括存储器和电路的装置被公开。存储器可以被配置为存储多个指令。每个指令通常包括相应的命令和相应的命令重复计数。指令中的至少一个可以包括子过程调用。电路可以被配置为（i）一次解码指令，以及（ii）在接口处呈现一系列命令。序列（i）可以基于解码，并且（ii）在接口的连续命令之间可以没有延迟。

4. 发明授权

US08842784B2 L-value generation in a decoder 有权
标题翻译：解码器中的L值生成
公开(公告)号：US08842784B2
公开(公告)日：2014-09-23
申请号：US13115359
申请日：2011-05-25
申请人： Andrey P. Sokolov , Pavel A. Panteleev , Elyar E. Gasanov , Ilya V. Neznanov , Yurii S. Shutkin
发明人： Andrey P. Sokolov , Pavel A. Panteleev , Elyar E. Gasanov , Ilya V. Neznanov , Yurii S. Shutkin
IPC分类号： H03M13/03 , H03M13/00 , H03M13/39 , H03M13/29
CPC分类号： H03M13/296 , H03M13/3927 , H03M13/3988 , H03M13/6525 , H03M13/6544
摘要： An apparatus having a first circuit, a second circuit and a third circuit is disclosed. The first circuit may be configured to generate a plurality of load values corresponding to a trellis of a decoding process. The second circuit generally includes a plurality of calculation layers. The calculation layers may be configured to generate a plurality of maximum values in response to the load values. The third circuit may be configured to generate a plurality of L-values of the decoding process in response to the maximum values.
摘要翻译：公开了一种具有第一电路，第二电路和第三电路的装置。第一电路可以被配置为产生对应于解码处理格架的多个负载值。第二电路通常包括多个计算层。计算层可以被配置为响应于负载值产生多个最大值。第三电路可以被配置为响应于最大值产生解码处理的多个L值。

5. 发明授权

US08621329B2 Reconfigurable BCH decoder 有权
标题翻译：可重构BCH解码器
公开(公告)号：US08621329B2
公开(公告)日：2013-12-31
申请号：US13044809
申请日：2011-03-10
申请人： Pavel A. Panteleev , Elyar E. Gasanov , Ilya V. Neznanov , Andrey P. Sokolov , Yurii S. Shutkin
发明人： Pavel A. Panteleev , Elyar E. Gasanov , Ilya V. Neznanov , Andrey P. Sokolov , Yurii S. Shutkin
IPC分类号： H03M13/00
CPC分类号： H03M13/6516 , H03M13/152 , H03M13/1525 , H03M13/6561
摘要： An apparatus generally having a port, a first circuit and a second circuit is disclosed. The port may be configured to receive a current length of a codeword. The current length may be less than a maximum length of the codeword that the apparatus is designed to decode. The first circuit may be configured to calculate in parallel (i) a sequence of intermediate syndromes from the codeword and (ii) a sequence of correction values based on the current length. The second circuit may be configured to generate a particular number of updated syndromes by modifying the intermediate syndromes with the correction values. The particular number is generally twice a maximum error limit of the codeword.
摘要翻译：公开了一种通常具有端口，第一电路和第二电路的装置。端口可以被配置为接收码字的当前长度。当前长度可以小于设备被设计为解码的码字的最大长度。第一电路可以被配置为并行计算（i）来自码字的中间综合征序列，以及（ii）基于当前长度的校正值序列。第二电路可以被配置为通过用修正值修改中间综合征来生成特定数量的更新的综合征。特定数字通常是码字的最大误差限制的两倍。

6. 发明授权

US08656206B2 Timer manager architecture based on binary heap 有权
标题翻译：基于二进制堆的定时器管理器架构
公开(公告)号：US08656206B2
公开(公告)日：2014-02-18
申请号：US13282781
申请日：2011-10-27
申请人： Elyar E. Gasanov , Ilya V. Neznanov , Yurii S. Shutkin , Andrey P. Sokolov , Pavel A. Panteleev
发明人： Elyar E. Gasanov , Ilya V. Neznanov , Yurii S. Shutkin , Andrey P. Sokolov , Pavel A. Panteleev
IPC分类号： G06F1/00 , G06F1/14
CPC分类号： G06F1/14
摘要： An apparatus having a first memory and a circuit is disclosed. The first memory may be configured to store a plurality of timers. Each of the timers may have a respective value that indicates an expiration time. A first one of the timers nearest to expiring is generally stored at a first address of the first memory. The circuit may be configured to (i) assert a signal in response to the respective value of the first timer matching a counter of time, (ii) read a second of the timers and a third of the timers both from a second address of the first memory, (iii) sort the second timer and the third timer to determine which expires next and (iv) replace the first timer by writing one of the second timer or the third timer that expires next into the first memory at the first address.
摘要翻译：公开了一种具有第一存储器和电路的装置。第一存储器可以被配置为存储多个定时器。每个定时器可以具有指示过期时间的相应值。最接近到期的定时器中的第一个通常存储在第一存储器的第一地址处。电路可以被配置为（i）响应于与时间计数器匹配的第一定时器的相应值来声明信号，（ii）从定时器的第二地址读取定时器中的第二定时器和三分之一的定时器，第一存储器，（iii）对第二定时器和第三定时器进行排序以确定下一个到期;以及（iv）通过将第二定时器或第三定时器之一写入第一存储器中的第一定时器来替换第一定时器。

7. 发明申请

US20130019139A1 VARIABLE PARITY ENCODER 有权
标题翻译：可变奇偶编码器
公开(公告)号：US20130019139A1
公开(公告)日：2013-01-17
申请号：US13351362
申请日：2012-01-17
申请人： Pavel A. Panteleev , Elyar E. Gasanov , Ilya V. Neznanov , Andrey P. Sokolov , Yurii S. Shutkin
发明人： Pavel A. Panteleev , Elyar E. Gasanov , Ilya V. Neznanov , Andrey P. Sokolov , Yurii S. Shutkin
IPC分类号： G06F11/10
CPC分类号： H03M13/1515 , H03M7/40 , H03M7/4031 , H03M7/4093 , H03M13/15 , H03M13/152 , H03M13/35 , H03M13/3707 , H03M13/611 , H03M13/617 , H03M13/6318 , H03M13/6516 , H04L1/0047
摘要： An apparatus generally having a plurality of first circuits and a second circuit is disclosed. The first circuits may be configured to (i) generate a plurality of intermediate bits by dividing a plurality data bits by a plurality of minimal polynomials of an encoding along a first path and (ii) generate a plurality of parity bits by multiplying the intermediate bits by the minimal polynomials along a second path. A number of the parity bits may be variable based on a configuration signal. The second circuit may be configured to (i) delay the data bits and (ii) generate a plurality of code bits by appending the parity bits to a last of the data bits.
摘要翻译：公开了一种通常具有多个第一电路和第二电路的装置。第一电路可以被配置为（i）通过沿着第一路径将多个数据位除以编码的多个最小多项式来生成多个中间位，以及（ii）通过将中间位相乘来生成多个奇偶校验位通过沿着第二路径的最小多项式。基于配置信号，奇偶校验位数可以是可变的。第二电路可以被配置为（i）延迟数据位，并且（ii）通过将奇偶校验位附加到最后一个数据位来产生多个代码位。

8. 发明申请

US20120278648A1 TIMER MANAGER ARCHITECTURE BASED ON BINARY HEAP 有权
标题翻译：基于二进制的定时器管理器架构
公开(公告)号：US20120278648A1
公开(公告)日：2012-11-01
申请号：US13282781
申请日：2011-10-27
申请人： Elyar E. Gasanov , Ilya V. Neznanov , Yurii S. Shutkin , Andrey P. Sokolov , Pavel A. Panteleev
发明人： Elyar E. Gasanov , Ilya V. Neznanov , Yurii S. Shutkin , Andrey P. Sokolov , Pavel A. Panteleev
IPC分类号： G06F1/14
CPC分类号： G06F1/14
摘要： An apparatus having a first memory and a circuit is disclosed. The first memory may be configured to store a plurality of timers. Each of the timers may have a respective value that indicates an expiration time. A first one of the timers nearest to expiring is generally stored at a first address of the first memory. The circuit may be configured to (i) assert a signal in response to the respective value of the first timer matching a counter of time, (ii) read a second of the timers and a third of the timers both from a second address of the first memory, (iii) sort the second timer and the third timer to determine which expires next and (iv) replace the first timer by writing one of the second timer or the third timer that expires next into the first memory at the first address.
摘要翻译：公开了一种具有第一存储器和电路的装置。第一存储器可以被配置为存储多个定时器。每个定时器可以具有指示过期时间的相应值。最接近到期的定时器中的第一个通常存储在第一存储器的第一地址处。电路可以被配置为（i）响应于与时间计数器匹配的第一定时器的相应值来声明信号，（ii）从定时器的第二地址读取定时器中的第二定时器和三分之一的定时器，第一存储器，（iii）对第二定时器和第三定时器进行排序以确定下一个到期;以及（iv）通过将第二定时器或第三定时器之一写入第一存储器中的第一定时器来替换第一定时器。

9. 发明授权

US09319181B2 Parallel decoder for multiple wireless standards 有权
标题翻译：并行解码器，适用于多种无线标准
公开(公告)号：US09319181B2
公开(公告)日：2016-04-19
申请号：US13291285
申请日：2011-11-08
申请人： Andrey P. Sokolov , Elyar E. Gasanov , Pavel A. Panteleev , Ilya V. Neznanov , Yurii S. Shutkin
发明人： Andrey P. Sokolov , Elyar E. Gasanov , Pavel A. Panteleev , Ilya V. Neznanov , Yurii S. Shutkin
IPC分类号： H03K9/00 , H04B1/38 , H04L1/00
CPC分类号： H04L1/0054 , H04L1/0052 , H04L1/0059 , H04L1/0066
摘要： A method of parallel decoding for a plurality of communications standards generally including steps (A) to (C) is disclosed. Step (A) may receive a plurality of first words, at least two of the first words generally have a different length than each other. Step (B) may parse the first words into a plurality of memories. Step (C) may generate a plurality of second words by decoding the first words using a plurality of decoders. The decoders generally operate in parallel. The decoding of at least one of the first words may be performed by at least two of the decoders. The decoding is generally based on a signal that identifies a current one of the communications standards used to transfer the first words.
摘要翻译：公开了通常包括步骤（A）至（C）的多个通信标准的并行解码方法。步骤（A）可以接收多个第一单词，至少两个第一单词通常具有彼此不同的长度。步骤（B）可以将第一个单词解析成多个存储器。步骤（C）可以通过使用多个解码器对第一个字进行解码来生成多个第二字。解码器通常并行运行。至少一个第一个字的解码可以由至少两个解码器执行。解码通常基于识别用于传送第一个字的通信标准中的当前一个的信号。

10. 发明授权

US08700969B2 Reconfigurable encoding per multiple communications standards 有权
标题翻译：根据多种通信标准重新配置编码
公开(公告)号：US08700969B2
公开(公告)日：2014-04-15
申请号：US13116253
申请日：2011-05-26
申请人： Pavel A. Panteleev , Elyar E. Gasanov , Ilya V. Neznanov , Andrey P. Sokolov , Yurii S. Shutkin
发明人： Pavel A. Panteleev , Elyar E. Gasanov , Ilya V. Neznanov , Andrey P. Sokolov , Yurii S. Shutkin
IPC分类号： H03M13/00
CPC分类号： H03M13/235 , H03M13/2903 , H03M13/2957 , H03M13/616 , H03M13/6513 , H03M13/6516 , H03M13/6519 , H03M13/6525 , H03M13/6544 , H03M13/6558
摘要： An apparatus generally including a first circuit and a second circuit. The first circuit may be configured to (i) receive a configuration signal that identifies a current one of a plurality of communications standards and (ii) generate a plurality of matrix elements based on the configuration signal. The second circuit may include a plurality of matrixes. The second circuit may be configured to (i) fill the matrixes with the matrix elements and (ii) generate an encoded signal by forward error correction encoding an input signal using the matrixes. The encoded signal generally complies with the current communications standard.
摘要翻译：一种通常包括第一电路和第二电路的装置。第一电路可以被配置为（i）接收识别多个通信标准中的当前一个通信标准的配置信号，以及（ii）基于配置信号生成多个矩阵元素。第二电路可以包括多个矩阵。第二电路可以被配置为（i）用矩阵元素填充矩阵，并且（ii）通过使用矩阵对输入信号进行前向纠错编码来生成编码信号。编码信号通常符合当前的通信标准。

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