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1. 发明申请

US20110035937A1 Semiconductor Wafer Carrier and Method of Manufacturing 有权
标题翻译：半导体晶圆载体及制造方法
公开(公告)号：US20110035937A1
公开(公告)日：2011-02-17
申请号：US12840903
申请日：2010-07-21
申请人： Yung-Jean Lu , Ming-Fa Chen , Chen-Shien Chen , Jao Sheng Huang
发明人： Yung-Jean Lu , Ming-Fa Chen , Chen-Shien Chen , Jao Sheng Huang
IPC分类号： H05K13/00
CPC分类号： H01L21/6833 , Y10T29/49124
摘要： A system and method for a semiconductor wafer carrier is disclosed. An embodiment comprises a semiconductor wafer carrier wherein conductive dopants are implanted into the carrier in order to amplify the coulombic forces between an electrostatic chuck and the carrier to compensate for reduced forces that result from thinner semiconductor wafers. Another embodiment forms conductive layers and vias within the carrier instead of implanting conductive dopants.
摘要翻译：公开了一种用于半导体晶片载体的系统和方法。一个实施方案包括半导体晶片载体，其中将导电掺杂剂注入到载体中，以便放大静电卡盘和载体之间的库仑力，以补偿由较薄的半导体晶片产生的减小的力。另一个实施例在载体内形成导电层和通孔，而不是注入导电掺杂剂。

2. 发明授权

US08859424B2 Semiconductor wafer carrier and method of manufacturing 有权
标题翻译：半导体晶圆载体及其制造方法
公开(公告)号：US08859424B2
公开(公告)日：2014-10-14
申请号：US12840903
申请日：2010-07-21
申请人： Yung-Jean Lu , Ming-Fa Chen , Chen-Shien Chen , Jao Sheng Huang
发明人： Yung-Jean Lu , Ming-Fa Chen , Chen-Shien Chen , Jao Sheng Huang
IPC分类号： H01L21/44 , H01L21/683
CPC分类号： H01L21/6833 , Y10T29/49124
摘要： A system and method for a semiconductor wafer carrier is disclosed. An embodiment comprises a semiconductor wafer carrier wherein conductive dopants are implanted into the carrier in order to amplify the coulombic forces between an electrostatic chuck and the carrier to compensate for reduced forces that result from thinner semiconductor wafers. Another embodiment forms conductive layers and vias within the carrier instead of implanting conductive dopants.
摘要翻译：公开了一种用于半导体晶片载体的系统和方法。一个实施方案包括半导体晶片载体，其中将导电掺杂剂注入到载体中，以便放大静电卡盘和载体之间的库仑力，以补偿由较薄的半导体晶片产生的减小的力。另一个实施例在载体内形成导电层和通孔，而不是注入导电掺杂剂。

3. 发明授权

US08820728B2 Semiconductor wafer carrier 有权
标题翻译：半导体晶圆载体
公开(公告)号：US08820728B2
公开(公告)日：2014-09-02
申请号：US12617851
申请日：2009-11-13
申请人： Jao Sheng Huang , Ming-Fa Chen
发明人： Jao Sheng Huang , Ming-Fa Chen
IPC分类号： B23Q3/00
CPC分类号： H01L21/67346 , H01L21/67132
摘要： A system and a method for protecting semiconductor wafers is disclosed. A preferred embodiment comprises a carrier with a central region and an exterior region. The exterior region preferably has a thickness that is greater than the central region, to form a cavity in the carrier. An adhesive is preferably placed into the cavity, and a semiconductor wafer is placed onto the adhesive. The edges of the semiconductor wafer are protected by the raised exterior region as well as the displaced adhesive that at least partially fills the area between the semiconductor wafer and the exterior region of the carrier.
摘要翻译：公开了一种用于保护半导体晶片的系统和方法。优选实施例包括具有中心区域和外部区域的载体。外部区域优选具有大于中心区域的厚度，以在载体中形成空腔。优选将粘合剂放置在空腔中，并将半导体晶片放置在粘合剂上。半导体晶片的边缘被凸起的外部区域以及至少部分地填充半导体晶片和载体的外部区域之间的区域的移位的粘合剂保护。

4. 发明申请

US20100194014A1 Semiconductor Wafer Carrier 有权
标题翻译：半导体晶圆载体
公开(公告)号：US20100194014A1
公开(公告)日：2010-08-05
申请号：US12617851
申请日：2009-11-13
申请人： Jao Sheng Huang , Ming-Fa Chen
发明人： Jao Sheng Huang , Ming-Fa Chen
IPC分类号： H01L21/673 , B29C65/14
CPC分类号： H01L21/67346 , H01L21/67132
摘要： A system and a method for protecting semiconductor wafers is disclosed. A preferred embodiment comprises a carrier with a central region and an exterior region. The exterior region preferably has a thickness that is greater than the central region, to form a cavity in the carrier. An adhesive is preferably placed into the cavity, and a semiconductor wafer is placed onto the adhesive. The edges of the semiconductor wafer are protected by the raised exterior region as well as the displaced adhesive that at least partially fills the area between the semiconductor wafer and the exterior region of the carrier.
摘要翻译：公开了一种用于保护半导体晶片的系统和方法。优选实施例包括具有中心区域和外部区域的载体。外部区域优选具有大于中心区域的厚度，以在载体中形成空腔。优选将粘合剂放置在空腔中，并将半导体晶片放置在粘合剂上。半导体晶片的边缘被凸起的外部区域以及至少部分地填充半导体晶片和载体的外部区域之间的区域的移位的粘合剂保护。

5. 发明授权

US08501587B2 Stacked integrated chips and methods of fabrication thereof 有权
标题翻译：堆叠集成芯片及其制造方法
公开(公告)号：US08501587B2
公开(公告)日：2013-08-06
申请号：US12613408
申请日：2009-11-05
申请人： Ming-Fa Chen , Jao Sheng Huang
发明人： Ming-Fa Chen , Jao Sheng Huang
IPC分类号： H01L21/467 , H01L21/441
CPC分类号： H01L23/49816 , H01L21/76898 , H01L23/49827 , H01L25/0657 , H01L25/50 , H01L2224/05001 , H01L2224/05009 , H01L2224/05025 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/0557 , H01L2224/05571 , H01L2224/05644 , H01L2224/05655 , H01L2224/16145 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/1305 , H01L2924/15311 , H01L2924/18161 , H01L2924/00012 , H01L2924/00 , H01L2924/00014
摘要： Structure and methods of forming stacked semiconductor chips are described. In one embodiment, a method of forming a semiconductor chip includes forming an opening for a through substrate via from a top surface of a first substrate. The sidewalls of the opening are lined with an insulating liner and the opened filled with a conductive fill material. The first substrate is etched from an opposite bottom surface to form a protrusion, the protrusion being covered with the insulating liner. A resist layer is deposited around the protrusion to expose a portion of the insulating liner. The exposed insulating liner is etched to form a sidewall spacer along the protrusion.
摘要翻译：描述形成叠层半导体芯片的结构和方法。在一个实施例中，形成半导体芯片的方法包括从第一基板的顶表面形成用于贯通基板通孔的开口。开口的侧壁衬有绝缘衬垫，开口填充有导电填充材料。第一衬底从相对的底表面蚀刻以形成突起，突起被绝缘衬垫覆盖。抗蚀剂层沉积在突起周围以暴露绝缘衬垫的一部分。蚀刻暴露的绝缘衬垫以沿突起形成侧壁间隔物。

6. 发明申请

US20100178761A1 Stacked Integrated Chips and Methods of Fabrication Thereof 有权
标题翻译：堆叠集成芯片及其制作方法
公开(公告)号：US20100178761A1
公开(公告)日：2010-07-15
申请号：US12613408
申请日：2009-11-05
申请人： Ming-Fa Chen , Jao Sheng Huang
发明人： Ming-Fa Chen , Jao Sheng Huang
IPC分类号： H01L21/768
CPC分类号： H01L23/49816 , H01L21/76898 , H01L23/49827 , H01L25/0657 , H01L25/50 , H01L2224/05001 , H01L2224/05009 , H01L2224/05025 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/0557 , H01L2224/05571 , H01L2224/05644 , H01L2224/05655 , H01L2224/16145 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/1305 , H01L2924/15311 , H01L2924/18161 , H01L2924/00012 , H01L2924/00 , H01L2924/00014
摘要： Structure and methods of forming stacked semiconductor chips are described. In one embodiment, a method of forming a semiconductor chip includes forming an opening for a through substrate via from a top surface of a first substrate. The sidewalls of the opening are lined with an insulating liner and the opened filled with a conductive fill material. The first substrate is etched from an opposite bottom surface to form a protrusion, the protrusion being covered with the insulating liner. A resist layer is deposited around the protrusion to expose a portion of the insulating liner. The exposed insulating liner is etched to form a sidewall spacer along the protrusion.
摘要翻译：描述形成叠层半导体芯片的结构和方法。在一个实施例中，形成半导体芯片的方法包括从第一基板的顶表面形成用于贯通基板通孔的开口。开口的侧壁衬有绝缘衬垫，开口填充有导电填充材料。第一衬底从相对的底表面蚀刻以形成突起，突起被绝缘衬垫覆盖。抗蚀剂层沉积在突起周围以暴露绝缘衬垫的一部分。蚀刻暴露的绝缘衬垫以沿突起形成侧壁间隔物。

7. 发明授权

US06972241B2 Method of forming an STI feature to avoid electrical charge leakage 失效
标题翻译：形成STI特征以避免电荷泄漏的方法
公开(公告)号：US06972241B2
公开(公告)日：2005-12-06
申请号：US10761656
申请日：2004-01-20
申请人： Yih Song Chiu , Jao Sheng Huang , Wen Ting Tsai , Chen Hsiang Leu
发明人： Yih Song Chiu , Jao Sheng Huang , Wen Ting Tsai , Chen Hsiang Leu
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76232
摘要： A method for forming shallow trench isolation (STI) structure including providing a substrate comprising an overlying hardmask layer; patterning the hardmask layer to form a hardmask layer opening for etching a trench through a substrate thickness portion; etching a trench according to the patterned overlying hardmask layer; carrying out a wet chemical oxidizing process to form an oxidized surface portion on the hardmask layer; carrying out a wet chemical etching process to remove at least a portion of the oxidized surface portion to form the hardmask opening having an enlarged width and the trench opening comprising rounded upper corners; and, forming a completed planarized STI structure filled with oxide.
摘要翻译：一种用于形成浅沟槽隔离（STI）结构的方法，包括提供包括上覆硬掩模层的衬底; 图案化硬掩模层以形成用于通过衬底厚度部分蚀刻沟槽的硬掩模层开口; 根据图案化的覆盖硬掩模层蚀刻沟槽; 进行湿化学氧化处理以在硬掩模层上形成氧化表面部分; 执行湿化学蚀刻工艺以去除氧化表面部分的至少一部分以形成具有扩大宽度的硬掩模开口，并且沟槽开口包括圆形上角部; 并且形成填充有氧化物的完成的平坦化STI结构。

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