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1. 发明申请

US20090160558A1 RF AMPLIFIER 失效
标题翻译：射频放大器
公开(公告)号：US20090160558A1
公开(公告)日：2009-06-25
申请号：US12118562
申请日：2008-05-09
申请人： Yun-Ho CHOI , Young-Ho KIM , Seok-Bong HYUN
发明人： Yun-Ho CHOI , Young-Ho KIM , Seok-Bong HYUN
IPC分类号： H03F3/04
CPC分类号： H03F3/189
摘要： Provided is a radio frequency (RF) amplifier. The RF amplifier includes an amplification circuit amplifying an RF signal, a bias voltage generation circuit supplying a bias voltage of the amplification circuit, and a first bias resistor connected between the amplification circuit ad the bias voltage generation circuit, and having a predetermined resistance allowing the bias voltage to be affected by the RF signal.
摘要翻译：提供射频（RF）放大器。 RF放大器包括放大RF信号的放大电路，提供放大电路的偏置电压的偏置电压产生电路和连接在放大电路和偏置电压产生电路之间的第一偏置电阻，并且具有允许偏置电压受RF信号的影响。

2. 发明申请

US20120072810A1 ERROR CORRECTION CIRCUIT AND METHOD, AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE CIRCUIT 审中-公开
标题翻译：错误校正电路和方法以及包括电路的半导体存储器件
公开(公告)号：US20120072810A1
公开(公告)日：2012-03-22
申请号：US13239534
申请日：2011-09-22
申请人： Yong-Tae YIM , Yun-Ho CHOI
发明人： Yong-Tae YIM , Yun-Ho CHOI
IPC分类号： H03M13/07 , G06F11/10
CPC分类号： G11C7/1006 , G06F11/1008 , G11C2029/0411 , G11C2207/104
摘要： An error correction circuit, an error correction method, and a semiconductor memory device including the error correction circuit are provided. The error correction circuit includes a partial syndrome generator, first and second error position detectors, a coefficient calculator, and a determiner. The partial syndrome generator calculates at least two partial syndromes using coded data. The first error position detector calculates a first error position using a part of the partial syndromes. The coefficient calculator calculates coefficients of an error position equation using the at least two partial syndromes. The determiner determines an error type based on the coefficients. The second error position detector optionally calculates a second error position based on the error type.
摘要翻译：提供了纠错电路，误差校正方法以及包括误差校正电路的半导体存储器件。误差校正电路包括部分校正子发生器，第一和第二误差位置检测器，系数计算器和确定器。部分综合征发生器使用编码数据计算至少两个部分综合征。第一误差位置检测器使用部分综合征的一部分来计算第一误差位置。系数计算器使用至少两个部分综合征计算误差位置方程的系数。确定器基于系数确定错误类型。第二错误位置检测器可选地基于错误类型计算第二错误位置。

3. 发明申请

US20080052564A1 ERROR CORRECTION CIRCUIT AND METHOD, AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE CIRCUIT 有权
标题翻译：错误校正电路和方法以及包括电路的半导体存储器件
公开(公告)号：US20080052564A1
公开(公告)日：2008-02-28
申请号：US11776727
申请日：2007-07-12
申请人： Yong-Tae YIM , Yun-Ho CHOI
发明人： Yong-Tae YIM , Yun-Ho CHOI
IPC分类号： G06K5/04
CPC分类号： G11C7/1006 , G06F11/1008 , G11C2029/0411 , G11C2207/104
摘要： An error correction circuit, an error correction method, and a semiconductor memory device including the error correction circuit are provided. The error correction circuit includes a partial syndrome generator, first and second error position detectors, a coefficient calculator, and a determiner. The partial syndrome generator calculates at least two partial syndromes using coded data. The first error position detector calculates a first error position using a part of the partial syndromes. The coefficient calculator calculates coefficients of an error position equation using the at least two partial syndromes. The determiner determines an error type based on the coefficients. The second error position detector optionally calculates a second error position based on the error type. The semiconductor memory device includes the error correction circuit, an error checking and correcting (ECC) encoder generating syndrome data based on information data and generating the coded data by combining the syndrome data with information data, and a memory core storing the coded data. Multi-bit ECC performance is maintained and ECC for a predetermined (1 or 2) or less number of error bits is quickly performed.
摘要翻译：提供了纠错电路，误差校正方法以及包括误差校正电路的半导体存储器件。误差校正电路包括部分校正子发生器，第一和第二误差位置检测器，系数计算器和确定器。部分综合征发生器使用编码数据计算至少两个部分综合征。第一误差位置检测器使用部分综合征的一部分来计算第一误差位置。系数计算器使用至少两个部分综合征计算误差位置方程的系数。确定器基于系数确定错误类型。第二错误位置检测器可选地基于错误类型计算第二错误位置。半导体存储器件包括误差校正电路，错误校正和校正（ECC）编码器，其基于信息数据产生校正子数据，并通过将校正子数据与信息数据组合并产生编码数据，以及存储编码数据的存储器核心。维持多比特ECC性能，并且快速执行用于预定（1或2）或更少数目的错误比特的ECC。

4. 发明申请

US20090003064A1 FLASH MEMORY DEVICE AND METHOD OF PROGRAMMING FLASH MEMORY DEVICE 有权
标题翻译：闪存存储器件和编程闪速存储器件的方法
公开(公告)号：US20090003064A1
公开(公告)日：2009-01-01
申请号：US12126080
申请日：2008-05-23
申请人： Kyong-Ae KIM , Jin-Wook LEE , Yun-Ho CHOI
发明人： Kyong-Ae KIM , Jin-Wook LEE , Yun-Ho CHOI
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/349
摘要： A flash memory device and a method of programming the same include a memory cell array, a pass/fail check circuit and a control logic circuit. The memory cell array includes multiple memory cells arranged in rows and columns. The pass/fail check circuit verifies whether data bits selected by a column address during a column scan operation have program data values. The control logic circuit detects fail data bits from the selected data bits and stores the column address in response to the verification result of the pass/fail check circuit. The control logic circuit also compares a number of the fail data bits with a reference value and controls generation of the column address according to the comparison result.
摘要翻译：闪速存储器件及其编程方法包括存储单元阵列，通过/失败校验电路和控制逻辑电路。存储单元阵列包括以行和列排列的多个存储单元。通过/失败检查电路验证在列扫描操作期间由列地址选择的数据位是否具有程序数据值。控制逻辑电路根据所选数据位检测故障数据位，并响应于通过/不通过检查电路的验证结果存储列地址。控制逻辑电路还将多个故障数据位与参考值进行比较，并根据比较结果控制列地址的生成。

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