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    • 3. 发明授权
    • Document processor having a programmable dictionary
    • 具有可编程字典的文档处理器
    • US5359707A
    • 1994-10-25
    • US200558
    • 1994-02-22
    • Yumi Sato
    • Yumi Sato
    • G06F17/21G06F17/22G06F17/28G06F15/62
    • G06F17/2863
    • A document processor which advantageously provides usage information for words includes a first memory for storing a document to be elaborated, the document including first word data, a second memory for storing a dictionary including second word data and usage data associated with the second word data, and a third memory for temporarily storing a list of third word data which are not to be elaborated. A controller sequentially retrieves the first word data included in the first memory, sequentially compares the first word data with the second word data and the third word data, and selects individual word data for elaboration from the first word data which coincides with the second word data and which does not coincide with the third word data.
    • 有利地提供字的使用信息的文档处理器包括用于存储要阐述的文档的第一存储器,所述文档包括第一字数据,用于存储包括第二字数据和与第二字数据相关联的使用数据的字典的第二存储器, 以及第三存储器,用于临时存储不被详细描述的第三字数据的列表。 控制器顺序检索包含在第一存储器中的第一字数据,顺序地比较第一字数据与第二字数据和第三字数据,并从与第二字数据一致的第一字数据中选择详细的单词数据 并且与第三个字数据不一致。
    • 5. 发明申请
    • Storage control apparatus, control system capable of DMA transfer, and method of controlling DMA transfer
    • 存储控制装置,能够进行DMA传输的控制系统,以及DMA传输控制方法
    • US20050091458A1
    • 2005-04-28
    • US10800349
    • 2004-03-12
    • Yumi SatoFumio SudoYasumasa Nakada
    • Yumi SatoFumio SudoYasumasa Nakada
    • G06F12/08G06F12/10G06F13/28
    • G06F12/0831G06F12/0888
    • The present invention of a storage control apparatus which is connected to a host bus connected to a CPU (Central Processing Unit), a peripheral bus connected to at least one IP (Intellectual Property), and a system memory and controls DMA (Direct Memory Access) transfer from the IP to the system memory, having: an address map judgment section which judges whether an address given from one of the peripheral bus and the host bus indicates a memory area managed by the storage control apparatus in the system memory; a memory control section which controls data transfer to/from the system memory; a TLB (Translation Look-aside Buffer) information holding section which holds address information that indicates an area cacheable by the CPU; an address judgment section which judges on the basis of the address information held by the TLB information holding section whether the address given from one of the peripheral bus and the host bus indicates the area cacheable by the CPU; and a snoop address control section which, when it is judged on the basis of a judgment result from the address judgment section that the CPU needs to be notified of the address, executes notification through the host bus.
    • 连接到连接到CPU(中央处理单元)的主机总线,连接到至少一个IP(知识产权)的外围总线以及系统存储器并且控制DMA(直接存储器访问)的存储控制装置的本发明 )从IP传送到系统存储器,具有:地址映射判断部,判断从外围总线和主机总线中的一个给出的地址是否表示由系统存储器中的存储控制装置管理的存储区域; 存储器控制部分,其控制到/从系统存储器传送的数据; 信息保持部分,其保存指示可由CPU缓存的区域的地址信息; 地址判定部,其根据由TLB信息保持部所保持的地址信息判断从外围总线和主机总线之一给出的地址是否表示CPU可高速缓存的区域; 以及侦听地址控制部,其基于来自所述地址判断部的判定结果判断为需要通知所述CPU的地址,通过所述主机总线执行通知。