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1. 发明授权

US5155853A Data processor operating in a vector interrupt mode and register bank switching mode with selected bank for interrupt processing 失效
标题翻译：数据处理器工作在向量中断模式和寄存器组切换模式，选择存储区进行中断处理
公开(公告)号：US5155853A
公开(公告)日：1992-10-13
申请号：US441146
申请日：1989-11-27
申请人： Yuko Mitsuhira , Ichiro Kozono
发明人： Yuko Mitsuhira , Ichiro Kozono
IPC分类号： G06F9/46 , G06F9/48
CPC分类号： G06F9/4812
摘要： A data processor comprises a central processing unit, a plurality of register banks used by the central processing unit when the central processing unit executes a given process, an interrupt controller responding to an interrupt request signal to generate an interrupt acknowledge signal and to select a predetermined register bank and also to start an interrupt handling program, a interrupt code generator for generating an interrupt code corresponding to an interrupt request when the interrupt request signal is generated, and an interrupt source register for holding the interrupt code after the interrupt request is acknowledged until a next interrupt request is acknowledged, so that a start address of the interrupt handling program is controlled in accordance with the contents of the interrupt source register.
摘要翻译：数据处理器包括中央处理单元，当中央处理单元执行给定处理时由中央处理单元使用的多个寄存器组，响应于中断请求信号的中断控制器产生中断确认信号，并选择预定的寄存器组，并且还启动一个中断处理程序，一个中断代码发生器，用于在生成中断请求信号时产生与中断请求对应的中断代码，以及一个用于在中断请求之后保持中断代码的中断源寄存器，直到下一个中断请求被确认，从而根据中断源寄存器的内容来控制中断处理程序的起始地址。

2. 发明授权

US5561816A Data transfer controlling device for use in a direct memory access (DMA) system 失效
标题翻译：用于直接存储器存取（DMA）系统的数据传输控制装置
公开(公告)号：US5561816A
公开(公告)日：1996-10-01
申请号：US3851
申请日：1993-01-11
申请人： Yuko Mitsuhira , Tsuyoshi Katayose
发明人： Yuko Mitsuhira , Tsuyoshi Katayose
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A data transfer controlling device of a direct memory access controller (DMAC) type includes a transfer number data storage, a transfer number updating decrementer, a data setter for setting predetermined initial data in the transfer number data storage, a terminal counter with a decrementer or an area counter with a decrementer, a memory address register, an address updating section, and a DMA execution control section. The number of times of transfer for the subsequent DMA transfer is automatically set when the number of DMA transfers to be successively executed in response to each DMA transfer request has been completed. Immediately thereafter, the DMA transfer is repeated in response to the subsequent DMA transfer request. When the DMA transfer has been completed to the final data in the DMA transfer source region of a memory, it is placed in an inhibited state. Thus, DMAC can respond to the DMA transfer request issued from a peripheral device at a high speed.
摘要翻译：直接存储器存取控制器（DMAC）类型的数据传送控制装置包括传送号码数据存储器，传送号码更新递减器，用于设置传送号码数据存储器中的预定初始数据的数据设置器，具有减法器的终端计数器具有减法器的区域计数器，存储器地址寄存器，地址更新部分和DMA执行控制部分。当响应每个DMA传输请求连续执行的DMA传输次数已经完成时，自动设置随后的DMA传输的传送次数。之后立即响应于随后的DMA传输请求重复DMA传输。当DMA传输已完成到存储器的DMA传输源区域中的最终数据时，它被置于禁止状态。因此，DMAC可以高速响应从外围设备发出的DMA传输请求。

3. 发明授权

US5365183A Single chip microcomputer having two kinds of timer functions 失效
标题翻译：单片机具有两种定时器功能
公开(公告)号：US5365183A
公开(公告)日：1994-11-15
申请号：US951866
申请日：1992-09-28
申请人： Yuko Mitsuhira
发明人： Yuko Mitsuhira
IPC分类号： G06F1/14 , G06F15/78 , H03K5/15
CPC分类号： G06F1/14
摘要： A single chip microcomputer includes two kinds of timer circuits which receive a common clock signal. One of the timer circuits generates a first timer signal, and the other generates a second timer signal. When the first timer signal is being reset, the second timer signal is inactive.
摘要翻译：单片机包括接收公共时钟信号的两种定时器电路。一个定时器电路产生第一定时器信号，另一个产生第二定时器信号。当第一定时器信号被复位时，第二定时器信号是无效的。

4. 发明授权

US5696989A Microcomputer equipped with DMA controller allowed to continue to perform data transfer operations even after completion of a current data transfer operation 失效
标题翻译：配备有DMA控制器的微型计算机即使在当前的数据传输操作完成之后也能够继续执行数据传输操作
公开(公告)号：US5696989A
公开(公告)日：1997-12-09
申请号：US720288
申请日：1991-06-25
申请人： Katsumi Miura , Yuko Mitsuhira
发明人： Katsumi Miura , Yuko Mitsuhira
IPC分类号： G06F13/28 , G06F13/12
CPC分类号： G06F13/28
摘要： A microprocessor with a DMA controller for performing data transfers between a peripheral unit and a memory in response to a transfer request from the peripheral unit. The DMA controller includes a first memory block for storing information necessary to perform a current DMA data transfer and a second memory block for storing information necessary to perform the next DMA data transfer. The second DMA data transfer is initiated after completion of the first data transfer and the information stored in the second memory block is transferred to the first memory block. This process is repeated for all subsequent DMA data transfers. Each section of information stored in the first and second memory blocks includes the number of data transfers to be performed, a memory access address representing the location of the data to be transferred, and control/status information. The control/status information includes enable/disable information indicated whether another block of data is to be transferred via the DMA data transfer, thereby shortening the duration of a data transfer inhibiting state.
摘要翻译：一种具有DMA控制器的微处理器，用于响应于来自外围单元的传送请求在外围单元和存储器之间执行数据传输。 DMA控制器包括用于存储执行当前DMA数据传输所必需的信息的第一存储器块和用于存储执行下一个DMA数据传输所必需的信息的第二存储器块。第二DMA数据传输在完成第一数据传输之后启动，并且存储在第二存储器块中的信息被传送到第一存储器块。对所有后续DMA数据传输重复此过程。存储在第一和第二存储器块中的每个部分信息包括要执行的数据传送的数量，表示要传送的数据的位置的存储器访问地址以及控制/状态信息。控制/状态信息包括指示是否要通过DMA数据传送传送另一数据块的启用/禁用信息，从而缩短数据传送禁止状态的持续时间。

5. 发明授权

US5325489A Data transfer control device using direct memory access 失效
标题翻译：数据传输控制器使用直接存储器访问
公开(公告)号：US5325489A
公开(公告)日：1994-06-28
申请号：US913279
申请日：1992-07-14
申请人： Yuko Mitsuhira , Tsuyoshi Katayose
发明人： Yuko Mitsuhira , Tsuyoshi Katayose
IPC分类号： G06F13/38 , G06F13/28 , G06F13/00
CPC分类号： G06F13/28
摘要： When DMA transfer for a DMA transfer area is completed, DMA transfer for the next area may be continuously executed or stopped. In addition to this, if there is a need to urgently stop DMA transfer being executed, DMA transfer can be immediately stopped without waiting for the end of DMA transfer currently executed. For continuous DMA transfer for a plurality of DMA transfer areas, the device may be provided with an authorization bit to authorize DMA transfer operation and a next area authorization bit to authorize DMA transfer for the next area and the contents in the next area authorization bit are set to the DMA authorization bit when the terminal counter which counts the number of DMA transfer data reaches the predetermined value due to decrement. Depending on the contents in the DMA authorization bit, DMA transfer may be continued or stopped when the next DMA transfer request is generated. In addition, DMA transfer may be stopped in emergency by directly setting the applicable value at the DMA authorization bit.
摘要翻译：当DMA传输区域的DMA传输完成时，可能会连续执行或停止下一个区域的DMA传输。除此之外，如果需要紧急停止正在执行的DMA传输，则可以立即停止DMA传输，而无需等待当前执行的DMA传输的结束。对于多个DMA传输区域的连续DMA传输，该设备可以被提供有授权位来授权DMA传输操作和下一区域授权位来授权下一区域的DMA传输，并且下一区域授权位中的内容是当计数DMA传输数据的终端计数器由于递减而达到预定值时，设置为DMA授权位。根据DMA授权位中的内容，当生成下一个DMA传输请求时，DMA传输可能会继续或停止。此外，通过在DMA授权位上直接设置适用的值，可能会在紧急情况下停止DMA传输。

6. 发明授权

US5235682A Port output controller for use in microcomputer 失效
标题翻译：端口输出控制器用于微型计算机
公开(公告)号：US5235682A
公开(公告)日：1993-08-10
申请号：US783756
申请日：1991-10-17
申请人： Yuko Mitsuhira , Tsuyoshi Katayose
发明人： Yuko Mitsuhira , Tsuyoshi Katayose
IPC分类号： G06F15/78 , H02P8/00 , H02P23/00 , H02P27/06 , H02P29/00
CPC分类号： H02P23/0077
摘要： A port output controller for use in a microcomputer for outputting data to a plurality of output terminals in real time, includes a latch circuit for latching data being outputted to the output terminals and a buffer register for storing data to be outputted to the output terminals next to the data being outputted to the output terminals. A timer counter counts an elapsed time after the next data has been latched in the latch circuit and causes the next data stored in the buffer register to be latched into the latch circuit when the counted elapsed time becomes a predetermined data outputting period of time. In a delayed output mode, a delay counter counts a delayed time after the next data has been latched in the latch circuit, and a delay output circuit controls the outputting of the data latched in the latch circuit to the output terminals in such a manner that if the data latched in the latch circuit is a first value, the data latched in the latch circuit is outputted to the output terminal without delay, and if the data latched in the latch circuit is a second value, the data latched in the latch circuit is outputted to the output terminal when the counted delay time has become a predetermined delay time.

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