专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08325170B2 Image display device and driving method thereof 失效
标题翻译：图像显示装置及其驱动方法
公开(公告)号：US08325170B2
公开(公告)日：2012-12-04
申请号：US12639049
申请日：2009-12-16
申请人： Yukio Tanaka , Munehiro Azami , Yasushi Kubota , Hajime Washio
发明人： Yukio Tanaka , Munehiro Azami , Yasushi Kubota , Hajime Washio
IPC分类号： G09G5/00 , G06F3/038
CPC分类号： G09G3/3688 , G09G2310/027 , G09G2310/0297
摘要： An occupying area of a digital system signal line driver circuit in an image display device is large and this hinders the miniaturization of the display device. A memory circuit and a D/A converter circuit in the signal line driver circuit are commonly used for n (“n” is a natural number equal to or larger than 2) signal lines. One horizontal scanning period is divided into n periods and the memory circuit and the D/A converter circuit each perform processing for different signal lines during each of the divided periods. Thus, all the signal lines can be driven. Therefore, the number of memory circuits and the number of D/A converter circuits in the signal line driver circuit can be reduced to one n-th in a conventional case.
摘要翻译：图像显示装置中的数字系统信号线驱动电路的占有面积大，妨碍显示装置的小型化。信号线驱动电路中的存储电路和D / A转换电路通常用于n（n为等于或大于2的自然数）信号线。一个水平扫描周期被分为n个周期，并且存储器电路和D / A转换器电路在每个分割周期期间各自执行不同信号线的处理。因此，可以驱动所有的信号线。因此，在常规情况下，信号线驱动电路中的存储电路数量和D / A转换电路的数量可以减少到1 / n。

2. 发明申请

US20100090994A1 Image Display Device and Driving Method Thereof 失效
标题翻译：图像显示装置及其驱动方法
公开(公告)号：US20100090994A1
公开(公告)日：2010-04-15
申请号：US12639049
申请日：2009-12-16
申请人： Yukio Tanaka , Munehiro Azami , Yasushi Kubota , Hajime Washio
发明人： Yukio Tanaka , Munehiro Azami , Yasushi Kubota , Hajime Washio
IPC分类号： G09G5/00 , G09G3/36 , H04N5/66
CPC分类号： G09G3/3688 , G09G2310/027 , G09G2310/0297
摘要： An occupying area of a digital system signal line driver circuit in an image display device is large and this hinders the miniaturization of the display device. A memory circuit and a D/A converter circuit in the signal line driver circuit are commonly used for n (“n” is a natural number equal to or larger than 2) signal lines. One horizontal scanning period is divided into n periods and the memory circuit and the D/A converter circuit each perform processing for different signal lines during each of the divided periods. Thus, all the signal lines can be driven. Therefore, the number of memory circuits and the number of D/A converter circuits in the signal line driver circuit can be reduced to one n-th in a conventional case.
摘要翻译：图像显示装置中的数字系统信号线驱动电路的占有面积大，妨碍显示装置的小型化。信号线驱动电路中的存储电路和D / A转换电路通常用于n（“n”是等于或大于2的自然数）的信号线。一个水平扫描周期被分为n个周期，并且存储器电路和D / A转换器电路在每个分割周期期间各自执行不同信号线的处理。因此，可以驱动所有的信号线。因此，在常规情况下，信号线驱动电路中的存储电路数量和D / A转换电路的数量可以减少到1 / n。

3. 发明授权

US07663613B2 Image display device and driving method thereof 有权
标题翻译：图像显示装置及其驱动方法
公开(公告)号：US07663613B2
公开(公告)日：2010-02-16
申请号：US10159288
申请日：2002-06-03
申请人： Yukio Tanaka , Munehiro Azami , Yasushi Kubota , Hajime Washio
发明人： Yukio Tanaka , Munehiro Azami , Yasushi Kubota , Hajime Washio
IPC分类号： G09G5/00 , G06F3/038
CPC分类号： G09G3/3688 , G09G2310/027 , G09G2310/0297
摘要： An occupying area of a digital system signal line driver circuit in an image display device is large and this hinders the miniaturization of the display device. A memory circuit and a D/A converter circuit in the signal line driver circuit are commonly used for n (“n” is a natural number equal to or larger than 2) signal lines. One horizontal scanning period is divided into n periods and the memory circuit and the D/A converter circuit each perform processing for different signal lines during each of the divided periods. Thus, all the signal lines can be driven. Therefore, the number of memory circuits and the number of D/A converter circuits in the signal line driver circuit can be reduced to one n-th in a conventional case.
摘要翻译：图像显示装置中的数字系统信号线驱动电路的占有面积大，妨碍显示装置的小型化。信号线驱动电路中的存储电路和D / A转换电路通常用于n（“n”是等于或大于2的自然数）的信号线。一个水平扫描周期被分为n个周期，并且存储器电路和D / A转换器电路在每个分割周期期间各自执行不同信号线的处理。因此，可以驱动所有的信号线。因此，在常规情况下，信号线驱动电路中的存储电路数量和D / A转换电路的数量可以减少到1 / n。

4. 发明授权

US06693616B2 Image display device, method of driving thereof, and electronic equipment 有权
标题翻译：图像显示装置，其驱动方法和电子设备
公开(公告)号：US06693616B2
公开(公告)日：2004-02-17
申请号：US09782260
申请日：2001-02-14
申请人： Jun Koyama , Munehiro Azami , Yasushi Kubota , Hajime Washio
发明人： Jun Koyama , Munehiro Azami , Yasushi Kubota , Hajime Washio
IPC分类号： G09G336
CPC分类号： G09G3/3688 , G09G2310/0259 , G09G2310/027 , G09G2310/0297
摘要： The surface area occupied by a digital type signal line driver circuit in an image display device is large, and this is an impediment to reducing the size of the display device. A memory circuit within a signal line driver circuit is made common among n signal lines (where n is a natural number greater than or equal to 2). One horizontal scan period is divided into n divisions, and all signal lines can be driven by performing processing with respect to signal lines differing by memory circuit and D/A converter circuit, respectively, during the period of each division. It thus becomes possible to make 1/n as many memory circuits and D/A conversion circuits within the signal line driver circuit as in a conventional example.
摘要翻译：图像显示装置中的数字式信号线驱动电路所占据的表面积较大，这是减小显示装置尺寸的障碍。信号线驱动电路内的存储电路在n条信号线（其中n为大于或等于2的自然数）之间是共同的。一个水平扫描周期被划分为n个分区，并且在每个划分期间分别通过对与存储电路和D / A转换器电路不同的信号线执行处理来驱动所有的信号线。因此，与现有例一样，能够使信号线驱动电路内的1 / n的存储电路和D / A转换电路成为可能。

5. 发明申请

US20090009374A1 DIGITAL TO ANALOGUE CONVERTER 失效
标题翻译：数字到模拟转换器
公开(公告)号：US20090009374A1
公开(公告)日：2009-01-08
申请号：US11793522
申请日：2006-01-11
申请人： Yasushi Kubota , Kazuhiro Maeda , Hajime Washio , Patrick Zebedee
发明人： Yasushi Kubota , Kazuhiro Maeda , Hajime Washio , Patrick Zebedee
IPC分类号： H03M1/66
CPC分类号： H03M1/802
摘要： A digital/analogue converter for converting an input n-bit digital code, where n is an integer greater than one, has an n-bit digital input and an output for connection to a load, and includes: an array of (n−1) switched capacitors; and a switching arrangement. In one example embodiment, the switching arrangement is adapted, in a zeroing phase of operation, to connect a first reference voltage to the first plate of at least one capacitor of the array and to connect a second plate of the at least one capacitor to a voltage that, for at least one value of the input digital code, is different from the first reference voltage and is further adapted, in a decoding phase of operation, to enable, dependent on the value of the input digital code, injection of charge into the at least one capacitor. In one example embodiment, the converter may be a bufferless converter having an output for direct connection to a capacitive load.
摘要翻译：一种数字/模拟转换器，用于转换其中n是大于1的整数的输入n位数字码，具有n位数字输入和用于连接到负载的输出，并且包括：（n-1））开关电容器; 和切换装置。在一个示例性实施例中，切换装置在操作的归零阶段适于将第一参考电压连接到阵列的至少一个电容器的第一板，并将至少一个电容器的第二板连接到电压，对于输入数字代码的至少一个值，与第一参考电压不同，并且在操作的解码阶段中进一步适应于使得能够依赖于输入数字代码的值将电荷注入所述至少一个电容器。在一个示例性实施例中，转换器可以是具有用于直接连接到电容性负载的输出的无缓冲转换器。

6. 发明申请

US20080036753A1 Display device and driving method thereof 有权
标题翻译：显示装置及其驱动方法
公开(公告)号：US20080036753A1
公开(公告)日：2008-02-14
申请号：US11882533
申请日：2007-08-02
申请人： Hajime Washio , Yasuyoshi Kaise , Sachio Tsujino , Kazuhiro Maeda , Keiji Takahashi , Yasushi Kubota , Toshiya Aoki
发明人： Hajime Washio , Yasuyoshi Kaise , Sachio Tsujino , Kazuhiro Maeda , Keiji Takahashi , Yasushi Kubota , Toshiya Aoki
IPC分类号： G06F3/038
CPC分类号： G09G3/3688 , G09G3/3614 , G09G3/3648 , G09G3/3666 , G09G3/3677 , G09G2310/0213 , G09G2310/0232 , G09G2310/027 , G09G2310/0283 , G09G2310/0297 , G09G2310/04 , G09G2320/0214 , G09G2320/10 , G09G2330/021
摘要： An example control signal generating circuit CTL for controlling the writing into pixels PIX instructs a data signal line drive circuit SD2, which is for driving pixels in a non-display area, to write a voltage VB or a voltage VW which are for non-displaying, not only in the first frame but also once in a predetermined number of frames. In other words, the pixels in the display area are refreshed at intervals longer than those in the case of refreshing the pixels in each frame. Thus, even if the mobility of an active element is high and the leak current on the occasion of OFF-state is large, or even if a large amount of electric charge is accumulated because of the photoelectric effect due to the use of a backlight, it is possible to prevent unnecessary displaying on the display area, which is caused because the writing into the pixels in the display area influences on the pixels in the non-display area, and hence it is possible to improve the quality of partial displaying, while restraining the power consumption.
摘要翻译：用于控制写入像素PIX的示例性控制信号发生电路CTL指示用于驱动非显示区域中的像素的数据信号线驱动电路SD 2写入用于非显示区域的电压VB或电压VW，不仅在第一帧中显示，而且在预定数量的帧中显示一次。换句话说，显示区域中的像素以比刷新每帧中的像素的情况更长的间隔更新。因此，即使有源元件的迁移率高，关断状态下的漏电流大，或者即使由于使用背光导致的光电效应而累积大量的电荷，可以防止由于对显示区域中的像素的写入而影响非显示区域中的像素而导致的显示区域的不必要的显示，因此可以提高部分显示的质量，同时限制功耗。

7. 发明授权

US07042433B1 Signal line driving circuit and image display device 有权
标题翻译：信号线驱动电路和图像显示装置
公开(公告)号：US07042433B1
公开(公告)日：2006-05-09
申请号：US09567364
申请日：2000-05-09
申请人： Yasushi Kubota , Hajime Washio , Kazuhiro Maeda , Graham Andrew Cairns , Michael James Brownlow
发明人： Yasushi Kubota , Hajime Washio , Kazuhiro Maeda , Graham Andrew Cairns , Michael James Brownlow
IPC分类号： G09G3/36
CPC分类号： G09G3/3677 , G09G2310/0289
摘要： A signal line driving circuit includes a shift register having a plurality of shift circuits, each of which shifts a start pulse successively to the next stage, synchronizing with the timing of a clock signal. In this signal line driving circuit, shift pulses are outputted from an AND gate based on output pulses of two adjacent shift circuits. Meanwhile, a width specifying pulse for specifying a pulse width of the shift pulse is inputted via a transistor whose ON/OFF operation is controlled by the shift pulse. A logical operation circuit operates an AND of the shift pulse and the width specifying pulse and outputs the result of operation to a signal line. When the shift pulse is non-active, the transistor becomes OFF, which causes the signal line transmitting the width specifying pulse to be disconnected from the signal line driving circuit, thereby reducing a capacitive load of wiring. As a result, reduction of a parasitic capacitance of the wiring, reduction in the number of elements, reduction in the size of an amplitude of an input signal, etc. in the signal line driving circuit are attained.
摘要翻译：信号线驱动电路包括具有多个移位电路的移位寄存器，每个移位电路将开始脉冲连续地移位到下一级，与时钟信号的定时同步。在该信号线驱动电路中，基于两个相邻移位电路的输出脉冲，从与门输出移位脉冲。同时，用于指定移位脉冲的脉冲宽度的宽度指定脉冲通过由移位脉冲控制其ON / OFF操作的晶体管输入。逻辑运算电路对移位脉冲和宽度指定脉冲进行AND运算，并将运算结果输出到信号线。当移位脉冲不起作用时，晶体管变为截止，使得将信号线发送宽度指定脉冲与信号线驱动电路断开，从而降低布线的容性负载。结果，实现了信号线驱动电路中布线的寄生电容的减小，元件数目的减少，输入信号的幅度的减小等。

8. 发明申请

US20050140621A1 Shift register circuit, image display apparatus having the circuit, and driving method for LCD devices 有权
公开(公告)号：US20050140621A1
公开(公告)日：2005-06-30
申请号：US11060963
申请日：2005-02-18
申请人： Yasushi Kubota , Hajime Washio , Shigeto Yoshida
发明人： Yasushi Kubota , Hajime Washio , Shigeto Yoshida
IPC分类号： G09G3/36 , G11C19/28
CPC分类号： G09G3/3688 , G09G2310/0286 , G09G2310/061 , G09G2310/08 , G09G2320/0233 , G11C19/28
摘要： A shift register circuit includes a plurality of latch circuits connected in series to sequentially transfer a pulse signal ST from one to another, a clock signal line transmitting a clock signal CLK, and a plurality of switching circuits performing electrical connection and disconnection between the clock signal line and the plurality of latch circuits. Upon turning on the shift register, at least one of the switching circuits electrically disconnects at least one of the latch circuits from the clock signal line. During an initialization period immediately after power has been turned on, the frequency of the clock signal CLK is lower than in a normal operation period and gradually increases toward the frequency used in the normal operation period.

9. 发明授权

US06618043B2 Image display device and image display method 有权
公开(公告)号：US06618043B2
公开(公告)日：2003-09-09
申请号：US09504418
申请日：2000-02-15
申请人： Hajime Washio , Yasushi Kubota , Yasuyoshi Kaise , Tamotsu Sakai , Kazuhiro Maeda
发明人： Hajime Washio , Yasushi Kubota , Yasuyoshi Kaise , Tamotsu Sakai , Kazuhiro Maeda
IPC分类号： G09G500
CPC分类号： G09G3/3648 , G09G2310/0248 , G09G2330/021
摘要： A precharge circuit is composed of (a) a reference signal input section, to which at least one precharge reference potential is inputted, (b) a control signal input section, to which at least one control signal is inputted, (c) a plurality of signal delay sections for sequentially delaying an output of the control signal input section, and (d) a reference signal switching section for switching, in accordance with outputs of the signal delay sections, between a state of outputting the precharge reference potential of the reference signal input section to each of the data signal lines and a state of non-outputting the same thereto. With this arrangement, the precharge control signal is sequentially delayed within the precharge circuit by the delay circuits composed of inverter circuits or the like, so that timings at which the precharge reference potential is written in the data signal lines are dispersed. By sequentially delaying the control signal within the precharge circuit, reduction of power consumption and excellent image display are realized.

10. 发明授权

US06580411B1 Latch circuit, shift register circuit and image display device operated with a low consumption of power 有权
标题翻译：锁存电路，移位寄存器电路和图像显示设备以低功耗运行
公开(公告)号：US06580411B1
公开(公告)日：2003-06-17
申请号：US09300178
申请日：1999-04-27
申请人： Yasushi Kubota , Hajime Washio , Ichiro Shiraki , Kazuhiro Maeda , Yasuyoshi Kaise
发明人： Yasushi Kubota , Hajime Washio , Ichiro Shiraki , Kazuhiro Maeda , Yasuyoshi Kaise
IPC分类号： G09G336
CPC分类号： H03K3/356121 , G09G3/3677 , G09G3/3688 , G09G2300/0408 , G09G2310/0286 , G09G2320/0209 , G09G2320/0257 , G09G2330/021 , H03K3/356139
摘要： If a clock signal ck is “H” and an input pulse signal in (first control signal) is “H”, then n-type transistors M15 and M16 are turned on to make an output node/OUT have the GND level. Then, a p-type transistor M12 is turned on to make an output node OUT have a Vcc (16 V) level. Thus, a latch circuit LAT operates as a level shifter circuit when first and second control signals and the clock signal ck are at “H” and operates as a level hold circuit in any other case. Therefore, the shift register circuit constructed of the latch circuit LAT functions as a low-voltage interface, and the input of the clock signal ck is stopped when the latch circuit LAT is inactive, so that the load and the consumption of power of the clock signal line are reduced.
摘要翻译：如果时钟信号ck为“H”，并且（第一控制信号）中的输入脉冲信号为“H”，则n型晶体管M15和M16导通，使输出节点/ OUT具有GND电平。然后，p型晶体管M12导通，使得输出节点OUT具有Vcc（16V）电平。因此，当第一和第二控制信号和时钟信号ck处于“H”时，锁存电路LAT作为电平移位器电路工作，并且在任何其它情况下作为电平保持电路工作。因此，由锁存电路LAT构成的移位寄存器电路用作低电压接口，并且当锁存电路LAT不活动时，时钟信号ck的输入停止，使得时钟的负载和功率的消耗信号线减少。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式