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1. 发明申请

US20130015915A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20130015915A1
公开(公告)日：2013-01-17
申请号：US13547373
申请日：2012-07-12
申请人： Yukio KOMATSU , Hitoshi Ohta , Daisuke Awano
发明人： Yukio KOMATSU , Hitoshi Ohta , Daisuke Awano
IPC分类号： H01L25/00
CPC分类号： G11C29/12005 , G11C16/00 , G11C16/0483 , G11C29/48 , G11C2029/1202
摘要： A semiconductor device including: a first pad to receive first and second test commands supplied from the outside; a voltage generator circuit to generate a test target voltage on the basis of the first and second test commands; a second pad to receive first and second monitor voltages supplied from the outside in response to respective of the first and second test commands, the first and second monitor voltages corresponding to respective lower and upper limit voltages of the test target voltage; and a comparator to output a first output signal at one of first and second logical levels by comparing the test target voltage with the first monitor voltage, and to output a second output signal at one of the first and second logical levels by comparing the test target voltage with the second monitor voltage.
摘要翻译：一种半导体器件，包括：第一焊盘，用于接收从外部提供的第一和第二测试命令; 电压发生器电路，用于基于第一和第二测试命令产生测试目标电压; 响应于第一和第二测试命令的相应而接收从外部提供的第一和第二监视电压的第二焊盘，第一和第二监视电压对应于测试目标电压的相应的下限和上限电压; 以及比较器，用于通过将测试目标电压与第一监视电压进行比较来输出第一和第二逻辑电平中的一个的第一输出信号，并且通过将测试目标进行比较来输出第一和第二逻辑电平之一的第二输出信号电压与第二显示器电压。

2. 发明申请

US20120257456A1 SEMICONDUCTOR MEMORY DEVICE AND DATA WRITE METHOD THEREOF 有权
标题翻译：半导体存储器件及其数据写入方法
公开(公告)号：US20120257456A1
公开(公告)日：2012-10-11
申请号：US13525978
申请日：2012-06-18
申请人： Yukio KOMATSU
发明人： Yukio KOMATSU
IPC分类号： G11C16/06
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/24 , G11C16/3459 , G11C2211/5621
摘要： A semiconductor memory device includes a control circuit. The control circuit executes control to perform a verify operation with respect to only a lowest threshold voltage level of a memory cell at a time of a data write operation, and to skip the verify operation with respect to the other threshold voltage levels. The control circuit determines whether a verify pass bit number of the lowest threshold voltage level, which is counted by a bit scan circuit, is a prescribed bit number or more, and the control circuit further executes control, if the verify pass bit number is the prescribed bit number or more, to perform the verify operation with respect to only the lowest threshold voltage level and a threshold voltage level that is higher than the lowest threshold voltage level, and to skip the verify operation with respect to the other threshold voltage levels.
摘要翻译：半导体存储器件包括控制电路。控制电路执行控制，以在数据写入操作时仅对存储单元的最低阈值电压电平执行验证操作，并且跳过相对于其它阈值电压电平的验证操作。控制电路确定由位扫描电路计数的最低阈值电压电平的验证通过位数是否为规定位数或更多，并且如果验证通过位数为规定的位数以上，仅对最低阈值电压电平和高于最低阈值电压电平的阈值电压电平进行验证操作，并且跳过关于其它阈值电压电平的验证操作。

3. 发明申请

US20110205807A1 SEMICONDUCTOR MEMORY DEVICE AND DATA WRITE METHOD THEREOF 有权
标题翻译：半导体存储器件及其数据写入方法
公开(公告)号：US20110205807A1
公开(公告)日：2011-08-25
申请号：US13099962
申请日：2011-05-03
申请人： Yukio KOMATSU
发明人： Yukio KOMATSU
IPC分类号： G11C16/06
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/24 , G11C16/3459 , G11C2211/5621
摘要： A semiconductor memory device includes a control circuit. The control circuit executes control to perform a verify operation with respect to only a lowest threshold voltage level of a memory cell at a time of a data write operation, and to skip the verify operation with respect to the other threshold voltage levels. The control circuit determines whether a verify pass bit number of the lowest threshold voltage level, which is counted by a bit scan circuit, is a prescribed bit number or more, and the control circuit further executes control, if the verify pass bit number is the prescribed bit number or more, to perform the verify operation with respect to only the lowest threshold voltage level and a threshold voltage level that is higher than the lowest threshold voltage level, and to skip the verify operation with respect to the other threshold voltage levels.
摘要翻译：半导体存储器件包括控制电路。控制电路执行控制，以在数据写入操作时仅对存储单元的最低阈值电压电平执行验证操作，并且跳过相对于其它阈值电压电平的验证操作。控制电路确定由位扫描电路计数的最低阈值电压电平的验证通过位数是否为规定位数或更多，并且如果验证通过位数为规定的位数以上，仅对最低阈值电压电平和高于最低阈值电压电平的阈值电压电平进行验证操作，并且跳过关于其它阈值电压电平的验证操作。

4. 发明申请

US20100061148A1 SEMICONDUCTOR MEMORY DEVICE AND DATA WRITE METHOD THEREOF 有权
标题翻译：半导体存储器件及其数据写入方法
公开(公告)号：US20100061148A1
公开(公告)日：2010-03-11
申请号：US12535040
申请日：2009-08-04
申请人： Yukio KOMATSU
发明人： Yukio KOMATSU
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/24 , G11C16/3459 , G11C2211/5621
摘要： A semiconductor memory device includes a control circuit. The control circuit executes control to perform a verify operation with respect to only a lowest threshold voltage level of a memory cell at a time of a data write operation, and to skip the verify operation with respect to the other threshold voltage levels. The control circuit determines whether a verify pass bit number of the lowest threshold voltage level, which is counted by a bit scan circuit, is a prescribed bit number or more, and the control circuit further executes control, if the verify pass bit number is the prescribed bit number or more, to perform the verify operation with respect to only the lowest threshold voltage level and a threshold voltage level that is higher than the lowest threshold voltage level, and to skip the verify operation with respect to the other threshold voltage levels.
摘要翻译：半导体存储器件包括控制电路。控制电路执行控制，以在数据写入操作时仅对存储单元的最低阈值电压电平执行验证操作，并且跳过相对于其它阈值电压电平的验证操作。控制电路确定由位扫描电路计数的最低阈值电压电平的验证通过位数是否为规定位数或更多，并且如果验证通过位数为规定的位数以上，仅对最低阈值电压电平和高于最低阈值电压电平的阈值电压电平进行验证操作，并且跳过关于其它阈值电压电平的验证操作。

5. 发明申请

US20120254518A1 MEMORY SYSTEM 审中-公开
标题翻译：记忆系统
公开(公告)号：US20120254518A1
公开(公告)日：2012-10-04
申请号：US13425989
申请日：2012-03-21
申请人： Yukio KOMATSU
发明人： Yukio KOMATSU
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： G06F12/0246 , G06F2212/7204 , G11C16/04 , G11C16/0483 , G11C29/08 , G11C29/76 , G11C2029/4402
摘要： A memory system includes: a plurality of word lines; a plurality of bit lines; a plurality of memory cells each having a control gate and a drain end, the control gate being connected to one of the word lines, the drain end being connected to one of the bit lines; a memory cell array including a plurality of blocks, each of the blocks including a plurality of pages, each of the pages being including a plurality of the memory cells; and a storage area configured to hold good block data identifying whether or not each of the blocks is a good block based on the number of fail bits in each page in the good block being less than or equal to a first threshold, wherein the first threshold is smaller than a second threshold used for identifying whether or not each of the blocks is a bad block.
摘要翻译：存储器系统包括：多个字线; 多个位线; 每个具有控制栅极和漏极端的多个存储单元，所述控制栅极连接到所述字线之一，所述漏极端连接到所述位线之一; 包括多个块的存储单元阵列，每个块包括多个页，每个页包括多个存储单元; 以及存储区域，其被配置为保存良好块数据，其基于所述好块中的每个页中的故障位的数量小于或等于第一阈值来识别每个块是否是良好块，其中所述第一阈值小于用于识别每个块是否是坏块的第二阈值。

6. 发明申请

US20110063909A1 NONVOLATILE SEMICONDUCTOR MEMORY AND METHOD OF TESTING THE SAME 审中-公开
标题翻译：非易失性半导体存储器及其测试方法
公开(公告)号：US20110063909A1
公开(公告)日：2011-03-17
申请号：US12713674
申请日：2010-02-26
申请人： Yukio KOMATSU
发明人： Yukio KOMATSU
IPC分类号： G11C16/06 , G11C16/04 , G11C29/00
CPC分类号： G11C29/28 , G11C16/04 , G11C29/50012
摘要： A memory cell array and a peripheral circuit are provided. The memory cell array has a plurality of blocks which are erasing units respectively. Each of the blocks includes a plurality of memory cells. A block control unit operates according to input signals from outside and controls operation of the blocks. A ready/busy control circuit outputs a busy signal during a period of operation implementation for a block selected from the blocks, in response to an output from the block control unit. The ready/busy control circuit outputs a ready signal out of the period of the operation implementation for the selected block. A registration control unit registers the selected block as a bad block, in the case that the ready/busy control circuit outputs a busy signal when the registration control unit receives a bad block identification command.
摘要翻译：提供存储单元阵列和外围电路。存储单元阵列具有分别是擦除单元的多个块。每个块包括多个存储单元。块控制单元根据来自外部的输入信号进行操作并控制块的操作。响应于来自块控制单元的输出，就绪/忙控制电路在从块中选择的块的操作实施期间输出忙信号。准备/繁忙控制电路在所选块的操作实施期间输出就绪信号。在登录控制单元接收到不良块识别命令时，就绪/忙控制电路输出忙信号的情况下，登记控制单元将所选择的块登记为坏块。

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