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1. 发明授权

US4104358A Selective extraction of yttrium ions 失效
标题翻译：选择性提取钇离子
公开(公告)号：US4104358A
公开(公告)日：1978-08-01
申请号：US804465
申请日：1977-06-07
申请人： Yukinori Minagawa , Tsugio Kaneko , Fumikazu Yajima , Kunihiko Yamaguchi , Toshihiko Yoshitomi
发明人： Yukinori Minagawa , Tsugio Kaneko , Fumikazu Yajima , Kunihiko Yamaguchi , Toshihiko Yoshitomi
IPC分类号： C22B59/00 , C01F17/00
CPC分类号： C01F17/0006
摘要： Yttrium ions are selectively extracted by contacting an acid phosphoric ester with an aqueous solution containing diethylenetriaminepentaacetic acid and yttrium ions and one or more heavy rare earth (atomic number of 64 to 71) ions.
摘要翻译：通过使酸性磷酸酯与含有二亚乙基三胺五乙酸和钇离子的水溶液和一种或多种重稀土离子（原子序数64至71）的离子接触来选择性地提取钇离子。

2. 发明授权

US4201747A Method of separating yttrium ions 失效
标题翻译：分离钇离子的方法
公开(公告)号：US4201747A
公开(公告)日：1980-05-06
申请号：US949010
申请日：1978-10-06
申请人： Yukinori Minagawa , Tsugio Kaneko , Kunihiko Yamaguchi
发明人： Yukinori Minagawa , Tsugio Kaneko , Kunihiko Yamaguchi
IPC分类号： C22B3/38 , C22B3/40 , C22B59/00 , C01F17/00
CPC分类号： C22B3/0095 , C22B3/0087 , C22B59/00 , Y02P10/234 , Y10S423/14
摘要： Yttrium ions are selectively separated by extracting the yttrium ions by contacting an aqueous solution containing hydroxyethyl ethylenediaminetriacetic acid, yttrium ions and lanthanide ions with an extracting solvent containing tributyl phosphate and an acid phosphoric ester having the formula ##STR1## wherein R.sup.1 represents hydrogen atom or an alkyl group having the formula ##STR2## wherein n is an integer of 6 to 15 and m is n-1 or n-2; and R.sup.2 represents an alkyl group having the formula ##STR3## wherein n is an integer of 6 to 15 and m is n-1 or n-2.
摘要翻译：通过使包含羟乙基乙二胺三乙酸，钇离子和镧系元素离子的水溶液与含有磷酸三丁酯的萃取溶剂和具有式（I）的酸式磷酸酯接触来提取钇离子来选择性分离钇离子，其中R1表示氢原子或具有式“IMAGE”的烷基，其中n为6至15的整数，m为n-1或n-2; 并且R 2表示具有式“IMAGE”的烷基，其中n为6至15的整数，m为n-1或n-2。

3. 发明授权

US4865823A Method for recovering gallium 失效
标题翻译：镓的回收方法
公开(公告)号：US4865823A
公开(公告)日：1989-09-12
申请号：US229736
申请日：1988-08-03
申请人： Yukinori Minagawa , Minoru Tanaka , Kunihiko Yamaguchi , Kazumasa Arai , Gouichi Muramatsu
发明人： Yukinori Minagawa , Minoru Tanaka , Kunihiko Yamaguchi , Kazumasa Arai , Gouichi Muramatsu
IPC分类号： B01J45/00 , C01G15/00
CPC分类号： C01G15/003 , B01J45/00 , C22B3/24 , Y02P10/234 , Y10S423/14
摘要： A method for recovering gallium, which comprises a capturing step of contacting an aqueous solution containing gallium to a chelating agent containing a water-insoluble substituted quinolinol as the active ingredient, to let the chelating agent capture gallium, and an eluting step of contacting an eluting solution composed of an aqueous solution of an acid or strong base containing said substituted quinolinol, to the chelating agent from the capturing step, to elute gallium therefrom.
摘要翻译：一种回收镓的方法，其包括将含有镓的水溶液与含有不溶于水的取代的羟基喹啉的螯合剂作为活性成分接触以使螯合剂捕获镓的捕获步骤，以及使洗脱步骤由含有所述取代的羟基喹啉的酸或强碱的水溶液组成的溶液与捕获步骤的螯合剂一起从其中洗脱镓。

4. 发明授权

US06998878B2 Semiconductor integrated circuit and semiconductor logic circuit used in the integrated circuit 失效
标题翻译：集成电路中使用的半导体集成电路和半导体逻辑电路
公开(公告)号：US06998878B2
公开(公告)日：2006-02-14
申请号：US10754596
申请日：2004-01-12
申请人： Kazuo Kanetani , Hiroaki Nambu , Kaname Yamasaki , Takeshi Kusunoki , Keiichi Higeta , Kunihiko Yamaguchi , Fumihiko Arakawa
发明人： Kazuo Kanetani , Hiroaki Nambu , Kaname Yamasaki , Takeshi Kusunoki , Keiichi Higeta , Kunihiko Yamaguchi , Fumihiko Arakawa
IPC分类号： H03K19/20
CPC分类号： G11C8/10
摘要： To speed up the operation of a decoder circuit, reduce the power consumption of the decoder circuit and increase the cycle, each circuit such as a buffer, a predecoder and a main decoder in the decoder circuit includes a semiconductor logic circuit in which the number of columns of transistors for pulling down at an output node is small, even if the number of inputs is many and the true and a complementary output signal having approximately the same delay time are acquired and the output pulse length of each circuit in the decoder circuit is reduced. With this arrangement, the operation of the decoder circuit can be sped up, the power consumption can be reduced, the cycles can be increased and, in a semiconductor memory, for example, access time and power consumption can be reduced and the cycles can be increased.
摘要翻译：为了加速解码器电路的运行，降低解码器电路的功耗并增加周期，解码器电路中的每个电路如缓冲器，预解码器和主译码器都包括半导体逻辑电路，其中，在输出节点下拉的晶体管列很小，即使输入数量很多，并且获得了真实的和具有大致相同延迟时间的互补输出信号，并且解码器电路中每个电路的输出脉冲长度是减少利用这种布置，可以加速解码器电路的操作，可以降低功耗，可以提高周期，例如，在半导体存储器中，可以减少访问时间和功耗，并且可以将周期增加。

5. 发明授权

US5163022A Semiconductor cell memory with current sensing 失效
标题翻译：具有电流检测功能的半导体单元存储器
公开(公告)号：US5163022A
公开(公告)日：1992-11-10
申请号：US827873
申请日：1992-01-30
申请人： Noriyuki Homma , Hiroaki Nambu , Kunihiko Yamaguchi , Tohru Nakamura , Youji Idei , Kazuo Kanetani , Kenichi Ohhata , Yoshiaki Sakurai , Hisayuki Higuchi
发明人： Noriyuki Homma , Hiroaki Nambu , Kunihiko Yamaguchi , Tohru Nakamura , Youji Idei , Kazuo Kanetani , Kenichi Ohhata , Yoshiaki Sakurai , Hisayuki Higuchi
IPC分类号： G11C7/06 , G11C11/411 , G11C11/412 , G11C11/416 , G11C11/419
CPC分类号： G11C11/4113 , G11C11/412 , G11C11/416 , G11C11/419 , G11C7/062
摘要： The disclosure includes feeding a current I.sub.R to only BIT lines selected, or feeding current I.sub.R transiently to only the BIT lines switched from unselected to selected states; and a sense amplifier for detecting the difference between the currents flowing in selected BIT lines to read out stored information, wherein current I.sub.R and cell current I.sub.cell have a relation of I.sub.R >I.sub.cell. The BiC MOS memory has high speed, low power and high integration density. Diodes are provided between the memory cell and the BIT lines.
摘要翻译：本公开包括将电流IR馈送到仅选择的BIT线，或者将电流IR瞬时馈送到仅从未选择状态切换到选定状态的BIT线; 以及读出放大器，用于检测在所选择的BIT行中流动的电流之间的差以读出存储的信息，其中当前的IR和单元电流Icell具有IR> Icell的关系。 BiC MOS存储器具有高速度，低功耗和高集成度。在存储单元和BIT线之间提供二极管。

6. 发明授权

US4642486A Decoder circuit using transistors or diodes of different characteristics 失效
标题翻译：解码电路采用晶体管或二极管的不同特性
公开(公告)号：US4642486A
公开(公告)日：1987-02-10
申请号：US686660
申请日：1984-12-27
申请人： Noriyuki Honma , Hiroaki Nambu , Isao Yoshida , Hisayuki Higuchi , Kunihiko Yamaguchi
发明人： Noriyuki Honma , Hiroaki Nambu , Isao Yoshida , Hisayuki Higuchi , Kunihiko Yamaguchi
IPC分类号： G11C11/413 , G11C11/34 , H03K17/60 , H03K17/62 , H03K19/013 , G11C8/00 , H03K19/082 , H03K19/092
CPC分类号： H03K17/603 , H03K17/6214
摘要： This invention is effective in the speeding up of a decoder circuit and maintenance of output amplitude. The invention is characterized in that, in a decoder circuit composed of a multi-emitter transistor or at least one diode group in which the anodes of a plurality of diodes are connected, and a charge circuit having an output emitter follower transistor, the multi-emitter transistor or the forward voltage of the diodes are larger than the voltage between the base and the emitter of the output emitter follower transistor.
摘要翻译：本发明在解码器电路的加速和输出振幅的维持方面是有效的。本发明的特征在于，在由多个发射极晶体管组成的解码器电路或连接有多个二极管的阳极的至少一个二极管组以及具有输出射极跟随器晶体管的充电电路的情况下，发射极晶体管或二极管的正向电压大于输出射极跟随器晶体管的基极和发射极之间的电压。

7. 发明授权

US6034912A Semiconductor integrated circuit device and method of manufacturing the same 失效
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US6034912A
公开(公告)日：2000-03-07
申请号：US145076
申请日：1998-09-01
申请人： Satoru Isomura , Atsushi Shimizu , Keiichi Higeta , Tohru Kobayashi , Takeo Yamada , Yuko Ito , Kengo Miyazawa , Kunihiko Yamaguchi
发明人： Satoru Isomura , Atsushi Shimizu , Keiichi Higeta , Tohru Kobayashi , Takeo Yamada , Yuko Ito , Kengo Miyazawa , Kunihiko Yamaguchi
IPC分类号： G11C5/02 , H01L27/02 , H03K19/177
CPC分类号： H03K19/1776 , G11C5/025 , H01L27/0207 , H03K19/1774 , H03K19/17792 , H03K19/17796
摘要： A memory portion and a logic circuit portion of a semiconductor device are formed on a single semiconductor substrate in which a first logic circuit block and a second logic circuit block are formed in different areas and the second logic circuit is located between a pair of memory blocks. Data stored in the pair of memory blocks are transmitted to the second logic circuit block for processing via a memory peripheral circuit. A result of the data processing is transmitted to the first logic circuit block or an external device via an input/output circuit provided in the second logic circuit block. A clock signal entered at the center portion of the semiconductor chip is supplied to a plurality of first state clock distributing circuits equidistantly disposed from the center portion and then to a plurality of second stage clock distributing circuits at least equidistantly disposed from each of the first state clock distributing circuits. Next, the clock signal is supplied to a plurality of third state clock distributing circuits equidistantly disposed from each of the second stage clock distributing circuits and then supplied to a plurality of final stage clock distributing circuits equidistantly disposed from each of the third stage clock distributing circuits. From these final stage clock distributing circuits, the clock signal is supplied to an area in whose units an internal gate array and a RAM macro cell or a logic macro cell are made replaceable with each other.
摘要翻译：半导体器件的存储部分和逻辑电路部分形成在单个半导体衬底上，其中第一逻辑电路块和第二逻辑电路块形成在不同的区域中，并且第二逻辑电路位于一对存储块之间。存储在一对存储器块中的数据被发送到第二逻辑电路块，以经由存储器外围电路进行处理。经由第二逻辑电路块中提供的输入/输出电路将数据处理的结果发送到第一逻辑电路块或外部设备。输入到半导体芯片的中心部分的时钟信号被提供给从中心部分等距设置的多个第一状态时钟分配电路，然后被提供给至少等距地从第一状态中的每个状态设置的多个第二级时钟分配电路时钟分配电路。接下来，时钟信号被提供给从每个第二级时钟分配电路等距离设置的多个第三状态时钟分配电路，然后提供给从每个第三级时钟分配电路等距设置的多个最后级时钟分配电路。从这些最终级时钟分配电路，将时钟信号提供给其单位内的内部门阵列和RAM宏小区或逻辑宏小区彼此可替换的区域。

8. 发明授权

US4809052A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4809052A
公开(公告)日：1989-02-28
申请号：US860413
申请日：1986-05-07
申请人： Yasushiro Nishioka , Takeo Shiba , Hiroshi Shinriki , Kiichiro Mukai , Akihisa Uchida , Ichiro Mitamura , Keiichi Higeta , Katsumi Ogiue , Kunihiko Yamaguchi , Noriyuki Sakuma
发明人： Yasushiro Nishioka , Takeo Shiba , Hiroshi Shinriki , Kiichiro Mukai , Akihisa Uchida , Ichiro Mitamura , Keiichi Higeta , Katsumi Ogiue , Kunihiko Yamaguchi , Noriyuki Sakuma
IPC分类号： G11C11/411 , H01L27/102 , H01L27/10 , H01L29/40 , H01L29/48
CPC分类号： G11C11/4116 , H01L27/1025
摘要： A semiconductor memory device is provided such as the type having flip-flop memory cells each including two bipolar transistors in cross connection with each other. In certain embodiments, at least a part of a Schottky barrier diode or capacitor in the memory cell is formed under a digit line. This memory device is greatly reduced in its required area, and the Schottky barrier diode and capacitor are negligibly influenced by the digit line. In other embodiments, it is arranged to provide different electrodes for the Schottky barrier diode and the capacitor to optimize construction in a minimized space.
摘要翻译：提供半导体存储器件，例如具有触发器存储单元的类型，每个触发器存储单元包括彼此交叉连接的两个双极晶体管。在某些实施例中，在数字线下形成存储单元中的肖特基势垒二极管或电容器的至少一部分。该存储器件的所需面积大大降低，肖特基势垒二极管和电容器受数字线影响不大。在其他实施例中，它被设置为为肖特基势垒二极管和电容器提供不同的电极，以在最小化的空间中优化结构。

9. 发明授权

US4727265A Semiconductor circuit having a current switch circuit which imparts a latch function to an input buffer for generating high amplitude signals 失效
标题翻译：具有电流开关电路的半导体电路，其向输入缓冲器提供锁存功能，用于产生高幅度信号
公开(公告)号：US4727265A
公开(公告)日：1988-02-23
申请号：US755910
申请日：1985-07-17
申请人： Hiroaki Nanbu , Noriyuki Honma , Kunihiko Yamaguchi , Kazuo Kanetani , Goro Kitsukawa
发明人： Hiroaki Nanbu , Noriyuki Honma , Kunihiko Yamaguchi , Kazuo Kanetani , Goro Kitsukawa
IPC分类号： G11C11/414 , G11C11/41 , H03K17/30 , H03K17/60 , H03K17/62 , H03K17/693 , H03K17/16 , H03K19/00 , H03K19/092 , H03L5/00
CPC分类号： H03K17/693 , H03K17/603 , H03K17/6292
摘要： A semiconductor circuit of a current mode type logic is provided having a reference voltage generating circuit which generates the reference voltage to be applied to the logic circuit in response to a clock signal to latch the state corresponding to an input signal at an instant of the clock signal input. The reference voltage has three levels in response to the voltage levels of the clock signal and the input signal: a middle voltage between the two high and low voltage levels of the input signal when the clock signal is at a first level voltage; a voltage higher than the high voltage level of the input signal when the clock signal is at a second level voltage and the output signal is at a high voltage; and a voltage lower than the low voltage level of the input signal when the clock signal is at a second level voltage and the output signal is at a second level voltage and the output signal is at a low voltage. This semiconductor circuit can relax restrictions on the signal amplitude due to the supply voltage and the saturation of the transistors, and, accordingly, allows processing signals having a much greater amplitude than was previously possible.
摘要翻译：提供电流模式型逻辑的半导体电路，其具有参考电压产生电路，该参考电压产生电路响应于时钟信号产生要施加到逻辑电路的参考电压，以在时钟瞬间锁存对应于输入信号的状态信号输入。参考电压响应于时钟信号和输入信号的电压电平而具有三个电平：当时钟信号处于第一电平电压时，输入信号的两个高电平和低电平电平之间的中间电压; 当所述时钟信号处于第二电平电压并且所述输出信号处于高电压时，所述电压高于所述输入信号的高电压电平; 以及当所述时钟信号处于第二电平电压并且所述输出信号处于第二电平电压且所述输出信号处于低电压时，所述电压低于所述输入信号的低电压电平。该半导体电路可以放宽由于晶体管的电源电压和饱和度导致的对信号幅度的限制，因此允许处理具有比之前可能的幅度大得多的信号。

10. 发明授权

US4461992A Temperature-compensated current source circuit and a reference voltage generating circuit using the same 失效
标题翻译：温度补偿电流源电路和使用其的参考电压发生电路
公开(公告)号：US4461992A
公开(公告)日：1984-07-24
申请号：US367676
申请日：1982-04-12
申请人： Kunihiko Yamaguchi , Noriyuki Homma
发明人： Kunihiko Yamaguchi , Noriyuki Homma
IPC分类号： G05F1/56 , G05F1/567 , G05F3/30 , G05F3/20
CPC分类号： G05F1/567 , G05F3/30 , Y10S323/907
摘要： A current source circuit includes a first and a second transistor connected at the collector to a common load resistor. In the current source circuit, the emiiters of the first and second transistors are connected to a negative power source through different current restricting resistors. The base of the first transistor is biased by a series circuit including two diodes. The temperature coefficients of the collector currents of the first and second transistors are offset, so that the temperature-compensated current flows into the load resistor.
摘要翻译：电流源电路包括在集电极处连接到公共负载电阻器的第一和第二晶体管。在电流源电路中，第一和第二晶体管的发射器通过不同的电流限制电阻器连接到负电源。第一晶体管的基极由包括两个二极管的串联电路偏置。第一和第二晶体管的集电极电流的温度系数偏移，使得温度补偿电流流入负载电阻器。

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