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1. 发明授权

US08493991B2 Serial bus transmission system 有权
标题翻译：串行总线传输系统
公开(公告)号：US08493991B2
公开(公告)日：2013-07-23
申请号：US12988939
申请日：2009-04-20
申请人： Yuji Kasai , Eiichi Takahashi , Masahiro Murakawa , Tetsuya Higuchi
发明人： Yuji Kasai , Eiichi Takahashi , Masahiro Murakawa , Tetsuya Higuchi
IPC分类号： H04B7/212 , H04B1/44 , H04Q11/00 , H04J3/00 , H04L12/40 , H04L7/00 , H04W4/00
CPC分类号： H04L12/4035
摘要： A master node (12) sends an identification signal for designating a communication channel in an identification signal time slot. When the own node matches the node in which the communication channel designated by the identification signal sent from the master node (12) is set in the identification signal time slot, the master node (12) and slave nodes (131 to 13n) each perform data transmission via the communication channel, based on the set contents of the communication channel, in the data transmission time slot corresponding to the identification signal time slot in which the identification signal has been sent.
摘要翻译：主节点（12）在识别信号时隙中发送用于指定通信信道的识别信号。当自身节点与在主节点（12）发送的识别信号指定的通信信道被设置在识别信号时隙中的节点匹配时，主节点（12）和从节点（131至13n）各自执行在与发送识别信号的识别信号时隙对应的数据传输时隙中，基于通信信道的设定内容，经由通信信道的数据传输。

2. 发明申请

US20050179465A1 High-speed signal transmission system 失效
标题翻译：高速信号传输系统
公开(公告)号：US20050179465A1
公开(公告)日：2005-08-18
申请号：US10511720
申请日：2003-04-21
申请人： Kanji Otsuka , Tamotsu Usami , Tetsuya Higuchi , Eiichi Takahashi , Yuji Kasai , Masahiro Murakawa
发明人： Kanji Otsuka , Tamotsu Usami , Tetsuya Higuchi , Eiichi Takahashi , Yuji Kasai , Masahiro Murakawa
IPC分类号： H04B3/04 , H04L25/02 , G06F11/00
CPC分类号： H04B3/04 , H01L2224/48227 , H01L2924/12032 , H01L2924/1305 , H01L2924/13091 , H01L2924/19107 , H04L25/0286 , H01L2924/00
摘要： A purpose of a high-speed signal transmission system of the present invention is to pass a high-speed digital signal through an outside-chip line exchanging a signal with a high speed LSI chip with a band higher than GHz. The high-speed signal transmission system of the present invention has a configuration of: insertion of a circuit for feeding back received information and adjusting a waveform at a sending side based on genetic algorithm; a device structure for automatically performing pump up and pump down of a transistor carrier; a transmission line of a wiring out of a transistor; and elimination of a common power source of a circuit.
摘要翻译：本发明的高速信号传输系统的目的是通过外部芯片线路将高速数字信号与具有高于GHz的频带的高速LSI芯片交换信号。本发明的高速信号传输系统具有以下结构：基于遗传算法插入用于反馈接收信息的电路和调整发送侧的波形; 用于自动地执行泵浦和泵浦晶体管载体的装置结构; 晶体管的布线传输线; 并消除电路的公共电源。

3. 发明申请

US20110142066A1 SERIAL BUS TRANSMISSION SYSTEM 有权
标题翻译：串行总线传输系统
公开(公告)号：US20110142066A1
公开(公告)日：2011-06-16
申请号：US12988939
申请日：2009-04-20
申请人： Yuji Kasai , Eiichi Takahashi , Masahiro Murakawa , Tetsuya Higuchi
发明人： Yuji Kasai , Eiichi Takahashi , Masahiro Murakawa , Tetsuya Higuchi
IPC分类号： H04B7/212
CPC分类号： H04L12/4035
摘要： A master node (12) sends an identification signal for designating a communication channel in an identification signal time slot. When the own node matches the node in which the communication channel designated by the identification signal sent from the master node (12) is set in the identification signal time slot, the master node (12) and slave nodes (131 to 13n) each perform data transmission via the communication channel, based on the set contents of the communication channel, in the data transmission time slot corresponding to the identification signal time slot in which the identification signal has been sent.
摘要翻译：主节点（12）在识别信号时隙中发送用于指定通信信道的识别信号。当自身节点与在主节点（12）发送的识别信号指定的通信信道被设置在识别信号时隙中的节点匹配时，主节点（12）和从节点（131至13n）各自执行在与发送识别信号的识别信号时隙对应的数据传输时隙中，基于通信信道的设定内容，经由通信信道的数据传输。

4. 发明授权

US07447289B2 Signal timing adjustment device, signal timing adjustment system, signal timing adjustment amount setting program, and storage medium storing the program 失效
标题翻译：信号定时调整装置，信号定时调整系统，信号定时调整量设定程序以及存储该程序的存储介质
公开(公告)号：US07447289B2
公开(公告)日：2008-11-04
申请号：US10809374
申请日：2004-03-26
申请人： Munehiro Uratani , Eiichi Takahashi , Yuji Kasai , Tetsuya Higuchi , Masahiro Murakawa
发明人： Munehiro Uratani , Eiichi Takahashi , Yuji Kasai , Tetsuya Higuchi , Masahiro Murakawa
IPC分类号： H04L7/00
CPC分类号： H04L7/0337 , H03L7/087
摘要： Delay time between an input of data to a circuit block and an output of the data from the data block is measured in accordance with a timing at which the data from the circuit block is acquired by a measurement register and a timing at which the data from the circuit block is acquired by a data latch. An LSI tester sets well voltage adjustment values so that delay time of each circuit block is averaged. From voltages generated by the adjustment voltage generating circuit, a selector selects voltages that are in accordance with the well voltage adjustment values. The voltages selected are applied to a well of a CMOS transistor of each clock timing adjustment circuit. Delay time between timings of inputted clocks is thus adjusted.
摘要翻译：根据来自电路块的数据通过测量寄存器获取的定时和来自数据块的数据的定时，测量数据到电路块的数据输入与来自数据块的数据的输出之间的延迟时间电路块由数据锁存器获取。 LSI测试仪设置好的电压调整值，使得每个电路块的延迟时间被平均。根据由调整电压产生电路产生的电压，选择器选择与电压调节值相一致的电压。所选择的电压被施加到每个时钟定时调整电路的CMOS晶体管的阱。因此调整输入时钟的定时之间的延迟时间。

5. 发明申请

US20060236146A1 Digital system, clock signal adjusting method for digital system, recording medium recording processing program executed in the adjusting method 审中-公开
标题翻译：数字系统，数字系统的时钟信号调整方法，以调整方式执行的记录介质记录处理程序
公开(公告)号：US20060236146A1
公开(公告)日：2006-10-19
申请号：US10559672
申请日：2004-06-03
申请人： Eiichi Takahashi , Masahiro Murakawa , Yuji Kasai , Tetsuya Higuchi
发明人： Eiichi Takahashi , Masahiro Murakawa , Yuji Kasai , Tetsuya Higuchi
IPC分类号： G06F1/12
CPC分类号： G06F1/10 , G01R31/31725 , G01R31/31726 , H03K2005/00058 , H03K2005/00156 , H03K2005/0026
摘要： A digital system (1) which performs a digital processing according to a single or a plurality of clock signals to deliver a specified basic function, and which comprises a plurality of delay elements (4) respectively inserted into a plurality of clock circuits for supplying clock signals in a digital system, and respectively constituted by circuit elements for changing delay times according to values indicated by a control signal, and a plurality of holding circuits (5) for holding a plurality of control signals to be given to a plurality of delay elements. The plurality of holding circuits have a plurality of control signal values, held by these holding circuits, changed by external devices (6-8) according to a probabilistic search method with the digital system (1) supplied with power from a variable-output-voltage power supply (14) so that the basic function of the digital system satisfies specified specifications.
摘要翻译：一种数字系统（1），其根据单个或多个时钟信号执行数字处理以传送指定的基本功能，并且包括分别插入到多个时钟电路中的多个延迟元件（4），用于提供时钟信号，并且分别由用于根据控制信号指示的值改变延迟时间的电路元件构成，以及多个保持电路（5），用于保持多个控制信号被提供给多个延迟元件。多个保持电路具有由这些保持电路保持的多个控制信号值，根据概率搜索方法由外部设备（6-8）改变，数字系统（1）从可变输出 - 电压电源（14），使数字系统的基本功能满足规定的规格。

6. 发明授权

US07295032B2 High-speed signal transmission system 失效
标题翻译：高速信号传输系统
公开(公告)号：US07295032B2
公开(公告)日：2007-11-13
申请号：US10511720
申请日：2003-04-21
申请人： Kanji Otsuka , Tamotsu Usami , Tetsuya Higuchi , Eiichi Takahashi , Yuji Kasai , Masahiro Murakawa
发明人： Kanji Otsuka , Tamotsu Usami , Tetsuya Higuchi , Eiichi Takahashi , Yuji Kasai , Masahiro Murakawa
IPC分类号： H03K17/16
CPC分类号： H04B3/04 , H01L2224/48227 , H01L2924/12032 , H01L2924/1305 , H01L2924/13091 , H01L2924/19107 , H04L25/0286 , H01L2924/00
摘要： A purpose of a high-speed signal transmission system of the present invention is to pass a high-speed digital signal through an outside-chip line exchanging a signal with a high speed LSI chip with a band higher than GHz. The high-speed signal transmission system of the present invention has a configuration of: insertion of a circuit for feeding back received information and adjusting a waveform at a sending side based on genetic algorithm; a device structure for automatically performing pump up and pump down of a transistor carrier; a transmission line of a wiring out of a transistor; and elimination of a common power source of a circuit.
摘要翻译：本发明的高速信号传输系统的目的是通过外部芯片线路将高速数字信号与具有高于GHz的频带的高速LSI芯片交换信号。本发明的高速信号传输系统具有以下结构：基于遗传算法插入用于反馈接收信息的电路和调整发送侧的波形; 用于自动地执行泵浦和泵浦晶体管载体的装置结构; 晶体管的布线传输线; 并消除电路的公共电源。

7. 发明申请

US20130089120A1 SPECTRUM SPREAD COMMUNICATION SYSTEM 有权
标题翻译：光谱传播通信系统
公开(公告)号：US20130089120A1
公开(公告)日：2013-04-11
申请号：US13704087
申请日：2011-06-06
申请人： Yuji Kasai , Masahiro Murakawa , Tetsuya Higuchi
发明人： Yuji Kasai , Masahiro Murakawa , Tetsuya Higuchi
IPC分类号： H04B1/7075
CPC分类号： H04B1/7075 , H04B1/707 , H04B1/7073 , H04B1/70735 , H04B3/542 , H04B2203/5416 , H04J13/16
摘要： Disclosed is a spectrum spread communication system which is hardly influenced by noises, and in which a frame structure can be identified at a receiving side without use of a frame synchronization signal. A spread code generator switches spread codes (“Scai” and “Scbi”) in each frame, and outputs it to a spread modulation unit. The spread modulation unit performs spread modulation of transmission data, and transmits it to a direct current power line. A reference code generator generates reference codes (“Scai” and “Scbi”) in the same code phase. Spread demodulation units performs spread demodulation of the received signal with use of the reference codes (“Scai” and “Scbi”), and output it to a selection unit. A frame synchronization detection unit identifies a frame structure on the basis of switching of a synchronization state of a code phase in a code phase synchronization detection unit. The selection unit outputs reception data by selecting spread demodulated data from the spread demodulation unit which is in a phase-synchronized state.
摘要翻译：公开了几乎不受噪声影响的频谱扩展通信系统，其中可以在接收侧识别帧结构而不使用帧同步信号。扩频码发生器在每帧中切换扩频码（Scai和Scbi），并将其输出到扩展调制单元。扩展调制单元执行发送数据的扩展调制，并将其发送到直流电力线。参考代码生成器在相同的代码阶段生成参考代码（Scai和Scbi）。扩展解调单元使用参考码（Scai和Scbi）对接收信号进行扩展解调，并将其输出到选择单元。帧同步检测单元基于码相位同步检测单元中的码相位的同步状态的切换来识别帧结构。选择单元通过从相位同步状态的扩展解调单元中选择扩展解调数据来输出接收数据。

8. 发明授权

US06861848B2 Capacitance position sensor and position controller equipped with the sensor 失效
标题翻译：电容位置传感器和位置控制器配有传感器
公开(公告)号：US06861848B2
公开(公告)日：2005-03-01
申请号：US10279846
申请日：2002-10-25
申请人： Yuji Kasai , Hirokazu Nosato , Masahiro Murakawa , Taro Itatani , Tetsuya Higuchi
发明人： Yuji Kasai , Hirokazu Nosato , Masahiro Murakawa , Taro Itatani , Tetsuya Higuchi
IPC分类号： G01D5/24 , G01D5/241 , H01S3/086 , H01S3/105 , H01S3/139 , G01R27/26
CPC分类号： G01D5/24 , G01D5/2417 , H01S3/105
摘要： A capacitance position sensor includes a pair of opposed tabular electrodes, an LC oscillator circuit having a toroidal core winding and whose oscillating frequency varies with change in capacitance between the pair of electrodes, and an arithmetic processing unit for calculating an absolute value of a distance between the electrodes from the oscillating frequency of the oscillator circuit. A position controller includes a stationary member formed with one electrode of the pair of electrodes of the position sensor, a movable member on which the other electrode of the pair of electrodes is formed, and moving device for moving the movable member relative to the stationary member.
摘要翻译：电容位置传感器包括一对相对的平板电极，具有环形铁芯绕组的振荡频率随着一对电极之间的电容变化而变化的LC振荡器电路，以及运算处理单元，用于计算在一对电极之间的距离的绝对值电极从振荡电路的振荡频率。位置控制器包括：固定构件，其形成有位置传感器的一对电极的一个电极，形成有该对电极的另一个电极的可动构件;以及用于使可动构件相对于固定构件移动的移动装置。

9. 发明授权

US07583749B2 Digital data transmitting apparatus 失效
标题翻译：数字数据发送装置
公开(公告)号：US07583749B2
公开(公告)日：2009-09-01
申请号：US10569274
申请日：2004-09-07
申请人： Yuji Kasai , Masahiro Murakawa , Tetsuya Higuchi
发明人： Yuji Kasai , Masahiro Murakawa , Tetsuya Higuchi
IPC分类号： H04L25/49
CPC分类号： H04L27/368 , H04L5/14 , H04L25/03343
摘要： A transmitting circuit 10 converts transmission data to a multilevel analog signal suitable for transmission. The multilevel analog signal is output to a cable 21 via an amplifier and a hybrid circuit 12. In the transmitting circuit 10, a waveform which compensates waveform deterioration at the cable 21 is generated. A reception signal from the cable 21 is input to a mixer 14 via the hybrid circuit 12 and an amplifier 13. The mixer 14 mixes the reception signal and a cancel signal output from a cancel signal generation circuit 17 so as to remove undesired signals. In a receiving circuit 15, the signal output from the mixer 14 is sampled by use of a plurality of sample-hold circuits, and subjected to analog sum-of-product computation which is performed by a matrix circuit for distortion compensation. Subsequently, the sampled signals are converted to digital signals. The digital signals are collectively subjected to processing such as parallel-serial conversion, whereby reception data and an evaluation signal are obtained. An adjustment control circuit 18 includes a CPU, and adjusts the respective circuits on the basis of the evaluation signal such that data can be correctly transmitted and received.
摘要翻译：发送电路10将发送数据转换为适合于发送的多级模拟信号。多电平模拟信号经由放大器和混合电路12输出到电缆21.在发送电路10中，产生补偿电缆21的波形恶化的波形。来自电缆21的接收信号经由混合电路12和放大器13输入到混频器14.混频器14混合接收信号和从消除信号发生电路17输出的消除信号，以便去除不想要的信号。在接收电路15中，通过使用多个采样保持电路对从混频器14输出的信号进行采样，并进行由用于失真补偿的矩阵电路执行的模拟和积计算。随后，采样信号被转换成数字信号。数字信号被集体地进行并行串行转换的处理，从而获得接收数据和评估信号。调整控制电路18包括CPU，并且基于评估信号调整各个电路，使得可以正确地发送和接收数据。

10. 发明授权

US06637008B1 Electronic holding circuit and adjusting method thereof using a probabilistic searching technique 失效
标题翻译：电子保持电路及其使用概率搜索技术的调整方法
公开(公告)号：US06637008B1
公开(公告)日：2003-10-21
申请号：US09397636
申请日：1999-09-16
申请人： Tetsuya Higuchi , Masahiro Murakawa , Yuji Kasai , Shogo Kiryu , Toshio Adachi , Shiro Suzuki
发明人： Tetsuya Higuchi , Masahiro Murakawa , Yuji Kasai , Shogo Kiryu , Toshio Adachi , Shiro Suzuki
IPC分类号： G06F1750
CPC分类号： G06N3/126 , H03H7/19 , H03H7/20 , H03H11/0422 , H03H11/1291
摘要： In an electronic circuit being provided with a plurality of circuit elements and performing a specified function, a plurality of specific circuit elements related to a circuit performing the specified function out of the plurality of circuit elements are composed of circuit elements changing their element parameters according to values indicated by control signals. The electronic circuit is provided with a plurality of holding circuits for holding a plurality of control signals to be given to the plurality of specific circuit elements. The values of the plurality of control signals which these holding circuits hold are changed by external or internal apparatuses according to a probabilistic searching technique (for example genetic algorithms or simulated annealing algorithms) so that the function of the electronic circuit satisfies designated specifications.
摘要翻译：在设置有多个电路元件并执行指定功能的电子电路中，与执行多个电路元件中的指定功能的电路相关的多个特定电路元件由电路元件组成，电路元件根据值由控制信号表示。电子电路设有多个保持电路，用于保持多个控制信号给予多个特定电路元件。这些保持电路保持的多个控制信号的值根据概率搜索技术（例如遗传算法或模拟退火算法）由外部或内部装置改变，使得电子电路的功能满足指定的规格。

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