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1. 发明授权

US08098532B2 Non-volatile semiconductor storage device with address search circuit used when writing 有权
标题翻译：写入时使用地址搜索电路的非易失性半导体存储器件
公开(公告)号：US08098532B2
公开(公告)日：2012-01-17
申请号：US12273813
申请日：2008-11-19
申请人： Yuji Komine , Shinya Fujisawa , Yasuhiko Honda , Ryu Hondai , Takamichi Kasai , Takahiro Suzuki
发明人： Yuji Komine , Shinya Fujisawa , Yasuhiko Honda , Ryu Hondai , Takamichi Kasai , Takahiro Suzuki
IPC分类号： G11C7/10
CPC分类号： G11C16/10 , G11C11/5628 , G11C15/046 , G11C16/344 , G11C16/3445 , G11C16/3454 , G11C16/3459
摘要： A non-volatile semiconductor storage device includes a memory cell array having a plurality of non-volatile memory cells, an address search circuit which searches for write object data and outputs an address where the write object data is present, when writing data into the non-volatile memory cells, and a control circuit which exercises control to write the write object data into the non-volatile memory cells in accordance with the address output from the address search circuit.
摘要翻译：非挥发性半导体存储装置包括具有多个非易失性存储单元的存储单元阵列，地址搜索电路，当将数据写入非易失性存储单元时，搜索写入对象数据并输出存在写入对象数据的地址并且控制电路根据从地址搜索电路输出的地址进行控制以将写入目标数据写入非易失性存储单元。

2. 发明申请

US20090129156A1 NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：非挥发性半导体存储器件
公开(公告)号：US20090129156A1
公开(公告)日：2009-05-21
申请号：US12273813
申请日：2008-11-19
申请人： Yuji KOMINE , Shinya Fujisawa , Yasuhiko Honda , Ryu Hondai , Takamichi Kasai , Takahiro Suzuki
发明人： Yuji KOMINE , Shinya Fujisawa , Yasuhiko Honda , Ryu Hondai , Takamichi Kasai , Takahiro Suzuki
IPC分类号： G11C16/06 , G11C11/34 , G11C7/10
CPC分类号： G11C16/10 , G11C11/5628 , G11C15/046 , G11C16/344 , G11C16/3445 , G11C16/3454 , G11C16/3459
摘要： A non-volatile semiconductor storage device includes a memory cell array having a plurality of non-volatile memory cells, an address search circuit which searches for write object data and outputs an address where the write object data is present, when writing data into the non-volatile memory cells, and a control circuit which exercises control to write the write object data into the non-volatile memory cells in accordance with the address output from the address search circuit.
摘要翻译：非易失性半导体存储装置包括具有多个非易失性存储单元的存储单元阵列，地址搜索电路，当将数据写入非易失性存储单元时，搜索写入对象数据并输出存在写入对象数据的地址并且控制电路根据从地址搜索电路输出的地址进行控制以将写入目标数据写入非易失性存储单元。

3. 发明授权

US07791967B2 Semiconductor memory device and method of testing the same 有权
标题翻译：半导体存储器件及其测试方法
公开(公告)号：US07791967B2
公开(公告)日：2010-09-07
申请号：US11837722
申请日：2007-08-13
申请人： Takahiro Suzuki , Shinya Fujisawa , Tokumasa Hara
发明人： Takahiro Suzuki , Shinya Fujisawa , Tokumasa Hara
IPC分类号： G11C29/12
CPC分类号： G11C29/14 , G11C16/04
摘要： A semiconductor memory device includes a semiconductor memory, an auto-operation control circuit which outputs a clock signal, a sync read control circuit which outputs a sync read address in sync with the clock signal, a read control circuit which selects a read address of the semiconductor memory in accordance with an address of the sync read address, a read sense amplifier circuit which outputs a data read signal that is produced by sensing data that is read out of the semiconductor memory in accordance with the read address, and a determination circuit which compares the data read signal with an expectation value.
摘要翻译：半导体存储器件包括半导体存储器，输出时钟信号的自动操作控制电路，与时钟信号同步地输出同步读取地址的同步读取控制电路，选择读取地址的读取控制电路半导体存储器，根据同步读取地址的地址，读出读出放大器电路，其输出通过根据读取的地址感测从半导体存储器读出的数据而产生的数据读取信号;以及确定电路，将数据读取信号与期望值进行比较。

4. 发明申请

US20080282119A1 MEMORY DEVICE AND BUILT IN SELF-TEST METHOD OF THE SAME 审中-公开
标题翻译：存储器件并建立在其自检中的方法
公开(公告)号：US20080282119A1
公开(公告)日：2008-11-13
申请号：US11877188
申请日：2007-10-23
申请人： Takahiro Suzuki , Shinya Fujisawa , Shoichiro Hashimoto , Tokumasa Hara
发明人： Takahiro Suzuki , Shinya Fujisawa , Shoichiro Hashimoto , Tokumasa Hara
IPC分类号： G11C29/12 , G06F11/27
CPC分类号： G11C29/16
摘要： A memory device including, a nonvolatile memory which stores a step item, a parameter start address, and a parameter which has an address corresponding to the parameter start address and defines the step item, and a controller which performs, on the nonvolatile memory, a test step corresponding to the step item defined by the parameter, the controller being formed in the same chip as the nonvolatile memory.
摘要翻译：一种存储装置，包括存储步骤项目的非易失性存储器，参数起始地址和具有与参数起始地址对应的地址并定义步骤项目的参数的参数，以及控制器，其在非易失性存储器上执行测试步骤对应于由参数定义的步骤项目，控制器形成在与非易失性存储器相同的芯片中。

5. 发明授权

US08219744B2 Semiconductor memory device which includes memory cell having charge accumulation layer and control gate 有权
标题翻译：半导体存储器件，其包括具有电荷累积层和控制栅极的存储单元
公开(公告)号：US08219744B2
公开(公告)日：2012-07-10
申请号：US13301969
申请日：2011-11-22
申请人： Takahiro Suzuki , Shinya Fujisawa , Tokumasa Hara , Masuji Nishiyama
发明人： Takahiro Suzuki , Shinya Fujisawa , Tokumasa Hara , Masuji Nishiyama
IPC分类号： G06F12/02
CPC分类号： G11C16/06
摘要： A semiconductor memory device includes a memory cell array, a power source circuit, a sense amplifier, a control circuit, and a processor. The memory cell array includes a nonvolatile memory cell. The power source circuit includes a first register and generates a voltage. The sense amplifier includes a second register, reads from the memory cell and amplifies the read data. The control circuit includes a third register and controls operations of the power source circuit and the sense amplifier. The processor controls the operations of the power source circuit, the sense amplifier and the control circuit by giving an instruction to the first to third registers. The control circuit decodes the instruction received at the third register so as to control the power source circuit and the sense amplifier directly based on a result of decoding.
摘要翻译：半导体存储器件包括存储单元阵列，电源电路，读出放大器，控制电路和处理器。存储单元阵列包括非易失性存储单元。电源电路包括第一寄存器并产生电压。读出放大器包括第二寄存器，从存储器单元读取并放大读取的数据。控制电路包括第三寄存器并控制电源电路和读出放大器的操作。处理器通过给第一至第三寄存器指令来控制电源电路，读出放大器和控制电路的操作。控制电路解码在第三寄存器处接收的指令，以便基于解码结果来直接控制电源电路和读出放大器。

6. 发明申请

US20080181022A1 SEMICONDUCTOR MEMORY DEVICE WITH MEMORY CELL INCLUDING A CHARGE STORAGE LAYER AND A CONTROL GATE AND METHOD OF CONTROLLING THE SAME 有权
标题翻译：具有包含充电储存层的存储器单元的半导体存储器件和控制栅极及其控制方法
公开(公告)号：US20080181022A1
公开(公告)日：2008-07-31
申请号：US12019245
申请日：2008-01-24
申请人： Shinya Fujisawa , Tokumasa Hara , Takahiro Suzuki
发明人： Shinya Fujisawa , Tokumasa Hara , Takahiro Suzuki
IPC分类号： G11C7/22
CPC分类号： G11C7/1045 , G11C7/22 , G11C16/26 , G11C2216/22
摘要： A semiconductor memory device is capable of simultaneously carrying out a first operation and a second operation. The semiconductor memory device includes first and second control circuits, a select control circuit, and a select circuit. The first control circuit controls the first operation according to a first address signal and outputs a read start signal when the reading of the data is started. The second control circuit controls the second operation according to a second address signal and outputs a sequence flag when the first and second addresses coincide with each other. The select control circuit generates a select control signal. The select control signal is asserted if the second operation is carried out. The first control circuit instructs the select circuit to select the sequence flag if the select control signal is asserted or the data if the select control signal is negated.
摘要翻译：半导体存储器件能够同时执行第一操作和第二操作。半导体存储器件包括第一和第二控制电路，选择控制电路和选择电路。第一控制电路根据第一地址信号控制第一操作，并且当数据读取开始时输出读取开始信号。第二控制电路根据第二地址信号控制第二操作，并且当第一和第二地址彼此一致时输出序列标志。选择控制电路产生选择控制信号。如果执行第二操作，则选择控制信号被置位。如果选择控制信号被断言，则第一控制电路指示选择电路选择序列标志，或者如果选择控制信号被否定则指示数据。

7. 发明授权

US08082383B2 Semiconductor memory device which includes memory cell having charge accumulation layer and control gate 有权
标题翻译：半导体存储器件，其包括具有电荷累积层和控制栅极的存储单元
公开(公告)号：US08082383B2
公开(公告)日：2011-12-20
申请号：US12018493
申请日：2008-01-23
申请人： Takahiro Suzuki , Shinya Fujisawa , Tokumasa Hara , Masuji Nishiyama
发明人： Takahiro Suzuki , Shinya Fujisawa , Tokumasa Hara , Masuji Nishiyama
IPC分类号： G06F13/00
CPC分类号： G11C16/06
摘要： A semiconductor memory device includes a memory cell array, a power source circuit, a sense amplifier, a control circuit, and a processor. The memory cell array includes a nonvolatile memory cell. The power source circuit includes a first register and generates a voltage. The sense amplifier includes a second register, reads from the memory cell and amplifies the read data. The control circuit includes a third register and controls operations of the power source circuit and the sense amplifier. The processor controls the operations of the power source circuit, the sense amplifier and the control circuit by giving an instruction to the first to third registers. The control circuit decodes the instruction received at the third register so as to control the power source circuit and the sense amplifier directly based on a result of decoding.
摘要翻译：半导体存储器件包括存储单元阵列，电源电路，读出放大器，控制电路和处理器。存储单元阵列包括非易失性存储单元。电源电路包括第一寄存器并产生电压。读出放大器包括第二寄存器，从存储器单元读取并放大读取的数据。控制电路包括第三寄存器并控制电源电路和读出放大器的操作。处理器通过给第一至第三寄存器指令来控制电源电路，读出放大器和控制电路的操作。控制电路解码在第三寄存器处接收的指令，以便基于解码结果来直接控制电源电路和读出放大器。

8. 发明授权

US07701781B2 Semiconductor memory device with memory cell including a charge storage layer and a control gate and method of controlling the same 有权
标题翻译：具有包括电荷存储层和控制栅的存储单元的半导体存储器件及其控制方法
公开(公告)号：US07701781B2
公开(公告)日：2010-04-20
申请号：US12019245
申请日：2008-01-24
申请人： Shinya Fujisawa , Tokumasa Hara , Takahiro Suzuki
发明人： Shinya Fujisawa , Tokumasa Hara , Takahiro Suzuki
IPC分类号： G11C7/10
CPC分类号： G11C7/1045 , G11C7/22 , G11C16/26 , G11C2216/22
摘要： A semiconductor memory device is capable of simultaneously carrying out a first operation and a second operation. The semiconductor memory device includes first and second control circuits, a select control circuit, and a select circuit. The first control circuit controls the first operation according to a first address signal and outputs a read start signal when the reading of the data is started. The second control circuit controls the second operation according to a second address signal and outputs a sequence flag when the first and second addresses coincide with each other. The select control circuit generates a select control signal. The select control signal is asserted if the second operation is carried out. The first control circuit instructs the select circuit to select the sequence flag if the select control signal is asserted or the data if the select control signal is negated.
摘要翻译：半导体存储器件能够同时执行第一操作和第二操作。半导体存储器件包括第一和第二控制电路，选择控制电路和选择电路。第一控制电路根据第一地址信号控制第一操作，并且当数据读取开始时输出读取开始信号。第二控制电路根据第二地址信号控制第二操作，并且当第一和第二地址彼此一致时输出序列标志。选择控制电路产生选择控制信号。如果执行第二操作，则选择控制信号被置位。如果选择控制信号被断言，则第一控制电路指示选择电路选择序列标志，或者如果选择控制信号被否定则指示数据。

9. 发明授权

US08130545B2 Nonvolatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08130545B2
公开(公告)日：2012-03-06
申请号：US12938435
申请日：2010-11-03
申请人： Yasuhiko Honda , Takahiro Suzuki , Masao Iwamoto , Kiyochika Kinjo
发明人： Yasuhiko Honda , Takahiro Suzuki , Masao Iwamoto , Kiyochika Kinjo
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/10 , G11C11/5628 , G11C29/00
摘要： A nonvolatile semiconductor storage device capable of storing a plurality of bits of data in one memory cell by assigning multivalued data having a higher-order bit selected from one of a pair of data in a first unit and a lower-order bit selected from the other of the pair of data to each threshold voltage of the memory cell, wherein in a first write operation that processes data in the first unit, the logic of one of the higher-order bit and the lower-order bit is fixed, and two pieces of multivalued data that maximize the difference between the threshold voltages are assigned, thereby storing one bit of input data in the one memory cell in a pseudo binary state, and in a second write operation that processes data in a second unit larger than the first unit, a plurality of bits of input data is stored in the one memory cell in a multivalued state, and parity data for error correction in the second unit is stored in the memory cell.
摘要翻译：一种非易失性半导体存储装置，其能够通过分配具有从第一单位中选择的一对数据中的一个中选择的高阶位的多值数据和从另一个存储单元中选择的低位位来存储多个数据位在一个存储单元中所述数据对与所述存储单元的每个阈值电压相关，其中在处理所述第一单元中的数据的第一写入操作中，所述高位和低位中的一个的逻辑被固定，并且两个分配最大化阈值电压之间的差异的多值数据，从而将一位存储单元中的一位输入数据存储在伪二进制状态，并且在第二写入操作中处理大于第一单元的第二单元中的数据输入数据的多个位以多值状态存储在一个存储单元中，第二单元中用于纠错的奇偶校验数据被存储在存储单元中。

10. 发明授权

US07843728B2 Nonvolatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US07843728B2
公开(公告)日：2010-11-30
申请号：US12272161
申请日：2008-11-17
申请人： Yasuhiko Honda , Takahiro Suzuki , Masao Iwamoto , Kiyochika Kinjo
发明人： Yasuhiko Honda , Takahiro Suzuki , Masao Iwamoto , Kiyochika Kinjo
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C11/5628 , G11C29/00
摘要： A nonvolatile semiconductor storage device capable of storing a plurality of bits of data in one memory cell by assigning multivalued data having a higher-order bit selected from one of a pair of data in a first unit and a lower-order bit selected from the other of the pair of data to each threshold voltage of the memory cell, wherein in a first write operation that processes data in the first unit, the logic of one of the higher-order bit and the lower-order bit is fixed, and two pieces of multivalued data that maximize the difference between the threshold voltages are assigned, thereby storing one bit of input data in the one memory cell in a pseudo binary state, and in a second write operation that processes data in a second unit larger than the first unit, a plurality of bits of input data is stored in the one memory cell in a multivalued state, and parity data for error correction in the second unit is stored in the memory cell.
摘要翻译：一种非易失性半导体存储装置，其能够通过分配具有从第一单位中选择的一对数据中的一个中选择的高阶位的多值数据和从另一个存储单元中选择的低位位来存储多个数据位在一个存储单元中所述数据对与所述存储单元的每个阈值电压相关，其中在处理所述第一单元中的数据的第一写入操作中，所述高位和低位中的一个的逻辑被固定，并且两个分配最大化阈值电压之间的差异的多值数据，从而将一位存储单元中的一位输入数据存储在伪二进制状态，并且在第二写入操作中处理大于第一单元的第二单元中的数据输入数据的多个位以多值状态存储在一个存储单元中，第二单元中用于纠错的奇偶校验数据被存储在存储单元中。

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