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1. 发明申请

US20130026995A1 BATTERY PROTECTION IC AND BATTERY DEVICE 有权
标题翻译：电池保护IC和电池装置
公开(公告)号：US20130026995A1
公开(公告)日：2013-01-31
申请号：US13553174
申请日：2012-07-19
申请人： Yuichiro Kitajima , Naoto Kobayashi
发明人： Yuichiro Kitajima , Naoto Kobayashi
IPC分类号： H02J7/00
CPC分类号： H02J7/0029 , H01M2/342 , H01M10/425 , H01M10/46 , H01M10/48 , H02J7/0034 , H02J2007/0037 , H02J2007/0039 , H02J2007/004
摘要： Provided are a battery protection IC and a battery device, which are capable of ensuring safety even when a charger is connected in a reverse direction. The battery protection IC includes a first switch element provided between an overcurrent detection terminal and a VDD terminal so that, when the charger is connected with reverse polarity, the first switch element interrupts a current path between the overcurrent detection terminal and the VDD terminal. The battery protection IC further includes a second switch element provided between a charge control terminal and the VDD terminal so that, when the charger is connected with reverse polarity, the second switch element interrupts a current path between the charge control terminal and the VDD terminal.
摘要翻译：提供一种电池保护IC和电池装置，其即使在逆向连接充电器时也能够确保安全性。电池保护IC包括设置在过电流检测端子和VDD端子之间的第一开关元件，使得当充电器以相反的极性连接时，第一开关元件中断过电流检测端子和VDD端子之间的电流路径。电池保护IC还包括设置在充电控制端子和VDD端子之间的第二开关元件，使得当充电器以相反极性连接时，第二开关元件中断充电控制端子和VDD端子之间的电流路径。

2. 发明授权

US09142983B2 Battery protection IC and battery device 有权
标题翻译：电池保护IC和电池装置
公开(公告)号：US09142983B2
公开(公告)日：2015-09-22
申请号：US13553174
申请日：2012-07-19
申请人： Yuichiro Kitajima , Naoto Kobayashi
发明人： Yuichiro Kitajima , Naoto Kobayashi
IPC分类号： H01M2/34 , H02J7/00 , H01M10/42 , H01M10/48 , H01M10/46
CPC分类号： H02J7/0029 , H01M2/342 , H01M10/425 , H01M10/46 , H01M10/48 , H02J7/0034 , H02J2007/0037 , H02J2007/0039 , H02J2007/004
摘要： Provided are a battery protection IC and a battery device, which are capable of ensuring safety even when a charger is connected in a reverse direction. The battery protection IC includes a first switch element provided between an overcurrent detection terminal and a VDD terminal so that, when the charger is connected with reverse polarity, the first switch element interrupts a current path between the overcurrent detection terminal and the VDD terminal. The battery protection IC further includes a second switch element provided between a charge control terminal and the VDD terminal so that, when the charger is connected with reverse polarity, the second switch element interrupts a current path between the charge control terminal and the VDD terminal.
摘要翻译：提供一种电池保护IC和电池装置，其即使在逆向连接充电器时也能够确保安全性。电池保护IC包括设置在过电流检测端子和VDD端子之间的第一开关元件，使得当充电器以相反的极性连接时，第一开关元件中断过电流检测端子和VDD端子之间的电流路径。电池保护IC还包括设置在充电控制端子和VDD端子之间的第二开关元件，使得当充电器以相反极性连接时，第二开关元件中断充电控制端子和VDD端子之间的电流路径。

3. 发明授权

US07888212B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07888212B2
公开(公告)日：2011-02-15
申请号：US12392450
申请日：2009-02-25
申请人： Tomomitsu Risaki , Yuichiro Kitajima
发明人： Tomomitsu Risaki , Yuichiro Kitajima
IPC分类号： H01L21/336
CPC分类号： H01L29/66659 , H01L29/1037 , H01L29/4236 , H01L29/42376 , H01L29/66787 , H01L29/66795 , H01L29/7834 , H01L29/7835
摘要： In a well region, an irregular structure is formed in a gate width direction, and a gate electrode is formed in concave portions and on top surfaces of convex portions via an insulating film. Upper and lower source regions are formed on one side of the gate electrode in a gate length direction, and upper and lower drain regions are formed on the other side thereof. By thus forming the lower source and drain regions in the source and drain regions, current concentration occurring in an upper portion of a channel region, which is generated as the gate length becomes shorter, may be suppressed and a current may be allowed to flow uniformly in the entire channel region, and hence an effective gate width is made wider owing to the irregular structure formed in the well region. Accordingly, an on-resistance of a semiconductor device is reduced to enhance driving performance.
摘要翻译：在阱区域中，在栅极宽度方向上形成不规则结构，并且通过绝缘膜在凹部和凸部的上表面上形成栅电极。在栅极长度方向的一侧形成上下源极区，在另一侧形成上下漏极区。因此，通过在源极和漏极区域形成下部源极和漏极区域，可以抑制在栅极长度变短时产生的沟道区域的上部产生的电流集中，并且可以使电流均匀地流动在整个沟道区域中，由于在阱区域中形成不规则结构，因此使有效栅极宽度变宽。因此，减小了半导体器件的导通电阻以提高驱动性能。

4. 发明授权

US07575967B2 Semiconductor integrated circuit device and a manufacturing method for the same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US07575967B2
公开(公告)日：2009-08-18
申请号：US11582911
申请日：2006-10-18
申请人： Naoto Saitoh , Yuichiro Kitajima
发明人： Naoto Saitoh , Yuichiro Kitajima
IPC分类号： H01L29/72
CPC分类号： H01L29/405 , H01L29/402 , H01L29/41725 , H01L29/41775 , H01L29/4983 , H01L29/7834 , H01L29/7835
摘要： In a manufacturing method for a semiconductor device, a first impurity diffusion layer for a low impurity concentration drain of a second conductivity type is formed within a semiconductor layer of a first conductivity type, and a second impurity diffusion layer for a high impurity concentration drain of the second conductivity type is formed adjacent to the first impurity diffusion layer, with the second impurity diffusion layer having a higher impurity concentration than the first impurity diffusion layer. An interlayer insulating film is formed on the semiconductor substrate layer. A drain extension region having a high thermal conductivity is formed on a surface of the first impurity diffusion layer. A contact hole is formed through the interlayer insulating film and up to the second impurity diffusion layer. A wiring metal layer is then deposited into the contact hole to form therein a drain electrode that is electrically connected to the second impurity diffusion layer and that is disposed apart from and not in contact with the drain extension region.
摘要翻译：在半导体装置的制造方法中，在第一导电型的半导体层内形成第二导电型的低杂质浓度漏极的第一杂质扩散层，以及用于高杂质浓度漏极的第二杂质扩散层形成与第一杂质扩散层相邻的第二导电型，第二杂质扩散层的杂质浓度比第一杂质扩散层高。在半导体衬底层上形成层间绝缘膜。在第一杂质扩散层的表面上形成具有高导热性的漏极延伸区域。形成穿过层间绝缘膜和直到第二杂质扩散层的接触孔。然后将布线金属层沉积到接触孔中以在其中形成漏电极，该漏极电连接到第二杂质扩散层，并且被设置为与漏极延伸区域分开并且不与漏极延伸区域接触。

5. 发明申请

US20070200200A1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070200200A1
公开(公告)日：2007-08-30
申请号：US11705678
申请日：2007-02-13
申请人： Yuichiro Kitajima
发明人： Yuichiro Kitajima
IPC分类号： H01L29/00
CPC分类号： H01L28/20
摘要： Provided are a semiconductor device including a highly precise resistor formed of a polycrystalline silicon film and a method of manufacturing the same, in which: a portion of a base insulating film below a portion of the polycrystalline silicon film which becomes a resistance region into a convex shape; and the polycrystalline silicon film which becomes the resistor is selectively formed into a thin film, while an electrode lead-out region remains thick so as to obtain the resistor with high precision, high resistivity, and a preferable temperature coefficient while preventing penetration in an opening for contact.
摘要翻译：提供一种半导体器件，其包括由多晶硅膜形成的高精度电阻器及其制造方法，其中：在多晶硅膜的部分下方的基极绝缘膜的一部分变成为凸状形状; 并且成为电阻器的多晶硅膜选择性地形成为薄膜，同时电极引出区域保持较厚，从而获得高精度，高电阻率和优选的温度系数的电阻器，同时防止在开口中的穿透联系。

6. 发明申请

US20110227192A1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20110227192A1
公开(公告)日：2011-09-22
申请号：US13134039
申请日：2011-05-26
申请人： Yuichiro Kitajima
发明人： Yuichiro Kitajima
IPC分类号： H01L27/06 , H01L29/86
CPC分类号： H01L28/20
摘要： Provided are a semiconductor device including a highly precise resistor formed of a polycrystalline silicon film and a method of manufacturing the same, in which: a portion of a base insulating film below a portion of the polycrystalline silicon film which becomes a resistance region into a convex shape; and the polycrystalline silicon film which becomes the resistor is selectively formed into a thin film, while an electrode lead-out region remains thick so as to obtain the resistor with high precision, high resistivity, and a preferable temperature coefficient while preventing penetration in an opening for contact.
摘要翻译：提供一种半导体器件，其包括由多晶硅膜形成的高精度电阻器及其制造方法，其中：在多晶硅膜的部分下方的基极绝缘膜的一部分变成为凸状形状; 并且成为电阻器的多晶硅膜选择性地形成为薄膜，同时电极引出区域保持较厚，从而获得高精度，高电阻率和优选的温度系数的电阻器，同时防止在开口中的穿透联系。

7. 发明授权

US07847370B2 Semiconductor device with resistor and fuse and method of manufacturing the same 有权
标题翻译：具有电阻和保险丝的半导体器件及其制造方法
公开(公告)号：US07847370B2
公开(公告)日：2010-12-07
申请号：US12027620
申请日：2008-02-07
申请人： Yuichiro Kitajima
发明人： Yuichiro Kitajima
IPC分类号： H01L29/00
CPC分类号： H01L28/20
摘要： A fuse element is laminated on a resistor and the resistor is formed in a concave shape below a region in which cutting of the fuse element is carried out with a laser. Accordingly, there can be provided a semiconductor device which occupies a small area, causes no damage on the resistor in the cutting of the fuse element, has a small contact resistance occurred between elements, and has stable characteristics, and a method of manufacturing the same.
摘要翻译：熔丝元件层压在电阻器上，电阻器形成为在激光器上进行熔丝元件切割的区域下的凹形形状。因此，可以提供占用小面积的半导体器件，在熔丝元件的切割中不会对电阻器造成损坏，元件之间发生小的接触电阻，并且具有稳定的特性，及其制造方法。

8. 发明申请

US20070085137A1 Semiconductor integrated circuit device and a manufacturing method for the same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US20070085137A1
公开(公告)日：2007-04-19
申请号：US11582911
申请日：2006-10-18
申请人： Naoto Saitoh , Yuichiro Kitajima
发明人： Naoto Saitoh , Yuichiro Kitajima
IPC分类号： H01L29/76
CPC分类号： H01L29/405 , H01L29/402 , H01L29/41725 , H01L29/41775 , H01L29/4983 , H01L29/7834 , H01L29/7835
摘要： Provided is a manufacturing method for a power management semiconductor device or an analog semiconductor device both including a CMOS. According to the method, a substance having high thermal conductivity is additionally provided above a semiconductor region constituting a low impurity concentration drain region so as to expand the drain region, which contributes to a promotion of thermal conductivity (or thermal emission) in the drain region during a surge input and leads to suppression of local temperature increase, to thereby prevent thermal destruction. Therefore, it is possible to manufacture a power management semiconductor device or an analog semiconductor device with the extended possibility of transistor design.
摘要翻译：提供了一种用于包括CMOS的功率管理半导体器件或模拟半导体器件的制造方法。根据该方法，在构成低杂质浓度漏极区域的半导体区域的上方附加设置具有高导热性的物质，以扩大漏极区域，有助于提高漏极区域（或发热）并且导致局部温度升高的抑制，从而防止热破坏。因此，可以制造具有扩大晶体管设计可能性的功率管理半导体器件或模拟半导体器件。

9. 发明授权

US07043328B2 Method for manufacturing semiconductor device utilizing monitor wafers 有权
标题翻译：利用监视晶片制造半导体器件的方法
公开(公告)号：US07043328B2
公开(公告)日：2006-05-09
申请号：US10936736
申请日：2004-09-08
申请人： Kazutoshi Ishii , Jun Osanai , Yuichiro Kitajima , Yukimasa Minami , Keisuke Uemura , Miwa Wake
发明人： Kazutoshi Ishii , Jun Osanai , Yuichiro Kitajima , Yukimasa Minami , Keisuke Uemura , Miwa Wake
IPC分类号： G06F19/00
CPC分类号： H01L22/12 , H01L22/14 , H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： A manufacturing method for a semiconductor device which is capable of manufacturing the semiconductor device with a high quality in high yields while reducing variations in electric characteristic is disclosed. The manufacturing method according to the present invention includes a main body wafer manufacturing process for manufacturing a wafer on which a semiconductor device to be completed as a product is formed and a monitor wafer manufacturing process for manufacturing a wafer on which a monitor element is formed, the processes sharing a monitoring step alone, the main body wafer manufacturing process including a variation reduction step, the monitor wafer manufacturing process including a quality check step and a condition setting step.
摘要翻译：公开了一种半导体器件的制造方法，该半导体器件能够以降低电特性的变化的方式高产量地制造高质量的半导体器件。根据本发明的制造方法包括用于制造其上形成作为产品而要完成的半导体器件的晶片的主体晶片制造工艺和用于制造其上形成有监视元件的晶片的监视晶片制造工艺，所述处理单独共享监视步骤，所述主体晶片制造工艺包括变化减小步骤，所述监视晶片制造过程包括质量检查步骤和条件设置步骤。

10. 发明申请

US20050130332A1 Method for manufacturing semiconductor device 有权
公开(公告)号：US20050130332A1
公开(公告)日：2005-06-16
申请号：US10936737
申请日：2004-09-08
申请人： Kazutoshi Ishii , Jun Osanai , Yuichiro Kitajima , Yukimasa Minami , Keisuke Uemura , Miwa Wake
发明人： Kazutoshi Ishii , Jun Osanai , Yuichiro Kitajima , Yukimasa Minami , Keisuke Uemura , Miwa Wake
IPC分类号： H01L21/66 , G01R31/26 , H01L21/00 , H01L21/02
CPC分类号： H01L22/14 , H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： A manufacturing method for a semiconductor device which is capable of manufacturing the semiconductor device with a high quality in high yields while reducing variations in electric characteristic is disclosed. The manufacturing method according to the present invention includes a main body wafer manufacturing process for manufacturing a wafer on which a semiconductor device to be completed as a product is formed and a monitor wafer manufacturing process for manufacturing a wafer on which a monitor element is formed, the processes sharing a monitoring step alone, the main body wafer manufacturing process including a variation reduction step, the monitor wafer manufacturing process including a quality check step and a condition setting step.

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