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1. 发明申请

US20100176517A1 Electronic device 审中-公开
标题翻译：电子设备
公开(公告)号：US20100176517A1
公开(公告)日：2010-07-15
申请号：US12654834
申请日：2010-01-06
申请人： Yuichi Miyagawa , Jun Tsukano , Kenji Furuya , Takamitsu Noda , Hiroyasu Miyamoto
发明人： Yuichi Miyagawa , Jun Tsukano , Kenji Furuya , Takamitsu Noda , Hiroyasu Miyamoto
IPC分类号： H01L23/28
CPC分类号： H01L23/3121 , B29C45/02 , B29C45/1671 , H01L21/565 , H01L23/3185 , H01L24/48 , H01L24/49 , H01L25/0655 , H01L25/0657 , H01L2224/48091 , H01L2224/48227 , H01L2224/49171 , H01L2225/0651 , H01L2924/00014 , H01L2924/181 , H01L2924/1815 , H05K3/284 , H05K2201/0187 , H05K2201/09972 , H05K2203/1316 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Differences in contraction forces of a sealing resin can be alleviated and strain on a package can be reduced even when electronic components are unevenly positioned on a substrate. An electronic device (100) includes a substrate 102, electronic components (104, 108) mounted on one face of the substrate 102, and a sealing resin 118 formed on the one face of the substrate 102 and which seals the electronic components. The sealing resin 118 includes a first resin region 120 made up of a first resin composition and a second resin region 122 made up of a second resin composition, and is formed so as to have, as seen in planar view, a region in which only the first resin region 120 exists and a region in which only the second resin region 122 exists.
摘要翻译：密封树脂的收缩力的差异可以减轻，即使当电子部件不均匀地定位在基板上时，也可以减小包装上的应变。电子设备（100）包括衬底102，安装在衬底102的一个面上的电子部件（104,108）以及形成在衬底102的一个面上并密封电子部件的密封树脂118。密封树脂118包括由第一树脂组合物构成的第一树脂区域120和由第二树脂组合物构成的第二树脂区域122，并且形成为具有如平面图所示的区域，其中仅仅存在第一树脂区域120和仅存在第二树脂区域122的区域。

2. 发明申请

US20100102461A1 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20100102461A1
公开(公告)日：2010-04-29
申请号：US12588643
申请日：2009-10-22
申请人： Yuichi Miyagawa , Takamitsu Noda , Hiroyasu Miyamoto , Jun Tsukano
发明人： Yuichi Miyagawa , Takamitsu Noda , Hiroyasu Miyamoto , Jun Tsukano
IPC分类号： H01L23/28 , H01L21/56
CPC分类号： H01L23/3135 , H01L23/3121 , H01L23/562 , H01L25/0655 , H01L2224/48091 , H01L2224/48227 , H01L2224/49171 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor device including a substrate, a semiconductor chip mounted on the substrate, and an encapsulation resin encapsulating the semiconductor chip, wherein the encapsulation resin contains a first resin region composed of a first resin composition, a second resin region composed of a second resin composition, and a mixed layer formed between the first resin region and the second resin region so as to have the first resin composition and the second resin composition mixed therein is provided.
摘要翻译：一种半导体器件，包括衬底，安装在衬底上的半导体芯片和封装半导体芯片的封装树脂，其中封装树脂包含由第一树脂组合物构成的第一树脂区域，由第二树脂组合物构成的第二树脂区域并且设置在第一树脂区域和第二树脂区域之间形成的混合层以使第一树脂组合物和第二树脂组合物混合在一起。

3. 发明授权

US07888809B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07888809B2
公开(公告)日：2011-02-15
申请号：US12588643
申请日：2009-10-22
申请人： Yuichi Miyagawa , Takamitsu Noda , Hiroyasu Miyamoto , Jun Tsukano
发明人： Yuichi Miyagawa , Takamitsu Noda , Hiroyasu Miyamoto , Jun Tsukano
IPC分类号： H01L23/29
CPC分类号： H01L23/3135 , H01L23/3121 , H01L23/562 , H01L25/0655 , H01L2224/48091 , H01L2224/48227 , H01L2224/49171 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor device including a substrate, a semiconductor chip mounted on the substrate, and an encapsulation resin encapsulating the semiconductor chip, wherein the encapsulation resin contains a first resin region composed of a first resin composition, a second resin region composed of a second resin composition, and a mixed layer formed between the first resin region and the second resin region so as to have the first resin composition and the second resin composition mixed therein is provided.
摘要翻译：一种半导体器件，包括衬底，安装在衬底上的半导体芯片和封装半导体芯片的封装树脂，其中所述封装树脂包含由第一树脂组合物构成的第一树脂区域，由第二树脂组合物构成的第二树脂区域并且设置在第一树脂区域和第二树脂区域之间形成的混合层以使第一树脂组合物和第二树脂组合物混合在一起。

4. 发明申请

US20090227088A1 SEMICONDUCTOR WAFER AND MANUFACTURING PROCESS FOR SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件的半导体晶体管和制造工艺
公开(公告)号：US20090227088A1
公开(公告)日：2009-09-10
申请号：US12465349
申请日：2009-05-13
申请人： Tsuyoshi KIDA , Takamitsu Noda
发明人： Tsuyoshi KIDA , Takamitsu Noda
IPC分类号： H01L21/78 , H01L23/544
CPC分类号： H01L21/78 , H01L22/34 , H01L23/544 , H01L2223/54453 , H01L2223/5446 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor wafer 1 has first scribe lines 31 in two mutually perpendicular directions which have a first width and divide the semiconductor wafer 1 into a plurality of areas; second scribe lines 32 which have a second width smaller than the first width and divide the area into a plurality of semiconductor chip areas 2; an electrode pad 5 formed along the edge of the semiconductor chip area 2; and a metal-containing accessory pattern 4 disposed in the scribe lines. In the second scribe lines 32, the accessory pattern 4 is absent in at least the outermost surface in an area adjacent to the edge having the electrode pad 5 in the chip area 2.
摘要翻译：半导体晶片1具有第一切割线31，其具有第一宽度，并且将半导体晶片1分割成多个区域; 第二划痕线32具有小于第一宽度的第二宽度，并将该区域划分成多个半导体芯片区域2; 沿着半导体芯片区域2的边缘形成的电极焊盘5; 以及设置在划线中的含金属的附件图案4。在第二划片线32中，在与芯片区域2中具有电极焊盘5的边缘相邻的区域中的至少最外表面中不存在附件图案4。

5. 发明申请

US20050282360A1 Semiconductor wafer and manufacturing process for semiconductor device 有权
标题翻译：半导体晶圆及半导体器件制造工艺
公开(公告)号：US20050282360A1
公开(公告)日：2005-12-22
申请号：US11152092
申请日：2005-06-15
申请人： Tsuyoshi Kida , Takamitsu Noda
发明人： Tsuyoshi Kida , Takamitsu Noda
IPC分类号： H01L21/301 , H01L21/46 , H01L21/78 , H01L23/544
CPC分类号： H01L21/78 , H01L22/34 , H01L23/544 , H01L2223/54453 , H01L2223/5446 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor wafer 1 has first scribe lines 31 in two mutually perpendicular directions which have a first width and divide the semiconductor wafer 1 into a plurality of areas; second scribe lines 32 which have a second width smaller than the first width and divide the area into a plurality of semiconductor chip areas 2; an electrode pad 5 formed along the edge of the semiconductor chip area 2; and a metal-containing accessory pattern 4 disposed in the scribe lines. In the second scribe lines 32, the accessory pattern 4 is absent in at least the outermost surface in an area adjacent to the edge having the electrode pad 5 in the chip area 2.
摘要翻译：半导体晶片1具有第一切割线31，其具有第一宽度，并且将半导体晶片1分割成多个区域; 第二划痕线32具有小于第一宽度的第二宽度，并将该区域划分成多个半导体芯片区域2; 沿着半导体芯片区域2的边缘形成的电极焊盘5; 以及设置在划线中的含金属的附件图案4。在第二划片线32中，在与芯片区域2中具有电极焊盘5的边缘相邻的区域中的至少最外表面中不存在附件图案4。

6. 发明授权

US07759223B2 Semiconductor wafer and manufacturing process for semiconductor device 有权
标题翻译：半导体晶圆及半导体器件制造工艺
公开(公告)号：US07759223B2
公开(公告)日：2010-07-20
申请号：US12465349
申请日：2009-05-13
申请人： Tsuyoshi Kida , Takamitsu Noda
发明人： Tsuyoshi Kida , Takamitsu Noda
IPC分类号： H01L21/00
CPC分类号： H01L21/78 , H01L22/34 , H01L23/544 , H01L2223/54453 , H01L2223/5446 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor wafer 1 has first scribe lines 31 in two mutually perpendicular directions which have a first width and divide the semiconductor wafer 1 into a plurality of areas; second scribe lines 32 which have a second width smaller than the first width and divide the area into a plurality of semiconductor chip areas 2; an electrode pad 5 formed along the edge of the semiconductor chip area 2; and a metal-containing accessory pattern 4 disposed in the scribe lines. In the second scribe lines 32, the accessory pattern 4 is absent in at least the outermost surface in an area adjacent to the edge having the electrode pad 5 in the chip area 2.
摘要翻译：半导体晶片1具有第一切割线31，其具有第一宽度，并且将半导体晶片1分割成多个区域; 第二划痕线32具有小于第一宽度的第二宽度，并将该区域划分成多个半导体芯片区域2; 沿着半导体芯片区域2的边缘形成的电极焊盘5; 以及设置在划线中的含金属的附件图案4。在第二划片线32中，在与芯片区域2中具有电极焊盘5的边缘相邻的区域中的至少最外表面中不存在附件图案4。

7. 发明授权

US08053337B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08053337B2
公开(公告)日：2011-11-08
申请号：US12659991
申请日：2010-03-26
申请人： Takamitsu Noda
发明人： Takamitsu Noda
IPC分类号： H01L21/78
CPC分类号： H01L21/78 , B23K26/364 , B23K26/40 , B23K2103/172 , B23K2103/42 , B23K2103/50 , Y10S438/976
摘要： In a method of manufacturing a semiconductor device, a first groove and a second groove each having a width less than that of a scribe line are formed along the scribe line in a first protective film provided below a second protective film which protects element forming regions when a wafer is divided into parts by a laser dicing, and the first groove and the second groove are filled with the second protective film. Then, the laser dicing is performed on a region between the first groove and the second groove along the scribe line from the surface where the second protective film is formed to form a cutting groove that reaches at least a predetermined depth of the multi-layer interconnect.
摘要翻译：在制造半导体器件的方法中，沿着划线沿着划线形成第一保护膜，第一保护膜设置在保护元件形成区域的第二保护膜下方的第一保护膜中，第一保护膜和第二槽的宽度小于划线的宽度，通过激光切割将晶片分成多个部分，并且第一凹槽和第二凹槽被第二保护膜填充。然后，从形成第二保护膜的表面沿着划线在第一槽和第二槽之间的区域上进行激光切割，以形成至少达到多层互连的预定深度的切割槽。

8. 发明申请

US20100273312A1 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20100273312A1
公开(公告)日：2010-10-28
申请号：US12659991
申请日：2010-03-26
申请人： Takamitsu Noda
发明人： Takamitsu Noda
IPC分类号： H01L21/78
CPC分类号： H01L21/78 , B23K26/364 , B23K26/40 , B23K2103/172 , B23K2103/42 , B23K2103/50 , Y10S438/976
摘要： In a method of manufacturing a semiconductor device, a first groove and a second groove each having a width less than that of a scribe line are formed along the scribe line in a first protective film provided below a second protective film which protects element forming regions when a wafer is divided into parts by a laser dicing, and the first groove and the second groove are filled with the second protective film. Then, the laser dicing is performed on a region between the first groove and the second groove along the scribe line from the surface where the second protective film is formed to form a cutting groove that reaches at least a predetermined depth of the multi-layer interconnect.
摘要翻译：在制造半导体器件的方法中，沿着划线沿着划线形成第一保护膜，第一保护膜设置在保护元件形成区域的第二保护膜下方的第一保护膜中，第一保护膜和第二槽的宽度小于划线的宽度，通过激光切割将晶片分成多个部分，并且第一凹槽和第二凹槽被第二保护膜填充。然后，从形成第二保护膜的表面沿着划线在第一槽和第二槽之间的区域上进行激光切割，以形成至少达到多层互连的预定深度的切割槽。

9. 发明授权

US07554211B2 Semiconductor wafer and manufacturing process for semiconductor device 有权
标题翻译：半导体晶圆及半导体器件制造工艺
公开(公告)号：US07554211B2
公开(公告)日：2009-06-30
申请号：US11152092
申请日：2005-06-15
申请人： Tsuyoshi Kida , Takamitsu Noda
发明人： Tsuyoshi Kida , Takamitsu Noda
IPC分类号： H01L23/544
CPC分类号： H01L21/78 , H01L22/34 , H01L23/544 , H01L2223/54453 , H01L2223/5446 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor wafer 1 has first scribe lines 31 in two mutually perpendicular directions which have a first width and divide the semiconductor wafer 1 into a plurality of areas; second scribe lines 32 which have a second width smaller than the first width and divide the area into a plurality of semiconductor chip areas 2; an electrode pad 5 formed along the edge of the semiconductor chip area 2; and a metal-containing accessory pattern 4 disposed in the scribe lines. In the second scribe lines 32, the accessory pattern 4 is absent in at least the outermost surface in an area adjacent to the edge having the electrode pad 5 in the chip area 2.
摘要翻译：半导体晶片1具有第一切割线31，其具有第一宽度，并且将半导体晶片1分割成多个区域; 第二划痕线32具有小于第一宽度的第二宽度，并将该区域划分成多个半导体芯片区域2; 沿着半导体芯片区域2的边缘形成的电极焊盘5; 以及设置在划线中的含金属的附件图案4。在第二划片线32中，在与芯片区域2中具有电极焊盘5的边缘相邻的区域中的至少最外表面中不存在附件图案4。

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