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1. 发明申请

US20080044984A1 METHODS OF AVOIDING WAFER BREAKAGE DURING MANUFACTURE OF BACKSIDE ILLUMINATED IMAGE SENSORS 审中-公开
标题翻译：在背光照明图像传感器制造过程中避免浪涌破裂的方法
公开(公告)号：US20080044984A1
公开(公告)日：2008-02-21
申请号：US11465047
申请日：2006-08-16
申请人： Yuan-Chih Hsieh , Chung-Yi Yu , Gwo-Yuh Shiau , Shih-Chi Fu , Ming Chyi Liu , Chia-Shiung Tsai
发明人： Yuan-Chih Hsieh , Chung-Yi Yu , Gwo-Yuh Shiau , Shih-Chi Fu , Ming Chyi Liu , Chia-Shiung Tsai
IPC分类号： H01L21/30 , H01L21/46
CPC分类号： H01L21/304 , H01L27/14618 , H01L27/14687 , H01L2924/0002 , H01L2924/00
摘要： A process for forming backside illuminated devices is disclosed. Specifically, the process reduces processing damage to wafers caused by poor bond quality at the wafer edge ring. In one embodiment, a wafer edge trimming step is implemented prior to bonding the wafer to the substrate. A pre-grind blade is used to create a straight edge around the wafer perimeter, eliminating any sharp edges. In another embodiment, edge trimming is performed after the wafer has been bonded to the substrate, and a pre-grind blade is used to remove portion of the wafer edge ring subject to poor bonding quality before grinding. The final thickness of the ground wafer is about 50 microns in either case.
摘要翻译：公开了一种用于形成背面照明装置的工艺。具体地说，该方法减少了由于晶片边缘环上的接合质量差而导致的对晶片的加工损坏。在一个实施例中，在将晶片接合到基板之前实现晶片边缘修剪步骤。预磨刀片用于在晶片周边周围创建直边，消除任何尖锐边缘。在另一个实施例中，在晶片已经结合到基板之后进行边缘修整，并且在研磨之前使用预研磨刀片来去除在接合质量差的条件下的部分晶片边缘环。在任一情况下，接地晶片的最终厚度为约50微米。

2. 发明授权

US08710560B2 Embedded bonding pad for image sensors 有权
标题翻译：用于图像传感器的嵌入式焊盘
公开(公告)号：US08710560B2
公开(公告)日：2014-04-29
申请号：US11835814
申请日：2007-08-08
申请人： Yuan-Chih Hsieh , Shih-Chang Liu , Shih-Chi Fu , Tzu-Hsuan Hsu , Chung-Yi Yu , Gwo-Yuh Shiau , Chia-Shiung Tsai
发明人： Yuan-Chih Hsieh , Shih-Chang Liu , Shih-Chi Fu , Tzu-Hsuan Hsu , Chung-Yi Yu , Gwo-Yuh Shiau , Chia-Shiung Tsai
IPC分类号： H01L31/062
CPC分类号： H01L27/14643 , H01L24/05 , H01L27/14636 , H01L2224/05556 , H01L2924/12043 , H01L2924/00
摘要： A semiconductor device includes a semiconductor substrate having a front surface and a back surface, elements formed on the substrate, interconnect metal layers formed over the front surface of the substrate, including a topmost interconnect metal layer, an inter-metal dielectric for insulating each of the plurality of interconnect metal layers, and a bonding pad disposed within the inter-metal dielectric, the bonding pad in contact with one of the interconnect metal layers other than the topmost interconnect metal layer.
摘要翻译：半导体器件包括具有前表面和后表面的半导体衬底，形成在衬底上的元件，形成在衬底的前表面上的互连金属层，包括最上面的互连金属层，用于绝缘的金属间电介质所述多个互连金属层和设置在所述金属间电介质内的接合焊盘，所述接合焊盘与所述互连金属层中的一个互连金属层之外的最上面的互连金属层接触。

3. 发明申请

US20090039452A1 EMBEDDED BONDING PAD FOR IMAGE SENSORS 有权
标题翻译：用于图像传感器的嵌入式接合垫
公开(公告)号：US20090039452A1
公开(公告)日：2009-02-12
申请号：US11835814
申请日：2007-08-08
申请人： Yuan-Chih Hsieh , Shih-Chang Liu , Shih-Chi Fu , Tzu-Hsuan Hsu , Chung-Yi Yu , Gwo-Yuh Shiau , Chia-Shiung Tsai
发明人： Yuan-Chih Hsieh , Shih-Chang Liu , Shih-Chi Fu , Tzu-Hsuan Hsu , Chung-Yi Yu , Gwo-Yuh Shiau , Chia-Shiung Tsai
IPC分类号： H01L31/00
CPC分类号： H01L27/14643 , H01L24/05 , H01L27/14636 , H01L2224/05556 , H01L2924/12043 , H01L2924/00
摘要： A semiconductor device includes a semiconductor substrate having a front surface and a back surface, elements formed on the substrate, interconnect metal layers formed over the front surface of the substrate, including a topmost interconnect metal layer, an inter-metal dielectric for insulating each of the plurality of interconnect metal layers, and a bonding pad disposed within the inter-metal dielectric, the bonding pad in contact with one of the interconnect metal layers other than the topmost interconnect metal layer.
摘要翻译：半导体器件包括具有前表面和后表面的半导体衬底，形成在衬底上的元件，形成在衬底的前表面上的互连金属层，包括最上面的互连金属层，用于绝缘的金属间电介质所述多个互连金属层和设置在所述金属间电介质内的接合焊盘，所述接合焊盘与所述互连金属层中的一个互连金属层之外的最上面的互连金属层接触。

4. 发明授权

US08629531B2 Structure and method to reduce wafer warp for gallium nitride on silicon wafer 有权
标题翻译：减少硅晶片上氮化镓晶片翘曲的结构和方法
公开(公告)号：US08629531B2
公开(公告)日：2014-01-14
申请号：US13030645
申请日：2011-02-18
申请人： Ming Chyi Liu , Hsieh Ching Pei , Jiun-Lei Yu , Chi-Ming Chen , Shih-Chang Liu , Chung-Yi Yu , Chia-Shiung Tsai
发明人： Ming Chyi Liu , Hsieh Ching Pei , Jiun-Lei Yu , Chi-Ming Chen , Shih-Chang Liu , Chung-Yi Yu , Chia-Shiung Tsai
IPC分类号： H01L21/20 , H01L21/18
CPC分类号： H01L29/7787 , H01L21/02381 , H01L21/02458 , H01L21/02507 , H01L21/0254 , H01L21/0262 , H01L21/02639 , H01L29/0649 , H01L29/107 , H01L29/2003 , H01L29/66462 , H01L33/007 , H01L33/12
摘要： The present disclosure provides a semiconductor structure. The semiconductor structure includes a dielectric material layer on a silicon substrate, the dielectric material layer being patterned to define a plurality of regions separated by the dielectric material layer; a first buffer layer disposed on the silicon substrate; a heterogeneous buffer layer disposed on the first buffer layer; and a gallium nitride layer grown on the heterogeneous buffer layer only within the plurality of regions.
摘要翻译：本公开提供了一种半导体结构。所述半导体结构包括在硅衬底上的电介质材料层，所述电介质材料层被构图以限定由所述电介质材料层分隔的多个区域; 设置在所述硅衬底上的第一缓冲层; 设置在所述第一缓冲层上的异质缓冲层; 以及仅在多个区域内在异质缓冲层上生长的氮化镓层。

5. 发明申请

US20120211759A1 STRUCTURE AND METHOD TO REDUCE WAFER WARP FOR GALLIUM NITRIDE ON SILICON WAFER 有权
标题翻译：减少氮化硅在硅胶上的波纹的结构和方法
公开(公告)号：US20120211759A1
公开(公告)日：2012-08-23
申请号：US13030645
申请日：2011-02-18
申请人： Ming Chyi Liu , Hsieh Ching Pei , Jiun-Lei Yu , Chi-Ming Chen , Shih-Chang Liu , Chung-Yi Yu , Chia-Shiung Tsai
发明人： Ming Chyi Liu , Hsieh Ching Pei , Jiun-Lei Yu , Chi-Ming Chen , Shih-Chang Liu , Chung-Yi Yu , Chia-Shiung Tsai
IPC分类号： H01L29/20 , H01L21/20
CPC分类号： H01L29/7787 , H01L21/02381 , H01L21/02458 , H01L21/02507 , H01L21/0254 , H01L21/0262 , H01L21/02639 , H01L29/0649 , H01L29/107 , H01L29/2003 , H01L29/66462 , H01L33/007 , H01L33/12
摘要： The present disclosure provides a semiconductor structure. The semiconductor structure includes a dielectric material layer on a silicon substrate, the dielectric material layer being patterned to define a plurality of regions separated by the dielectric material layer; a first buffer layer disposed on the silicon substrate; a heterogeneous buffer layer disposed on the first buffer layer; and a gallium nitride layer grown on the heterogeneous buffer layer only within the plurality of regions.
摘要翻译：本公开提供了一种半导体结构。所述半导体结构包括在硅衬底上的电介质材料层，所述电介质材料层被构图以限定由所述电介质材料层分隔的多个区域; 设置在所述硅衬底上的第一缓冲层; 设置在所述第一缓冲层上的异质缓冲层; 以及仅在多个区域内在异质缓冲层上生长的氮化镓层。

6. 发明授权

US07799654B2 Reduced refractive index and extinction coefficient layer for enhanced photosensitivity 有权
$Reduced refractive index and extinction coefficient layer for enhanced photosensitivity$
标题翻译：降低折射率和消光系数层，提高光敏性
公开(公告)号：US07799654B2
公开(公告)日：2010-09-21
申请号：US11291880
申请日：2005-12-01
申请人： Yuan-Chih Hsieh , Chung-Yi Yu , Tsung-Hsun Huang , Tzu-Hsuan Hsu , Chia-Shiung Tsai
发明人： Yuan-Chih Hsieh , Chung-Yi Yu , Tsung-Hsun Huang , Tzu-Hsuan Hsu , Chia-Shiung Tsai
IPC分类号： H01L21/76 , H01L31/062 , H01L31/111 , H01L27/148 , H01L29/768
CPC分类号： H01L27/14632 , H01L27/14621 , H01L27/14627 , H01L27/14687
摘要： An image sensor device includes a semiconductor substrate and a plurality of pixels on the substrate. An etch-stop layer is formed over the pixels and has a thickness less than about 600 Angstroms. The image sensor device further includes an interlayer dielectric (ILD) overlying the etch stop layer. The etch-stop layer has a refractive index less than about 2 and an extinction coefficient less than about 0.1.
摘要翻译：图像传感器装置包括半导体衬底和衬底上的多个像素。在像素上方形成蚀刻停止层，其厚度小于约600埃。图像传感器装置还包括覆盖在蚀刻停止层上的层间电介质（ILD）。蚀刻停止层的折射率小于约2，消光系数小于约0.1。

7. 发明申请

US20070048965A1 Reduced refractive index and extinction coefficient layer for enhanced photosensitivity 有权
$Reduced refractive index and extinction coefficient layer for enhanced photosensitivity$
标题翻译：降低折射率和消光系数层，提高光敏性
公开(公告)号：US20070048965A1
公开(公告)日：2007-03-01
申请号：US11291880
申请日：2005-12-01
申请人： Yuan-Chih Hsieh , Chung-Yi Yu , Tsung-Hsun Huang , Tzu-Hsuan Hsu , Chia-Shiung Tsai
发明人： Yuan-Chih Hsieh , Chung-Yi Yu , Tsung-Hsun Huang , Tzu-Hsuan Hsu , Chia-Shiung Tsai
IPC分类号： H01L21/76
CPC分类号： H01L27/14632 , H01L27/14621 , H01L27/14627 , H01L27/14687
摘要： An image sensor device includes a semiconductor substrate and a plurality of pixels on the substrate. An etch-stop layer is formed over the pixels and has a thickness less than about 600 Angstroms. The image sensor device further includes an interlayer dielectric (ILD) overlying the etch stop layer. The etch-stop layer has a refractive index less than about 2 and an extinction coefficient less than about 0.1.
摘要翻译：图像传感器装置包括半导体衬底和衬底上的多个像素。在像素上方形成蚀刻停止层，其厚度小于约600埃。图像传感器装置还包括覆盖在蚀刻停止层上的层间电介质（ILD）。蚀刻停止层的折射率小于约2，消光系数小于约0.1。

8. 发明授权

US07544982B2 Image sensor device suitable for use with logic-embedded CIS chips and methods for making the same 有权
标题翻译：适用于逻辑嵌入式CIS芯片的图像传感器装置及其制造方法
公开(公告)号：US07544982B2
公开(公告)日：2009-06-09
申请号：US11542064
申请日：2006-10-03
申请人： Chung-Yi Yu , Chia-Shiung Tsai , Shih-Chi Fu
发明人： Chung-Yi Yu , Chia-Shiung Tsai , Shih-Chi Fu
IPC分类号： H01L31/062
CPC分类号： H01L27/14627 , H01L27/14621 , H01L27/14632 , H01L27/14636 , H01L27/14685 , H01L27/14687
摘要： An image sensor device is provided. A substrate has a photosensor region formed therein and/or thereon. An interconnection structure is formed over the substrate, and includes metal lines formed in inter-metal dielectric (IMD) layers. At least one IMD-level micro-lens is/are formed in at least one of the IMD layers over the photosensor region. Preferably, barrier layers are located between the IMD layers. Preferably, each of the barrier layers at each level has a net thickness limited to 100 angstroms or less at locations over the photosensor region, except at locations where the IMD-level micro-lenses are located. The IMD-level micro-lenses and the etch stop layers preferably have a refractive index greater than that of the IMD layers. A cap layer is preferably formed on the metal lines, especially when the metal lines include copper. An upper-level micro-lens may be located on a level that is above the interconnection structure.
摘要翻译：提供图像传感器装置。衬底在其中和/或其上形成有光电传感器区域。在衬底上形成互连结构，并且包括在金属间电介质（IMD）层中形成的金属线。在光电传感器区域中的至少一个IMD层中形成至少一个IMD级微透镜。优选地，阻挡层位于IMD层之间。优选地，除了在IMD级微透镜所在的位置之外，每个级别的每个阻挡层的净厚度在光电传感器区域之外的位置处具有限制在100埃或更小的净厚度。 IMD级微透镜和蚀刻停止层优选具有大于IMD层的折射率的折射率。优选在金属线上形成覆盖层，特别是当金属线包括铜时。上级微透镜可以位于互连结构之上的层上。

9. 发明申请

US20080087921A1 Image sensor device suitable for use with logic-embedded CIS chips and methods for making the same 有权
标题翻译：适用于逻辑嵌入式CIS芯片的图像传感器装置及其制造方法
公开(公告)号：US20080087921A1
公开(公告)日：2008-04-17
申请号：US11542064
申请日：2006-10-03
申请人： Chung-Yi Yu , Chia-Shiung Tsai , Shih-Chi Fu
发明人： Chung-Yi Yu , Chia-Shiung Tsai , Shih-Chi Fu
IPC分类号： H01L29/76 , H01L29/745
CPC分类号： H01L27/14627 , H01L27/14621 , H01L27/14632 , H01L27/14636 , H01L27/14685 , H01L27/14687
摘要： An image sensor device is provided. A substrate has a photosensor region formed therein and/or thereon. An interconnection structure is formed over the substrate, and includes metal lines formed in inter-metal dielectric (IMD) layers. At least one IMD-level micro-lens is/are formed in at least one of the IMD layers over the photosensor region. Preferably, barrier layers are located between the IMD layers. Preferably, each of the barrier layers at each level has a net thickness limited to 100 angstroms or less at locations over the photosensor region, except at locations where the IMD-level micro-lenses are located. The IMD-level micro-lenses and the etch stop layers preferably have a refractive index greater than that of the IMD layers. A cap layer is preferably formed on the metal lines, especially when the metal lines include copper. An upper-level micro-lens may be located on a level that is above the interconnection structure.
摘要翻译：提供图像传感器装置。衬底在其中和/或其上形成有光电传感器区域。在衬底上形成互连结构，并且包括在金属间电介质（IMD）层中形成的金属线。在光电传感器区域中的至少一个IMD层中形成至少一个IMD级微透镜。优选地，阻挡层位于IMD层之间。优选地，除了在IMD级微透镜所在的位置之外，每个级别的每个阻挡层的净厚度在光电传感器区域之外的位置处具有限制在100埃或更小的净厚度。 IMD级微透镜和蚀刻停止层优选具有大于IMD层的折射率的折射率。优选在金属线上形成覆盖层，特别是当金属线包括铜时。上级微透镜可以位于互连结构之上的层上。

10. 发明授权

US09142407B2 Semiconductor structure having sets of III-V compound layers and method of forming the same 有权
标题翻译：具有III-V族化合物层的半导体结构及其形成方法
公开(公告)号：US09142407B2
公开(公告)日：2015-09-22
申请号：US13743045
申请日：2013-01-16
申请人： Chi-Ming Chen , Po-Chun Liu , Chung-Yi Yu , Chia-Shiung Tsai
发明人： Chi-Ming Chen , Po-Chun Liu , Chung-Yi Yu , Chia-Shiung Tsai
IPC分类号： H01L29/66 , H01L21/02 , H01L29/778 , H01L29/15 , H01L29/20
CPC分类号： H01L21/02507 , H01L21/02458 , H01L21/02505 , H01L21/0251 , H01L21/0254 , H01L29/157 , H01L29/2003 , H01L29/205 , H01L29/66462 , H01L29/66522 , H01L29/778 , H01L29/7787
摘要： A semiconductor structure includes a substrate, a first III-V compound layer over the substrate, one or more sets of III-V compound layers over the first III-V compound layer, a second III-V compound layer over the one or more sets of III-V compound layers, and an active layer over the second III-V compound layer. The first III-V compound layer has a first type doping. Each of the one or more sets of III-V compound layers includes a lower III-V compound layer and an upper III-V compound layer over the lower III-V compound layer. The upper III-V compound layer having the first type doping, and the lower III-V compound layer is at least one of undoped, unintentionally doped having a second type doping, or doped having the second type doping. The second III-V compound layer is either undoped or unintentionally doped having the second type doping.
摘要翻译：半导体结构包括衬底，在衬底上的第一III-V化合物层，在第一III-V化合物层上的一组或多组III-V化合物层，在一个或多个组上的第二III-V化合物层的III-V化合物层，以及在第二III-V化合物层上的活性层。第一III-V族化合物层具有第一种掺杂。一组或多组III-V化合物层中的每一个在下III-V化合物层上包括下III-V化合物层和上III-V化合物层。具有第一类掺杂的上III-V化合物层和下III-V族化合物层是至少一种未掺杂的，无意掺杂的具有第二类型掺杂或掺杂具有第二类掺杂的至少一种。第二III-V族化合物层是未掺杂的或无意掺杂的，具有第二种掺杂。

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