专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06893909B2 Method of manufacturing metal-oxide-semiconductor transistor 有权
标题翻译：制造金属氧化物半导体晶体管的方法
公开(公告)号：US06893909B2
公开(公告)日：2005-05-17
申请号：US10681768
申请日：2003-10-07
申请人： Yu-Ren Wang , Chun-Yi Lee , Yu-Kun Chen , Neng-Hui Yang
发明人： Yu-Ren Wang , Chun-Yi Lee , Yu-Kun Chen , Neng-Hui Yang
IPC分类号： H01L21/00 , H01L21/265 , H01L21/28 , H01L21/336 , H01L29/78
CPC分类号： H01L29/6659 , H01L21/265 , H01L21/28035 , H01L29/6656 , H01L29/7833
摘要： A method of manufacturing a MOS transistor is provided. A gate insulation layer and a conductive layer are sequentially formed over a substrate. A pre-amorphization implantation is carried out to amorphize the conductive layer. The conductive layer and the gate insulation layer are patterned to form a gate structure. A first spacer is formed on the sidewall of the gate structure. A second pre-amorphization implantation is carried out to amorphize a portion of the substrate. A doped source/drain extension region is formed in the substrate on each side of the first spacer. A second spacer is formed on the sidewall of the first spacer and then a doped source/drain region is formed in the substrate on each side of the second spacer. A solid phase epitaxial process is carried out to convert the doped source/drain extension region and the doped source/drain region into a source/drain terminal. In the pre-amorphization implantations, dopants having an ionic radius greater than the germanium ion are used.
摘要翻译：提供一种制造MOS晶体管的方法。栅极绝缘层和导电层依次形成在衬底上。进行前非晶化注入以使导电层非晶化。将导电层和栅极绝缘层图案化以形成栅极结构。在栅极结构的侧壁上形成第一间隔物。进行第二次非晶化植入以使基板的一部分非晶化。在第一间隔物的每一侧上的衬底中形成掺杂的源极/漏极延伸区域。在第一间隔物的侧壁上形成第二间隔物，然后在第二间隔物的每一侧上的衬底中形成掺杂源/漏区。进行固相外延处理以将掺杂的源极/漏极延伸区域和掺杂的源极/漏极区域转换成源极/漏极端子。在前非晶化注入中，使用离子半径大于锗离子的掺杂剂。

2. 发明申请

US20050074931A1 METHOD OF MANUFACTURING METAL-OXIDE-SEMICONDUCTOR TRANSISTOR 有权
标题翻译：制造金属氧化物半导体晶体管的方法
公开(公告)号：US20050074931A1
公开(公告)日：2005-04-07
申请号：US10681768
申请日：2003-10-07
申请人： Yu-Ren Wang , Chun-Yi Lee , Yu-Kun Chen , Neng-Hui Yang
发明人： Yu-Ren Wang , Chun-Yi Lee , Yu-Kun Chen , Neng-Hui Yang
IPC分类号： H01L21/00 , H01L21/265 , H01L21/28 , H01L21/336 , H01L29/78
CPC分类号： H01L29/6659 , H01L21/265 , H01L21/28035 , H01L29/6656 , H01L29/7833
摘要： A method of manufacturing a MOS transistor is provided. A gate insulation layer and a conductive layer are sequentially formed over a substrate. A pre-amorphization implantation is carried out to amorphize the conductive layer. The conductive layer and the gate insulation layer are patterned to form a gate structure. A first spacer is formed on the sidewall of the gate structure. A second pre-amorphization implantation is carried out to amorphize a portion of the substrate. A doped source/drain extension region is formed in the substrate on each side of the first spacer. A second spacer is formed on the sidewall of the first spacer and then a doped source/drain region is formed in the substrate on each side of the second spacer. A solid phase epitaxial process is carried out to convert the doped source/drain extension region and the doped source/drain region into a source/drain terminal. In the pre-amorphization implantations, dopants having an ionic radius greater than the germanium ion are used.
摘要翻译：提供一种制造MOS晶体管的方法。栅极绝缘层和导电层依次形成在衬底上。进行前非晶化注入以使导电层非晶化。将导电层和栅极绝缘层图案化以形成栅极结构。在栅极结构的侧壁上形成第一间隔物。进行第二次非晶化植入以使基板的一部分非晶化。在第一间隔物的每一侧上的衬底中形成掺杂的源极/漏极延伸区域。在第一间隔物的侧壁上形成第二间隔物，然后在第二间隔物的每一侧上的衬底中形成掺杂源/漏区。进行固相外延处理以将掺杂的源极/漏极延伸区域和掺杂的源极/漏极区域转换成源极/漏极端子。在前非晶化注入中，使用离子半径大于锗离子的掺杂剂。

3. 发明授权

US07435658B2 Method of manufacturing metal-oxide-semiconductor transistor 有权
标题翻译：制造金属氧化物半导体晶体管的方法
公开(公告)号：US07435658B2
公开(公告)日：2008-10-14
申请号：US11147506
申请日：2005-06-07
申请人： Yu-Ren Wang , Chin-Cheng Chien , Hsiang-Ying Wang , Neng-Hui Yang
发明人： Yu-Ren Wang , Chin-Cheng Chien , Hsiang-Ying Wang , Neng-Hui Yang
IPC分类号： H01L21/336
CPC分类号： H01L29/6659 , H01L21/26513 , H01L29/6656 , H01L29/66666
摘要： A method of manufacturing a MOS transistor is provided. A substrate having a gate structure thereon is provided. A first spacer is formed on the sidewall of the gate structure. A pre-amorphization implantation is carried out to amorphize a portion of the substrate. A doped source/drain extension region is formed in the substrate on each side of the first spacer. A second spacer is formed on the sidewall of the first spacer. A doped source/drain region is formed in the substrate on each side of the second spacer. Thereafter, a solid phase epitaxial process is carried out to re-crystallize the amorphized portion of the substrate and activate the doped source/drain extension region and the doped source/drain region to form a source/drain terminal. Finally, a post-annealing operation is performed.
摘要翻译：提供一种制造MOS晶体管的方法。提供其上具有栅极结构的衬底。在栅极结构的侧壁上形成第一间隔物。进行预非晶化注入以使基板的一部分非晶化。在第一间隔物的每一侧上的衬底中形成掺杂的源极/漏极延伸区域。第二间隔件形成在第一间隔件的侧壁上。在第二间隔物的每一侧上的衬底中形成掺杂源/漏区。此后，进行固相外延处理以重新结晶衬底的非晶化部分并激活掺杂的源极/漏极延伸区域和掺杂源极/漏极区域以形成源极/漏极端子。最后，执行后退火操作。

4. 发明申请

US20050130434A1 Method of surface pretreatment before selective epitaxial growth 审中-公开
标题翻译：选择性外延生长前的表面预处理方法
公开(公告)号：US20050130434A1
公开(公告)日：2005-06-16
申请号：US10734197
申请日：2003-12-15
申请人： Chin-Cheng Chien , Ya-Lun Cheng , Yu-Ren Wang , Neng-Hui Yang
发明人： Chin-Cheng Chien , Ya-Lun Cheng , Yu-Ren Wang , Neng-Hui Yang
IPC分类号： C30B25/18 , H01L21/20 , H01L21/306 , H01L21/336 , C30B1/00
CPC分类号： H01L21/02046 , C30B25/18 , H01L21/02381 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L29/665 , H01L29/6659 , H01L29/66636
摘要： A method of surface pretreatment before selective epitaxial growth is provided. A semiconductor substrate having metal-oxide-semiconductor devices formed thereon is provided, and a lightly dry etching process with a carbon-free plasma source is performed to remove a portion of the semiconductor substrate. Then, a selective epitaxial growth process is performed to form a semiconductor layer on the semiconductor substrate. A clean surface for selective epitaxial growth is provided by the lightly dry etching process, which can resolve the undercut issue and surface roughness.
摘要翻译：提供了选择性外延生长前的表面预处理方法。提供其上形成有金属氧化物半导体器件的半导体衬底，并且执行具有无碳等离子体源的轻度干蚀刻工艺以去除半导体衬底的一部分。然后，进行选择性外延生长工艺以在半导体衬底上形成半导体层。用于选择性外延生长的清洁表面通过轻度干蚀刻工艺提供，其可以解决底切问题和表面粗糙度。

5. 发明授权

US06943085B2 Method of manufacturing metal-oxide-semiconductor transistor 有权
公开(公告)号：US06943085B2
公开(公告)日：2005-09-13
申请号：US10667229
申请日：2003-09-17
申请人： Yu-Ren Wang , Chin-Cheng Chien , Hsiang-Ying Wang , Neng-Hui Yang
发明人： Yu-Ren Wang , Chin-Cheng Chien , Hsiang-Ying Wang , Neng-Hui Yang
IPC分类号： H01L21/265 , H01L21/336
CPC分类号： H01L29/6659 , H01L21/26513 , H01L29/6656 , H01L29/66666
摘要： A method of manufacturing a MOS transistor is provided. A substrate having a gate structure thereon is provided. A first spacer is formed on the sidewall of the gate structure. A pre-amorphization implantation is carried out to amorphize a portion of the substrate. A doped source/drain extension region is formed in the substrate on each side of the first spacer. A second spacer is formed on the sidewall of the first spacer. A doped source/drain region is formed in the substrate on each side of the second spacer and then a pre-annealing operation is performed. Thereafter, a solid phase epitaxial process is carried out to re-crystallize the amorphized portion of the substrate and activate the doped source/drain extension region and the doped source/drain region to form a source/drain terminal. Finally, a post-annealing operation is performed.

6. 发明申请

US20050054173A1 Method of manufacturing metal-oxide-semiconductor transistor 有权
标题翻译：金属氧化物半导体晶体管的制造方法
公开(公告)号：US20050054173A1
公开(公告)日：2005-03-10
申请号：US10667229
申请日：2003-09-17
申请人： Yu-Ren Wang , Chin-Cheng Chien , Hsiang-Ying Wang , Neng-Hui Yang
发明人： Yu-Ren Wang , Chin-Cheng Chien , Hsiang-Ying Wang , Neng-Hui Yang
IPC分类号： H01L21/265 , H01L21/336 , H01L21/331
CPC分类号： H01L29/6659 , H01L21/26513 , H01L29/6656 , H01L29/66666
摘要： A method of manufacturing a MOS transistor is provided. A substrate having a gate structure thereon is provided. A first spacer is formed on the sidewall of the gate structure. A pre-amorphization implantation is carried out to amorphize a portion of the substrate. A doped source/drain extension region is formed in the substrate on each side of the first spacer. A second spacer is formed on the sidewall of the first spacer. A doped source/drain region is formed in the substrate on each side of the second spacer and then a pre-annealing operation is performed. Thereafter, a solid phase epitaxial process is carried out to re-crystallize the amorphized portion of the substrate and activate the doped source/drain extension region and the doped source/drain region to form a source/drain terminal. Finally, a post-annealing operation is performed.
摘要翻译：提供一种制造MOS晶体管的方法。提供其上具有栅极结构的衬底。在栅极结构的侧壁上形成第一间隔物。进行预非晶化注入以使基板的一部分非晶化。在第一间隔物的每一侧上的衬底中形成掺杂的源极/漏极延伸区域。第二间隔件形成在第一间隔件的侧壁上。在第二间隔物的每一侧上的衬底中形成掺杂的源/漏区，然后进行预退火操作。此后，进行固相外延处理以重新结晶衬底的非晶化部分并激活掺杂的源极/漏极延伸区域和掺杂源极/漏极区域以形成源极/漏极端子。最后，执行后退火操作。

7. 发明授权

US07306681B2 Method of cleaning a semiconductor substrate 有权
标题翻译：清洗半导体衬底的方法
公开(公告)号：US07306681B2
公开(公告)日：2007-12-11
申请号：US10843444
申请日：2004-05-12
申请人： Ya-Lun Cheng , Yi-Chia Lee , Yu-Ren Wang , Neng-Hui Yang
发明人： Ya-Lun Cheng , Yi-Chia Lee , Yu-Ren Wang , Neng-Hui Yang
IPC分类号： B08B3/00
CPC分类号： H01L21/02052 , B08B3/08 , C11D3/3942 , C11D3/3947 , C11D7/08 , C11D11/0047 , Y10S438/906
摘要： A cleaning method and cleaning recipes are disclosed. The present invention relates to a method for cleaning a semiconductor substrate and cleaning recipes. The present invention utilizes a first cleaning solution including diluted hydrofluoric acid and a second cleaning solution including hydrogen chloride and hydrogen peroxide (H2O2) to clean a semiconductor substrate without using an alkaline solution including ammonium hydroxide. Accordingly, a clean surface of a semiconductor substrate is provided in selective epitaxial growth (SEG) process to grow an epitaxial layer with smooth surface.
摘要翻译：公开了一种清洁方法和清洁配方。本发明涉及一种清洗半导体衬底和清洁配方的方法。本发明利用包含稀释氢氟酸的第一清洗溶液和包含氯化氢和过氧化氢（H 2 O 2 O 2）的第二清洗溶液来清洁半导体衬底而不使用包括氢氧化铵的碱性溶液。因此，在选择性外延生长（SEG）工艺中提供半导体衬底的干净的表面以生长具有光滑表面的外延层。

8. 发明申请

US20050272213A1 Method of manufacturing metal-oxide-semiconductor transistor 有权
标题翻译：制造金属氧化物半导体晶体管的方法
公开(公告)号：US20050272213A1
公开(公告)日：2005-12-08
申请号：US11147506
申请日：2005-06-07
申请人： Yu-Ren Wang , Chin-Cheng Chien , Hsiang-Ying Wang , Neng-Hui Yang
发明人： Yu-Ren Wang , Chin-Cheng Chien , Hsiang-Ying Wang , Neng-Hui Yang
IPC分类号： H01L21/265 , H01L21/336
CPC分类号： H01L29/6659 , H01L21/26513 , H01L29/6656 , H01L29/66666
摘要： A method of manufacturing a MOS transistor is provided. A substrate having a gate structure thereon is provided. A first spacer is formed on the sidewall of the gate structure. A pre-amorphization implantation is carried out to amorphize a portion of the substrate. A doped source/drain extension region is formed in the substrate on each side of the first spacer. A second spacer is formed on the sidewall of the first spacer. A doped source/drain region is formed in the substrate on each side of the second spacer. Thereafter, a solid phase epitaxial process is carried out to re-crystallize the amorphized portion of the substrate and activate the doped source/drain extension region and the doped source/drain region to form a source/drain terminal. Finally, a post-annealing operation is performed.
摘要翻译：提供一种制造MOS晶体管的方法。提供其上具有栅极结构的衬底。在栅极结构的侧壁上形成第一间隔物。进行预非晶化注入以使基板的一部分非晶化。在第一间隔物的每一侧上的衬底中形成掺杂的源极/漏极延伸区域。第二间隔件形成在第一间隔件的侧壁上。在第二间隔物的每一侧上的衬底中形成掺杂源/漏区。此后，进行固相外延处理以重新结晶衬底的非晶化部分并激活掺杂的源极/漏极延伸区域和掺杂源极/漏极区域以形成源极/漏极端子。最后，执行后退火操作。

9. 发明申请

US20050252525A1 Method of cleaning a semiconductor substrate and cleaning recipes 有权
标题翻译：清洗半导体衬底和清洁配方的方法
公开(公告)号：US20050252525A1
公开(公告)日：2005-11-17
申请号：US10843444
申请日：2004-05-12
申请人： Ya-Lun Cheng , Yi-Chia Lee , Yu-Ren Wang , Neng-Hui Yang
发明人： Ya-Lun Cheng , Yi-Chia Lee , Yu-Ren Wang , Neng-Hui Yang
IPC分类号： B08B3/08 , B08B6/00 , C11D3/39 , C11D7/08 , C11D11/00 , H01L21/02
CPC分类号： H01L21/02052 , B08B3/08 , C11D3/3942 , C11D3/3947 , C11D7/08 , C11D11/0047 , Y10S438/906
摘要： A cleaning method and cleaning recipes are disclosed. The present invention relates to a method for cleaning a semiconductor substrate and cleaning recipes. The present invention utilizes a first cleaning solution including diluted hydrofluoric acid and a second cleaning solution including hydrogen chloride and hydrogen peroxide (H2O2) to clean a semiconductor substrate without using an alkaline solution including ammonium hydroxide. Accordingly, a clean surface of a semiconductor substrate is provided in selective epitaxial growth (SEG) process to grow an epitaxial layer with smooth surface.
摘要翻译：公开了一种清洁方法和清洁配方。本发明涉及一种清洗半导体衬底和清洁配方的方法。本发明利用包含稀释氢氟酸的第一清洗溶液和包含氯化氢和过氧化氢（H 2 O 2 O 2）的第二清洗溶液来清洁半导体衬底而不使用包括氢氧化铵的碱性溶液。因此，在选择性外延生长（SEG）工艺中提供半导体衬底的干净的表面以生长具有光滑表面的外延层。

10. 发明授权

US08921238B2 Method for processing high-k dielectric layer 有权
标题翻译：高k电介质层的处理方法
公开(公告)号：US08921238B2
公开(公告)日：2014-12-30
申请号：US13235515
申请日：2011-09-19
申请人： Shao-Wei Wang , Yu-Ren Wang , Chien-Liang Lin , Wen-Yi Teng , Tsuo-Wen Lu , Chih-Chung Chen , Ying-Wei Yen
发明人： Shao-Wei Wang , Yu-Ren Wang , Chien-Liang Lin , Wen-Yi Teng , Tsuo-Wen Lu , Chih-Chung Chen , Ying-Wei Yen
IPC分类号： H01L21/31 , H01L21/3105 , H01L21/02
CPC分类号： H01L21/3105 , H01L21/02148 , H01L21/02178 , H01L21/02181 , H01L21/02183 , H01L21/02192 , H01L21/02197 , H01L21/0228
摘要： A method for processing a high-k dielectric layer includes the following steps. A semiconductor substrate is provided, and a high-k dielectric layer is formed thereon. The high-k dielectric layer has a crystalline temperature. Subsequently, a first annealing process is performed, and a process temperature of the first annealing process is substantially smaller than the crystalline temperature. A second annealing process is performed, and a process temperature of the second annealing process is substantially larger than the crystalline temperature.
摘要翻译：一种用于处理高k电介质层的方法包括以下步骤。提供半导体衬底，并且在其上形成高k电介质层。高k电介质层具有结晶温度。随后，进行第一退火处理，并且第一退火工艺的处理温度显着小于结晶温度。进行第二退火处理，第二退火处理的工艺温度显着大于结晶温度。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式