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    • 1. 发明授权
    • Method and apparatus for software management of on-chip cache
    • 片上缓存的软件管理方法和装置
    • US06859862B1
    • 2005-02-22
    • US09545184
    • 2000-04-07
    • Yu-Chung C. LiaoPeter A. SandonHoward ChengPeter Hsu
    • Yu-Chung C. LiaoPeter A. SandonHoward ChengPeter Hsu
    • G06F12/08G06F9/30G06F12/12
    • G06F9/30047G06F12/126
    • A microprocessor including a control unit and a cache connected with the control unit for storing data to be used by the control, wherein the cache is selectively configurable as either a single cache or as a partitioned cache having a locked cache portion and a normal cache portion. The normal cache portion is controlled by a hardware implemented automatic replacement process. The locked cache portion is locked so that the automatic replacement process cannot modify the contents of the locked cache. An instruction is provided in the instruction set that enables software to selectively allocate lines in the locked cache portion to correspond to locations in an external memory, thereby enabling the locked cache portion to be completely managed by software.
    • 一种微处理器,包括与所述控制单元连接的控制单元和高速缓存,用于存储要由所述控制使用的数据,其中所述高速缓存可选择性地配置为单个高速缓存或具有锁定的高速缓存部分和正常高速缓存部分的分区高速缓存 。 正常缓存部分由硬件实现的自动替换过程控制。 锁定的高速缓存部分被锁定,使得自动替换进程不能修改锁定的高速缓存的内容。 在指令集中提供指令,使得软件能够选择性地在锁定的高速缓存部分中分配线以对应于外部存储器中的位置,从而使锁定的高速缓存部分能够被软件完全地管理。
    • 2. 发明授权
    • Method and apparatus for software management of on-chip cache
    • 片上缓存的软件管理方法和装置
    • US06681296B2
    • 2004-01-20
    • US09918703
    • 2001-08-01
    • Yu-Chung C. LiaoPeter A. SandonHoward ChengPeter Hsu
    • Yu-Chung C. LiaoPeter A. SandonHoward ChengPeter Hsu
    • G06F1208
    • G06F9/30047G06F12/126
    • A microprocessor including a control unit and a cache connected with the control unit for storing data to be used by the control, wherein the cache is selectively configurable as either a single cache or as a partitioned cache having a locked cache portion and a normal cache portion. The normal cache portion is controlled by a hardware implemented automatic replacement process. The locked cache portion is locked so that the automatic replacement process cannot modify the contents of the locked cache. An instruction is provided in the instruction set that enables software to selectively allocate lines in the locked cache portion to correspond to locations in an external memory, thereby enabling the locked cache portion to be completely managed by software.
    • 一种微处理器,包括与所述控制单元连接的控制单元和高速缓存,用于存储要由所述控制使用的数据,其中所述高速缓存可选择性地配置为单个高速缓存或具有锁定的高速缓存部分和正常高速缓存部分的分区高速缓存 。 正常缓存部分由硬件实现的自动替换过程控制。 锁定的高速缓存部分被锁定,使得自动替换进程不能修改锁定的高速缓存的内容。 在指令集中提供指令,使得软件能够选择性地在锁定的高速缓存部分中分配线以对应于外部存储器中的位置,从而使锁定的高速缓存部分能够被软件完全地管理。
    • 10. 发明授权
    • Method and apparatus for converting data into different ordinal types
    • 将数据转换为不同序数类型的方法和装置
    • US06591361B1
    • 2003-07-08
    • US09473760
    • 1999-12-28
    • Yu-Chung LiaoPeter A. SandonHoward Cheng
    • Yu-Chung LiaoPeter A. SandonHoward Cheng
    • G06F9302
    • G06F9/3001G06F9/30025G06F9/30043
    • A method and apparatus that converts integer numbers to/from floating point representations while loading/storing the data. The method and apparatus perform this conversion within a central processing unit having a converter unit and a set of conversion registers. The load/store instructions having data requiring conversion include an index field for identifying one of the conversion registers. Each one of the conversion registers includes information on the type of conversion required and any scaling factors to be applied. Upon receiving one of these instructions, the converter uses the identified conversion register to perform the conversion and stores the converted data into the corresponding register or memory location.
    • 一种在加载/存储数据时将整数转换成浮点表示的方法和装置。 该方法和装置在具有转换器单元和一组转换寄存器的中央处理单元内执行该转换。 具有需要转换的数据的加载/存储指令包括用于识别转换寄存器之一的索引字段。 每个转换寄存器包括有关所需转换类型和要应用的任何缩放因子的信息。 在接收到这些指令之一时,转换器使用所识别的转换寄存器来执行转换,并将转换的数据存储到相应的寄存器或存储单元中。