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    • 2. 发明授权
    • Stacked amplifier with diode-based biasing
    • 具有基于二极管的偏置的堆叠放大器
    • US08847689B2
    • 2014-09-30
    • US12711858
    • 2010-02-24
    • Yu ZhaoNathan M. Pletcher
    • Yu ZhaoNathan M. Pletcher
    • H03F3/04
    • H03F1/0283H03F1/301H03F3/189
    • Techniques for improving linearity of amplifiers are described. In an exemplary design, an amplifier (e.g., a power amplifier) may include a plurality of transistors coupled in a stack and at least one diode. The plurality of transistors may receive and amplify an input signal and provide an output signal. The at least one diode may be operatively coupled to at least one transistor in the stack. Each diode may provide a variable bias voltage to an associated transistor in the stack. Each diode may have a lower voltage drop across the diode at high input power and may provide a higher bias voltage to the associated transistor at high input power. The at least one transistor may have higher gain at high input power due to the higher bias voltage from the at least one diode. The higher gain may improve the linearity of the amplifier.
    • 描述了用于提高放大器线性度的技术。 在示例性设计中,放大器(例如,功率放大器)可以包括耦合在堆叠中的多个晶体管和至少一个二极管。 多个晶体管可以接收和放大输入信号并提供输出信号。 至少一个二极管可以可操作地耦合到堆叠中的至少一个晶体管。 每个二极管可以向堆叠中的相关联的晶体管提供可变偏置电压。 每个二极管可以在高输入功率下在二极管上具有较低的电压降,并且可以在高输入功率下向相关联的晶体管提供更高的偏置电压。 由于来自至少一个二极管的较高偏置电压,至少一个晶体管可能在高输入功率下具有更高的增益。 较高的增益可以提高放大器的线性度。
    • 4. 发明申请
    • DIGITAL TUNABLE INTER-STAGE MATCHING CIRCUIT
    • 数字可调节间歇匹配电路
    • US20110043285A1
    • 2011-02-24
    • US12715254
    • 2010-03-01
    • Yu ZhaoBabak NejatiNathan M. PletcherAristotele Hadjichristos
    • Yu ZhaoBabak NejatiNathan M. PletcherAristotele Hadjichristos
    • H03F3/16
    • H03F1/42H03F1/223H03F3/193H03F2200/318H03H7/40
    • A tunable inter-stage matching circuit that can improve performance is described. In an exemplary design, an apparatus includes a first active circuit (e.g., a driver amplifier), a second active circuit (e.g., a power amplifier), and a tunable inter-stage matching circuit coupled between the first and second active circuits. The tunable inter-stage matching circuit includes a tunable capacitor that can be varied in discrete steps to adjust impedance matching between the first and second active circuits. In an exemplary design, the tunable capacitor includes (i) a plurality of capacitors coupled in parallel and (ii) a plurality of switches coupled to the plurality of capacitors, one switch for each capacitor. Each switch may be turned on to select an associated capacitor or turned off to unselect the associated capacitor. The tunable capacitor may further include a fixed capacitor coupled in parallel with the plurality of capacitors.
    • 描述了可以提高性能的可调谐级间匹配电路。 在示例性设计中,装置包括耦合在第一和第二有源电路之间的第一有源电路(例如,驱动器放大器),第二有源电路(例如,功率放大器)和可调谐级间匹配电路。 可调谐级间匹配电路包括可以在离散步骤中变化的可调谐电容器,以调整第一和第二有源电路之间的阻抗匹配。 在示例性设计中,可调谐电容器包括(i)并联耦合的多个电容器和(ii)耦合到多个电容器的多个开关,用于每个电容器的一个开关。 每个开关可以被接通以选择一个相关联的电容器或关闭以取消选择相关联的电容器。 可调谐电容器还可以包括与多个电容器并联耦合的固定电容器。
    • 5. 发明授权
    • Amplifier with variable matching circuit to improve linearity
    • 具有可变匹配电路的放大器,以提高线性度
    • US08779857B2
    • 2014-07-15
    • US12699659
    • 2010-02-03
    • Nathan M. PletcherYu Zhao
    • Nathan M. PletcherYu Zhao
    • H03F3/191
    • H03F1/565H03F1/086H03F3/193
    • Techniques for reducing distortion and improving linearity of amplifiers are described. In an exemplary design, an apparatus includes a driver amplifier, a variable matching circuit, and a power amplifier. The driver amplifier amplifies a first RF signal and provides a second RF signal. The variable matching circuit receives the second RF signal and provides a third RF signal. The power amplifier amplifies the third RF signal and provides a fourth RF signal. The variable matching circuit matches a fixed impedance at the output of the driver amplifier to a variable impedance at the input of the power amplifier in order to improve the linearity of the amplifiers. In an exemplary design, the power amplifier includes a first transistor (e.g., an NMOS transistor) of a first type, and the variable matching circuit includes a second transistor (e.g., a PMOS transistor) of a second type that is different from the first type.
    • 描述了减小失真和提高放大器线性度的技术。 在示例性设计中,装置包括驱动器放大器,可变匹配电路和功率放大器。 驱动器放大器放大第一RF信号并提供第二RF信号。 可变匹配电路接收第二RF信号并提供第三RF信号。 功率放大器放大第三RF信号并提供第四RF信号。 可变匹配电路将驱动放大器输出端的固定阻抗与功率放大器输入端的可变阻抗相匹配,以提高放大器的线性度。 在示例性设计中,功率放大器包括第一类型的第一晶体管(例如,NMOS晶体管),并且可变匹配电路包括与第一类型不同的第二类型的第二晶体管(例如,PMOS晶体管) 类型。
    • 7. 发明申请
    • AMPLIFIER WITH VARIABLE MATCHING CIRCUIT TO IMPROVE LINEARITY
    • 具有可变匹配电路的放大器,以提高线性度
    • US20110037519A1
    • 2011-02-17
    • US12699659
    • 2010-02-03
    • Nathan M. PletcherYu Zhao
    • Nathan M. PletcherYu Zhao
    • H03F3/16
    • H03F1/565H03F1/086H03F3/193
    • Techniques for reducing distortion and improving linearity of amplifiers are described. In an exemplary design, an apparatus includes a driver amplifier, a variable matching circuit, and a power amplifier. The driver amplifier amplifies a first RF signal and provides a second RF signal. The variable matching circuit receives the second RF signal and provides a third RF signal. The power amplifier amplifies the third RF signal and provides a fourth RF signal. The variable matching circuit matches a fixed impedance at the output of the driver amplifier to a variable impedance at the input of the power amplifier in order to improve the linearity of the amplifiers. In an exemplary design, the power amplifier includes a first transistor (e.g., an NMOS transistor) of a first type, and the variable matching circuit includes a second transistor (e.g., a PMOS transistor) of a second type that is different from the first type.
    • 描述了减小失真和提高放大器线性度的技术。 在示例性设计中,装置包括驱动器放大器,可变匹配电路和功率放大器。 驱动器放大器放大第一RF信号并提供第二RF信号。 可变匹配电路接收第二RF信号并提供第三RF信号。 功率放大器放大第三RF信号并提供第四RF信号。 可变匹配电路将驱动放大器输出端的固定阻抗与功率放大器输入端的可变阻抗相匹配,以提高放大器的线性度。 在示例性设计中,功率放大器包括第一类型的第一晶体管(例如,NMOS晶体管),并且可变匹配电路包括与第一类型不同的第二类型的第二晶体管(例如,PMOS晶体管) 类型。
    • 9. 发明申请
    • STACKED AMPLIFIER WITH DIODE-BASED BIASING
    • 基于二极管偏置的堆叠放大器
    • US20110043284A1
    • 2011-02-24
    • US12711858
    • 2010-02-24
    • Yu ZhaoNathan M. Pletcher
    • Yu ZhaoNathan M. Pletcher
    • H03F3/16
    • H03F1/0283H03F1/301H03F3/189
    • Techniques for improving linearity of amplifiers are described. In an exemplary design, an amplifier (e.g., a power amplifier) may include a plurality of transistors coupled in a stack and at least one diode. The plurality of transistors may receive and amplify an input signal and provide an output signal. The at least one diode may be operatively coupled to at least one transistor in the stack. Each diode may provide a variable bias voltage to an associated transistor in the stack. Each diode may have a lower voltage drop across the diode at high input power and may provide a higher bias voltage to the associated transistor at high input power. The at least one transistor may have higher gain at high input power due to the higher bias voltage from the at least one diode. The higher gain may improve the linearity of the amplifier.
    • 描述了用于提高放大器线性度的技术。 在示例性设计中,放大器(例如,功率放大器)可以包括耦合在堆叠中的多个晶体管和至少一个二极管。 多个晶体管可以接收和放大输入信号并提供输出信号。 至少一个二极管可以可操作地耦合到堆叠中的至少一个晶体管。 每个二极管可以向堆叠中的相关联的晶体管提供可变偏置电压。 每个二极管可以在高输入功率下在二极管上具有较低的电压降,并且可以在高输入功率下向相关联的晶体管提供更高的偏置电压。 由于来自至少一个二极管的较高偏置电压,至少一个晶体管可能在高输入功率下具有更高的增益。 较高的增益可以提高放大器的线性度。
    • 10. 发明申请
    • MULTI-STAGE IMPEDANCE MATCHING
    • 多级阻抗匹配
    • US20110037516A1
    • 2011-02-17
    • US12641228
    • 2009-12-17
    • Babak NejatiYu ZhaoNathan M. PletcherAristotele HadjichristosPuay Hoe See
    • Babak NejatiYu ZhaoNathan M. PletcherAristotele HadjichristosPuay Hoe See
    • H03F3/68
    • H03F1/565H03F3/211H03F3/72
    • Exemplary techniques for performing impedance matching are described. In an exemplary embodiment, the apparatus may include an amplifier (e.g., a power amplifier) coupled to first and second matching circuits. The first matching circuit may include multiple stages coupled to a first node and may provide input impedance matching for the amplifier. The second matching circuit may include multiple stages coupled to a second node and may provide output impedance matching for the amplifier. At least one switch may be coupled between the first and second nodes and may bypass or select the amplifier. The first and second nodes may have a common impedance. The apparatus may further include a second amplifier coupled in parallel with the amplifier and further to the matching circuits. The second matching circuit may include a first input stage coupled to the amplifier, a second input stage coupled to the second amplifier, and a second stage coupled to the two input stages via switches.
    • 描述了用于执行阻抗匹配的示例性技术。 在示例性实施例中,该装置可以包括耦合到第一和第二匹配电路的放大器(例如,功率放大器)。 第一匹配电路可以包括耦合到第一节点的多个级并且可以为放大器提供输入阻抗匹配。 第二匹配电路可以包括耦合到第二节点的多个级并且可以为放大器提供输出阻抗匹配。 至少一个开关可以耦合在第一和第二节点之间,并且可以旁路或选择放大器。 第一和第二节点可以具有公共阻抗。 该装置还可以包括与放大器并联并且进一步耦合到匹配电路的第二放大器。 第二匹配电路可以包括耦合到放大器的第一输入级,耦合到第二放大器的第二输入级,以及经由开关耦合到两个输入级的第二级。