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    • 3. 发明授权
    • Pattern selection for lithographic model calibration
    • 光刻模型校准的图案选择
    • US08694928B2
    • 2014-04-08
    • US12613244
    • 2009-11-05
    • Yu CaoWenjin ShaoJun YeRonaldus Johannes Gljsbertus Goossens
    • Yu CaoWenjin ShaoJun YeRonaldus Johannes Gljsbertus Goossens
    • G06F17/50
    • G06F17/50G03F1/14G03F1/44G03F1/68G03F7/70433G03F7/705G06F17/10G06F17/5009
    • The present invention relates generally to methods and apparatuses for test pattern selection for computational lithography model calibration. According to some aspects, the pattern selection algorithms of the present invention can be applied to any existing pool of candidate test patterns. According to some aspects, the present invention automatically selects those test patterns that are most effective in determining the optimal model parameter values from an existing pool of candidate test patterns, as opposed to designing optimal patterns. According to additional aspects, the selected set of test patterns according to the invention is able to excite all the known physics and chemistry in the model formulation, making sure that the wafer data for the test patterns can drive the model calibration to the optimal parameter values that realize the upper bound of prediction accuracy imposed by the model formulation.
    • 本发明一般涉及用于计算光刻模型校准的测试图案选择的方法和装置。 根据一些方面,本发明的模式选择算法可以应用于任何现有的候选测试模式池。 根据一些方面,与设计最佳图案相反,本发明自动选择从现有的候选测试图案池中确定最佳模型参数值最有效的测试图案。 根据另外的方面,根据本发明的所选择的一组测试图案能够激发模型配方中的所有已知物理和化学,确保用于测试图案的晶片数据可以将模型校准驱动到最佳参数值 实现了模型公式对预测精度的上限。
    • 4. 发明申请
    • PATTERN SELECTION FOR LITHOGRAPHIC MODEL CALIBRATION
    • 图形模型校准的图案选择
    • US20100122225A1
    • 2010-05-13
    • US12613244
    • 2009-11-05
    • Yu CaoWenjin ShaoJun YeRonaldus Johannes Gljsbertus Goossens
    • Yu CaoWenjin ShaoJun YeRonaldus Johannes Gljsbertus Goossens
    • G06F17/50
    • G06F17/50G03F1/14G03F1/44G03F1/68G03F7/70433G03F7/705G06F17/10G06F17/5009
    • The present invention relates generally to methods and apparatuses for test pattern selection for computational lithography model calibration. According to some aspects, the pattern selection algorithms of the present invention can be applied to any existing pool of candidate test patterns. According to some aspects, the present invention automatically selects those test patterns that are most effective in determining the optimal model parameter values from an existing pool of candidate test patterns, as opposed to designing optimal patterns. According to additional aspects, the selected set of test patterns according to the invention is able to excite all the known physics and chemistry in the model formulation, making sure that the wafer data for the test patterns can drive the model calibration to the optimal parameter values that realize the upper bound of prediction accuracy imposed by the model formulation.
    • 本发明一般涉及用于计算光刻模型校准的测试图案选择的方法和装置。 根据一些方面,本发明的模式选择算法可以应用于任何现有的候选测试模式池。 根据一些方面,与设计最佳图案相反,本发明自动选择从现有的候选测试图案池中确定最佳模型参数值最有效的测试图案。 根据另外的方面,根据本发明的所选择的一组测试图案能够激发模型配方中的所有已知物理和化学,确保用于测试图案的晶片数据可以将模型校准驱动到最佳参数值 实现了模型公式对预测精度的上限。
    • 9. 发明申请
    • Computational Process Control
    • 计算过程控制
    • US20120303151A1
    • 2012-11-29
    • US13481564
    • 2012-05-25
    • Jun YeYu CaoJames Patrick Koonmen
    • Jun YeYu CaoJames Patrick Koonmen
    • G05B19/18
    • G03F7/70525B29C64/386G03F9/7096G05B13/04
    • The present invention provides a number of innovations in the area of computational process control (CPC). CPC offers unique diagnostic capability during chip manufacturing cycle by analyzing temporal drift of a lithography apparatus/ process, and provides a solution towards achieving performance stability of the lithography apparatus/process. Embodiments of the present invention enable optimized process windows and higher yields by keeping performance of a lithography apparatus and/or parameters of a lithography process substantially close to a pre-defined baseline condition. This is done by comparing the measured temporal drift to a baseline performance using a lithography process simulation model. Once in manufacturing, CPC optimizes a scanner for specific patterns or reticles by leveraging wafer metrology techniques and feedback loop, and monitors and controls, among other things, overlay and/or CD uniformity (CDU) performance over time to continuously maintain the system close to the baseline condition.
    • 本发明提供了计算过程控制(CPC)领域的许多创新。 CPC通过分析光刻设备/工艺的时间漂移​​,在芯片制造周期中提供独特的诊断功能,并为实现光刻设备/工艺的性能稳定性提供了解决方案。 本发明的实施例通过保持光刻设备的性能和/或基本上接近预定义基线条件的光刻工艺的参数来实现优化的工艺窗口和更高的产量。 这通过使用光刻过程模拟模型将测量的时间漂移​​与基线性能进行比较来完成。 一旦制造,CPC通过利用晶片计量技术和反馈回路来优化扫描仪的特定图案或掩模版,并监控和控制其他方面的重叠和/或CD均匀性(CDU)性能,以持续保持系统接近 基线条件。
    • 10. 发明授权
    • Computational process control
    • 计算过程控制
    • US08856694B2
    • 2014-10-07
    • US13481564
    • 2012-05-25
    • Jun YeYu CaoJames Patrick Koonmen
    • Jun YeYu CaoJames Patrick Koonmen
    • G06F17/50G05B13/04G03F7/20
    • G03F7/70525B29C64/386G03F9/7096G05B13/04
    • The present invention provides a number of innovations in the area of computational process control (CPC). CPC offers unique diagnostic capability during chip manufacturing cycle by analyzing temporal drift of a lithography apparatus/ process, and provides a solution towards achieving performance stability of the lithography apparatus/process. Embodiments of the present invention enable optimized process windows and higher yields by keeping performance of a lithography apparatus and/or parameters of a lithography process substantially close to a pre-defined baseline condition. This is done by comparing the measured temporal drift to a baseline performance using a lithography process simulation model. Once in manufacturing, CPC optimizes a scanner for specific patterns or reticles by leveraging wafer metrology techniques and feedback loop, and monitors and controls, among other things, overlay and/or CD uniformity (CDU) performance over time to continuously maintain the system close to the baseline condition.
    • 本发明提供了计算过程控制(CPC)领域的许多创新。 CPC通过分析光刻设备/工艺的时间漂移​​,在芯片制造周期中提供独特的诊断功能,并为实现光刻设备/工艺的性能稳定性提供了解决方案。 本发明的实施例通过保持光刻设备的性能和/或基本上接近预定义基线条件的光刻工艺的参数来实现优化的工艺窗口和更高的产量。 这通过使用光刻过程模拟模型将测量的时间漂移​​与基线性能进行比较来完成。 一旦制造,CPC通过利用晶片计量技术和反馈回路来优化扫描仪的特定图案或掩模版,以及监视和控制其他方面的覆盖和/或CD均匀性(CDU)性能,以持续保持系统接近 基线条件。