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1. 发明授权

US07488669B2 Method to make markers for double gate SOI processing 失效
标题翻译：制造双栅极SOI处理标记的方法
公开(公告)号：US07488669B2
公开(公告)日：2009-02-10
申请号：US11083356
申请日：2005-03-16
申请人： Josine Johanna Gerarda Petra Loo , Youri V. Ponomarev , David William Laidler
发明人： Josine Johanna Gerarda Petra Loo , Youri V. Ponomarev , David William Laidler
IPC分类号： H01L21/46
CPC分类号： H01L27/0203 , H01L27/1203 , H01L29/78648
摘要： A method of making at least one marker (MX) for double gate SOI processing on a SOI wafer is disclosed. The marker has a diffracting structure in a first direction and the diffracting structure is configured to generate an asymmetrical diffraction pattern during use in an alignment and overlay detection system for detection in the first direction.
摘要翻译：公开了一种在SOI晶片上制造用于双栅极SOI处理的至少一个标记（MX）的方法。标记物在第一方向上具有衍射结构，并且衍射结构被配置为在使用期间在用于在第一方向上检测的对准和覆盖检测系统中产生非对称衍射图案。

2. 发明授权

US07795112B2 Method of fabricating self-aligned source and drain contacts in a double gate FET with controlled manufacturing of a thin Si or non-Si channel 有权
标题翻译：在双栅极FET中制造自对准源极和漏极接触的方法，其中可控制造薄的Si或非Si沟道
公开(公告)号：US07795112B2
公开(公告)日：2010-09-14
申请号：US11093265
申请日：2005-03-28
申请人： Youri V. Ponomarev , Josine Johanna Gerarda Petra Loo
发明人： Youri V. Ponomarev , Josine Johanna Gerarda Petra Loo
IPC分类号： H01L21/30
CPC分类号： B82Y10/00 , H01L21/26506 , H01L29/66575
摘要： A method of forming a transistor structure on a substrate (SOI) is disclosed, wherein the substrate comprises a supporting Si layer, a buried insulating layer, and a top Si layer. The method comprises forming a gate region of the transistor structure on the top Si layer, wherein the gate region is separated from the top Si layer by a dielectric layer, and wherein the top Si layer comprises a high dopant level. The method further comprises forming an open area on the top Si layer demarcated by a demarcating oxide and/or resist layer region, forming high level impurity or heavily-damaged regions by ion implantation, and exposing the open area to an ion beam, wherein the ion beam comprises a combination of beam energy and dose, and wherein the demarcating layer region and the gate region act as an implantation mask.
摘要翻译：公开了一种在衬底（SOI）上形成晶体管结构的方法，其中衬底包括支撑Si层，掩埋绝缘层和顶部Si层。该方法包括在顶部Si层上形成晶体管结构的栅极区域，其中栅极区域通过介电层从顶部Si层分离，并且其中顶部Si层包括高掺杂剂水平。该方法还包括在由分界氧化物和/或抗蚀剂层区域划定的顶部Si层上形成开放区域，通过离子注入形成高级杂质或严重损坏的区域，并将开放区域暴露于离子束，其中离子束包括光束能量和剂量的组合，并且其中分界层区域和栅极区域用作注入掩模。

3. 发明授权

US07829411B2 Method and device to form high quality oxide layers of different thickness in one processing step 有权
标题翻译：在一个加工步骤中形成不同厚度的高品质氧化物层的方法和装置
公开(公告)号：US07829411B2
公开(公告)日：2010-11-09
申请号：US10503046
申请日：2003-01-20
申请人： Josine Johanna Gerarda Petra Loo , Youri Ponomarev , Robertus Theodorus Fransiscus Schaijk
发明人： Josine Johanna Gerarda Petra Loo , Youri Ponomarev , Robertus Theodorus Fransiscus Schaijk
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L21/28273 , H01L21/31662 , H01L21/823462 , H01L21/823468 , H01L27/115 , H01L27/11524 , H01L29/66825
摘要： The present invention relates to a method for forming high quality oxide layers of different thickness over a first and a second semiconductor region in one processing step. The method comprises the steps of: doping the first and the second semiconductor region with a different dopant concentration, and oxidising, during the same processing step, both the first and the second semiconductor region under a temperature between 500° C. and 700° C., preferably between 500° C. and 650° C. A corresponding device is also provided.Using a low-temperature oxidation in combination with high doping levels results in an unexpected oxidation rate increase.
摘要翻译：本发明涉及在一个处理步骤中在第一和第二半导体区域形成不同厚度的高质量氧化物层的方法。该方法包括以下步骤：以不同的掺杂剂浓度掺杂第一和第二半导体区域，并且在相同的处理步骤期间，在500℃和700℃之间的温度下氧化第一和第二半导体区域优选在500℃和650℃之间。还提供了相应的装置。结合高掺杂水平使用低温氧化会导致意想不到的氧化速率增加。

4. 发明授权

US07772646B2 Method of manufacturing a semiconductor device and such a semiconductor device 有权
标题翻译：制造半导体器件和这种半导体器件的方法
公开(公告)号：US07772646B2
公开(公告)日：2010-08-10
申请号：US11574338
申请日：2005-08-10
申请人： Josine Johanna Gerarda Petra Loo , Vincent Charles Venezia , Youri Ponomarev
发明人： Josine Johanna Gerarda Petra Loo , Vincent Charles Venezia , Youri Ponomarev
IPC分类号： H01L29/78 , H01L21/84
CPC分类号： H01L21/76243 , Y10S438/981
摘要： There is a method of manufacturing a semiconductor device with a semiconductor body comprising a semiconductor substrate and a semiconductor region which are separated from each other with an electrically insulating layer which includes a first and a second sub-layer which, viewed in projection, are adjacent to one another, wherein the first sub-layer has a smaller thickness than the second sub-layer, and wherein, in a first sub-region of the semiconductor region lying above the first sub-layer, at least one digital semiconductor element is formed and, in a second sub-region of the semiconductor region lying above the second sub-layer, at least one analog semiconductor element is formed.According to an example embodiment, the second sub-layer is formed in that the lower border thereof is recessed in the semiconductor body in relation to the lower border of the first sub-layer Fully depleted SOI devices are thus formed.
摘要翻译：制造具有半导体本体的半导体器件的方法，该半导体器件包括半导体衬底和半导体区域，该半导体衬底和半导体区域由电绝缘层彼此分离，所述电绝缘层包括第一和第二子层，该第一子层和第二子层在投影中是相邻的其中，所述第一子层的厚度小于所述第二子层的厚度，并且其中，在位于所述第一子层之上的所述半导体区域的第一子区域中，形成至少一个数字半导体元件并且在位于第二子层上方的半导体区域的第二子区域中，形成至少一个模拟半导体元件。根据示例实施例，第二子层形成为其下边界相对于第一子层的下边界凹陷在半导体本体中。因此形成完全耗尽的SOI器件。

5. 发明申请

US20090166799A1 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SUCH A SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法及其半导体器件
公开(公告)号：US20090166799A1
公开(公告)日：2009-07-02
申请号：US11574338
申请日：2005-08-10
申请人： Josine Johanna Gerarda Petra Loo , Vincent Charles Venezia , Youri Ponomarev
发明人： Josine Johanna Gerarda Petra Loo , Vincent Charles Venezia , Youri Ponomarev
IPC分类号： H01L29/66 , H01L21/322
CPC分类号： H01L21/76243 , Y10S438/981
摘要： The invention relates to a method of manufacturing a semiconductor device (10) with a semiconductor body (1) comprising a semiconductor substrate (2) and a semiconductor region (3) which are separated from each other by means of an electrically insulating layer (4) which comprises a first and second sublayer (4A, 4B) that are viewed in projection adjacent to each other, whereby the first sublayer (4A) is provided with a smaller thickness than the second sublayer (4B) and whereby in a first subregion (3B) of the semiconductor region (3) lying above the first sublayer (4A) at least one digital semiconductor element (5) is formed and in a second subregion (3B) of the semiconductor region (3) lying above the second sublayer (4B) at least one analogue semiconductor element (6) is formed.According to the invention the second sublayer (4B) is formed in such a way that the lower border thereof is in relation to the lower border of the first sublayer (4A) formed sunken in the semiconductor body (1). In this way the formation of so called FD (=Fully Depleted) SOI devices (10) is made easy. Preferably, the sublayers (4A, 4B) are formed using a thermal oxidation that is locally enhanced or retarded (prevented). The semiconductor region (3) is preferably formed by using a substrate transfer technique.
摘要翻译：本发明涉及一种制造具有半导体本体（1）的半导体器件（10）的方法，半导体器件（1）包括通过电绝缘层（4）彼此分离的半导体衬底（2）和半导体区域（3）），其包括在彼此相邻的突起中观察的第一和第二子层（4A，4B），由此所述第一子层（4A）设置有比所述第二子层（4B）更小的厚度，并且由此在第一子区域如图3B所示，位于第一子层（4A）上方的半导体区域（3）形成至少一个数字半导体元件（5），并且位于第二子层（4B）上方的半导体区域（3）的第二子区域（3B））形成至少一个模拟半导体元件（6）。根据本发明，第二子层（4B）以这样的方式形成，使得其下边界相对于形成在半导体本体（1）中凹陷的第一子层（4A）的下边界。以这种方式，使得所谓的FD（=完全耗尽）SOI器件（10）的形成变得容易。优选地，使用局部增强或延迟（防止）的热氧化形成子层（4A，4B）。半导体区域（3）优选通过使用基板转印技术形成。

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